1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __GXBB_H__ 8*4882a593Smuzhiyun #define __GXBB_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define GXBB_PERIPHS_BASE 0xc8834400 11*4882a593Smuzhiyun #define GXBB_HIU_BASE 0xc883c000 12*4882a593Smuzhiyun #define GXBB_ETH_BASE 0xc9410000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Peripherals registers */ 15*4882a593Smuzhiyun #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2)) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* GPIO registers 0 to 6 */ 18*4882a593Smuzhiyun #define _GXBB_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n)) 19*4882a593Smuzhiyun #define GXBB_GPIO_EN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0) 20*4882a593Smuzhiyun #define GXBB_GPIO_IN(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1) 21*4882a593Smuzhiyun #define GXBB_GPIO_OUT(n) GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define GXBB_ETH_REG_0 GXBB_PERIPHS_ADDR(0x50) 24*4882a593Smuzhiyun #define GXBB_ETH_REG_1 GXBB_PERIPHS_ADDR(0x51) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define GXBB_ETH_REG_0_PHY_INTF BIT(0) 27*4882a593Smuzhiyun #define GXBB_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5) 28*4882a593Smuzhiyun #define GXBB_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7) 29*4882a593Smuzhiyun #define GXBB_ETH_REG_0_PHY_CLK_EN BIT(10) 30*4882a593Smuzhiyun #define GXBB_ETH_REG_0_CLK_EN BIT(12) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* HIU registers */ 33*4882a593Smuzhiyun #define GXBB_HIU_ADDR(off) (GXBB_HIU_BASE + ((off) << 2)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define GXBB_MEM_PD_REG_0 GXBB_HIU_ADDR(0x40) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Ethernet memory power domain */ 38*4882a593Smuzhiyun #define GXBB_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Clock gates */ 41*4882a593Smuzhiyun #define GXBB_GCLK_MPEG_0 GXBB_HIU_ADDR(0x50) 42*4882a593Smuzhiyun #define GXBB_GCLK_MPEG_1 GXBB_HIU_ADDR(0x51) 43*4882a593Smuzhiyun #define GXBB_GCLK_MPEG_2 GXBB_HIU_ADDR(0x52) 44*4882a593Smuzhiyun #define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53) 45*4882a593Smuzhiyun #define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define GXBB_GCLK_MPEG_1_ETH BIT(3) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif /* __GXBB_H__ */ 50