Home
last modified time | relevance | path

Searched +full:0 +full:x35000000 (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/u-boot/board/hisilicon/hikey/
H A DREADME87 2. Once LED 0 comes on solid, HiKey board should be detected as a fastboot device by plugging a USB…
114 Switch to aarch64 mode. CPU0 executes at 0xf9801000!
116 INFO: BL1: 0xf9810000 - 0xf9817000 [size = 28672]
120 INFO: BL1: RAM 0xf9810000 - 0xf9817000
130 INFO: ddr test value:0xa5a55a5a
133 INFO: Loading file 'bl2.bin' at address 0xf9818000
134 INFO: File 'bl2.bin' loaded: 0xf9818000 - 0xf9821100
136 INFO: BL1: BL2 address = 0xf9818000
137 INFO: BL1: BL2 spsr = 0x3c5
138 INFO: [BDID] [fff91c18] midr: 0x410fd033
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Dhikey.h27 #define CONFIG_SYS_TEXT_BASE 0x35000000
30 #define PHYS_SDRAM_1 0x00000000
33 #define PHYS_SDRAM_1_SIZE 0x3EFFFFFF
37 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
39 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
41 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
47 #define GICD_BASE 0xf6801000
48 #define GICC_BASE 0xf6802000
57 #define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000
85 func(USB, usb, 0) \
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/4xx/
H A Dpci.c39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
50 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) in ppc440spe_revA()
53 return 0; in ppc440spe_revA()
61 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
81 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { in fixup_ppc4xx_pci_bridge()
82 dev->resource[i].start = dev->resource[i].end = 0; in fixup_ppc4xx_pci_bridge()
83 dev->resource[i].flags = 0; in fixup_ppc4xx_pci_bridge()
102 res->start = 0; in ppc4xx_parse_dma_ranges()
103 size = 0x80000000; in ppc4xx_parse_dma_ranges()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/ti/
H A Dk3-udma.yaml53 for source thread IDs (rx): 0 - 0x7fff
54 for destination thread IDs (tx): 0x8000 - 0xffff
158 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
164 reg = <0x0 0x31150000 0x0 0x100>,
165 <0x0 0x34000000 0x0 0x100000>,
166 <0x0 0x35000000 0x0 0x100000>;
177 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
178 <0x2>; /* TX_CHAN */
179 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
180 <0x5>; /* RX_CHAN */
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/platforms/cell/spufs/
H A Dspu_save_dump.h_shipped7 0x20805000,
8 0x20805201,
9 0x20805402,
10 0x20805603,
11 0x20805804,
12 0x20805a05,
13 0x20805c06,
14 0x20805e07,
15 0x20806008,
16 0x20806209,
[all …]
H A Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x40200000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/include/asm/
H A Dinsn.h22 * 0 0 - - Unallocated
23 * 1 0 0 - Data processing, immediate
24 * 1 0 1 - Branch, exception generation and system instructions
25 * - 1 - 0 Loads and stores
26 * - 1 0 1 Data processing - register
27 * 0 1 1 1 Data processing - SIMD and floating point
42 AARCH64_INSN_HINT_NOP = 0x0 << 5,
43 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
44 AARCH64_INSN_HINT_WFE = 0x2 << 5,
45 AARCH64_INSN_HINT_WFI = 0x3 << 5,
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-j7200-main.dtsi11 reg = <0x00 0x70000000 0x00 0x100000>;
14 ranges = <0x00 0x00 0x70000000 0x100000>;
16 atf-sram@0 {
17 reg = <0x00 0x20000>;
23 reg = <0x00 0x00100000 0x00 0x1c000>;
26 ranges = <0x00 0x00 0x00100000 0x1c000>;
31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
[all …]
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-j721e-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
19 #clock-cells = <0>;
21 clock-frequency = <0>;
28 reg = <0x0 0x70000000 0x0 0x800000>;
31 ranges = <0x0 0x0 0x70000000 0x800000>;
33 atf-sram@0 {
34 reg = <0x0 0x20000>;
40 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
43 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
/OK3568_Linux_fs/kernel/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/OK3568_Linux_fs/kernel/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h130 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0
132 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */
162 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
164 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
166 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
285 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
287 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
[all …]