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/OK3568_Linux_fs/kernel/drivers/staging/media/hantro/
H A Drk3399_vpu_regs.h13 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
14 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
15 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
16 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
17 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
18 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
19 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
20 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
21 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
22 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
H A Dhantro_postproc.c29 #define VPU_PP_IN_YUYV 0x0
30 #define VPU_PP_IN_NV12 0x1
31 #define VPU_PP_IN_YUV420 0x2
32 #define VPU_PP_IN_YUV240_TILED 0x5
33 #define VPU_PP_OUT_RGB 0x0
34 #define VPU_PP_OUT_YUYV 0x3
37 .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
38 .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
39 .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
40 .out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1},
[all …]
/OK3568_Linux_fs/external/mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_reg_tbl.h25 #define VEPU_REG_VP8_QUT_1ST(i) (0x000 + ((i) * 0x24))
26 #define VEPU_REG_VP8_QUT_DC_Y2(x) (((x) & 0x3fff) << 16)
27 #define VEPU_REG_VP8_QUT_DC_Y1(x) (((x) & 0x3fff) << 0)
28 #define VEPU_REG_VP8_QUT_2ND(i) (0x004 + ((i) * 0x24))
29 #define VEPU_REG_VP8_QUT_AC_Y1(x) (((x) & 0x3fff) << 16)
30 #define VEPU_REG_VP8_QUT_DC_CHR(x) (((x) & 0x3fff) << 0)
31 #define VEPU_REG_VP8_QUT_3RD(i) (0x008 + ((i) * 0x24))
32 #define VEPU_REG_VP8_QUT_AC_CHR(x) (((x) & 0x3fff) << 16)
33 #define VEPU_REG_VP8_QUT_AC_Y2(x) (((x) & 0x3fff) << 0)
34 #define VEPU_REG_VP8_QUT_4TH(i) (0x00c + ((i) * 0x24))
[all …]
/OK3568_Linux_fs/kernel/drivers/dma/ti/
H A Dk3-udma.h12 #define UDMA_REV_REG 0x0
13 #define UDMA_PERF_CTL_REG 0x4
14 #define UDMA_EMU_CTL_REG 0x8
15 #define UDMA_PSIL_TO_REG 0x10
16 #define UDMA_UTC_CTL_REG 0x1c
17 #define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
18 #define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
19 #define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
22 #define UDMA_CHAN_RT_CTL_REG 0x0
23 #define UDMA_CHAN_RT_SWTRIG_REG 0x8
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/thermal/
H A Dthermal-sensor.yaml35 0 on sensor nodes with only a single sensor and at least 1 on nodes
37 enum: [0, 1]
54 reg = <0 0x0c263000 0 0x1ff>, /* TM */
55 <0 0x0c222000 0 0x1ff>; /* SROT */
65 reg = <0 0x0c265000 0 0x1ff>, /* TM */
66 <0 0x0c223000 0 0x1ff>; /* SROT */
/OK3568_Linux_fs/kernel/drivers/gpu/host1x/hw/
H A Dhw_host1x01_sync.h29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/rkvdec/
H A Drkvdec-regs.h7 #define RKVDEC_REG_INTERRUPT 0x004
8 #define RKVDEC_INTERRUPT_DEC_E BIT(0)
32 #define RKVDEC_REG_SYSCTRL 0x008
33 #define RKVDEC_IN_ENDIAN BIT(0)
44 #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
45 #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
55 #define RKVDEC_REG_PICPAR 0x00C
56 #define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff)
58 #define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12)
59 #define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21)
[all …]
/OK3568_Linux_fs/kernel/drivers/thermal/tegra/
H A Dtegra210-soctherm.c24 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31)
25 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
26 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
27 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
28 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
29 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
30 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
31 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
33 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
34 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drockchip_vop_reg.c29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
[all …]
/OK3568_Linux_fs/kernel/drivers/net/dsa/
H A Dbcm_sf2_regs.h13 REG_SWITCH_CNTRL = 0,
30 #define MDIO_MASTER_SEL (1 << 0)
33 #define SF2_REV_MASK 0xffff
35 #define SWITCH_TOP_REV_MASK 0xffff
38 #define PHY_REVISION_MASK 0xffff
41 #define IDDQ_BIAS (1 << 0)
48 #define PHY_PHYAD_MASK 0x1F
53 #define RGMII_MODE_EN (1 << 0)
56 #define INT_EPHY (0 << PORT_MODE_SHIFT)
61 #define PORT_MODE_MASK 0x7
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dmc.h15 #define MC_INTSTATUS 0x00
16 #define MC_INTMASK 0x04
17 #define MC_ERR_STATUS 0x08
18 #define MC_ERR_ADR 0x0c
19 #define MC_GART_ERROR_REQ 0x30
20 #define MC_EMEM_ADR_CFG 0x54
21 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58
22 #define MC_SECURITY_VIOLATION_STATUS 0x74
23 #define MC_EMEM_ARB_CFG 0x90
24 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/mac_ax/
H A Dfwcmd_intf_f2p.h21 #define FWCMD_F2PTEST_ULBW_SH 0
22 #define FWCMD_F2PTEST_ULBW_MSK 0x3
24 #define FWCMD_F2PTEST_GILTF_MSK 0x3
26 #define FWCMD_F2PTEST_NUMLTF_MSK 0x7
28 #define FWCMD_F2PTEST_ULSTBC_MSK 0x1
30 #define FWCMD_F2PTEST_DPLR_MSK 0x1
32 #define FWCMD_F2PTEST_TXPWR_MSK 0x3F
34 #define FWCMD_F2PTEST_USERNUM_MSK 0x7
36 #define FWCMD_F2PTEST_PKTNUM_MSK 0x7
38 #define FWCMD_F2PTEST_BITMAP_MSK 0xFF
[all …]
H A Dmac_txccxrpt.h5 #define TXCCXRPT_RPT_SEL_SH 0
6 #define TXCCXRPT_RPT_SEL_MSK 0x1f
9 #define TXCCXRPT_TX_STATE_MSK 0x3
11 #define TXCCXRPT_SW_DEFINE_MSK 0xf
15 #define TXCCXRPT_MACID_MSK 0x7f
17 #define TXCCXRPT_QSEL_MSK 0x3f
21 #define TXCCXRPT_QUEUE_TIME_SH 0
22 #define TXCCXRPT_QUEUE_TIME_MSK 0xffff
24 #define TXCCXRPT_ACCTXTIME_MSK 0xff
27 #define TXCCXRPT_BITMAP_SHORT_MSK 0x3
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/mac_ax/
H A Dfwcmd_intf_f2p.h21 #define FWCMD_F2PTEST_ULBW_SH 0
22 #define FWCMD_F2PTEST_ULBW_MSK 0x3
24 #define FWCMD_F2PTEST_GILTF_MSK 0x3
26 #define FWCMD_F2PTEST_NUMLTF_MSK 0x7
28 #define FWCMD_F2PTEST_ULSTBC_MSK 0x1
30 #define FWCMD_F2PTEST_DPLR_MSK 0x1
32 #define FWCMD_F2PTEST_TXPWR_MSK 0x3F
34 #define FWCMD_F2PTEST_USERNUM_MSK 0x7
36 #define FWCMD_F2PTEST_PKTNUM_MSK 0x7
38 #define FWCMD_F2PTEST_BITMAP_MSK 0xFF
[all …]
H A Dmac_txccxrpt.h5 #define TXCCXRPT_RPT_SEL_SH 0
6 #define TXCCXRPT_RPT_SEL_MSK 0x1f
9 #define TXCCXRPT_TX_STATE_MSK 0x3
11 #define TXCCXRPT_SW_DEFINE_MSK 0xf
15 #define TXCCXRPT_MACID_MSK 0x7f
17 #define TXCCXRPT_QSEL_MSK 0x3f
21 #define TXCCXRPT_QUEUE_TIME_SH 0
22 #define TXCCXRPT_QUEUE_TIME_MSK 0xffff
24 #define TXCCXRPT_ACCTXTIME_MSK 0xff
27 #define TXCCXRPT_BITMAP_SHORT_MSK 0x3
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dau1200fb.h33 #define AU1200_LCD_ADDR 0xB5000000
64 uint32 reserved2[(0x0100-0x0058)/4];
77 uint32 reserved3[(0x0400-0x0180)/4];
79 volatile uint32 palette[(0x0800-0x0400)/4];
86 #define LCD_SCREEN_SX (0x07FF<<19)
87 #define LCD_SCREEN_SY (0x07FF<< 8)
90 #define LCD_SCREEN_PT (7<<0)
91 #define LCD_SCREEN_PT_TFT (0<<0)
94 #define LCD_SCREEN_PT_CSTN (1<<0)
95 #define LCD_SCREEN_PT_CDSTN (2<<0)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/ipu-v3/
H A Dipu-ic.c18 #define IC_CONF 0x0000
19 #define IC_PRP_ENC_RSC 0x0004
20 #define IC_PRP_VF_RSC 0x0008
21 #define IC_PP_RSC 0x000C
22 #define IC_CMBP_1 0x0010
23 #define IC_CMBP_2 0x0014
24 #define IC_IDMAC_1 0x0018
25 #define IC_IDMAC_2 0x001C
26 #define IC_IDMAC_3 0x0020
27 #define IC_IDMAC_4 0x0024
[all …]
/OK3568_Linux_fs/kernel/drivers/mtd/nand/raw/ingenic/
H A Djz4740_ecc.c19 #define JZ_REG_NAND_ECC_CTRL 0x00
20 #define JZ_REG_NAND_DATA 0x04
21 #define JZ_REG_NAND_PAR0 0x08
22 #define JZ_REG_NAND_PAR1 0x0C
23 #define JZ_REG_NAND_PAR2 0x10
24 #define JZ_REG_NAND_IRQ_STAT 0x14
25 #define JZ_REG_NAND_IRQ_CTRL 0x18
26 #define JZ_REG_NAND_ERR(x) (0x1C + ((x) << 2))
32 #define JZ_NAND_ECC_CTRL_ENABLE BIT(0)
39 #define JZ_NAND_STATUS_ERROR BIT(0)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/davinci/
H A Dvpbe_osd_regs.h9 #define VPBE_PID 0x0
10 #define VPBE_PCR 0x4
13 #define VPSSCLK_PID 0x00
14 #define VPSSCLK_CLKCTRL 0x04
17 #define VPSSBL_PID 0x00
18 #define VPSSBL_PCR 0x04
19 #define VPSSBL_BCR 0x08
20 #define VPSSBL_INTSTAT 0x0C
21 #define VPSSBL_INTSEL 0x10
22 #define VPSSBL_EVTSEL 0x14
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/
H A Dtxdesc.h23 #define AX_TXD_WP_OFFSET_MSK 0xff
29 #define AX_TXD_CH_DMA_MSK 0xf
31 #define AX_TXD_HDR_LLC_LEN_MSK 0x1f
40 #define AX_TXD_HW_SSN_SEL_MSK 0x3
41 #define AX_TXD_EN_HWSEQ_MODE_SH 0
42 #define AX_TXD_EN_HWSEQ_MODE_MSK 0x3
46 #define AX_TXD_PLD_MSK 0xffff
48 #define AX_TXD_DMA_TXAGG_NUM_MSK 0xff
49 #define AX_TXD_SHCUT_CAMID_SH 0
50 #define AX_TXD_SHCUT_CAMID_MSK 0xff
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/
H A Dtxdesc.h23 #define AX_TXD_WP_OFFSET_MSK 0xff
29 #define AX_TXD_CH_DMA_MSK 0xf
31 #define AX_TXD_HDR_LLC_LEN_MSK 0x1f
40 #define AX_TXD_HW_SSN_SEL_MSK 0x3
41 #define AX_TXD_EN_HWSEQ_MODE_SH 0
42 #define AX_TXD_EN_HWSEQ_MODE_MSK 0x3
46 #define AX_TXD_PLD_MSK 0xffff
48 #define AX_TXD_DMA_TXAGG_NUM_MSK 0xff
49 #define AX_TXD_SHCUT_CAMID_SH 0
50 #define AX_TXD_SHCUT_CAMID_MSK 0xff
[all …]
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/drx39xyj/
H A Ddrxj_map.h37 * Generated by: IDF:x 1.3.0
56 #define ATV_COMM_EXEC__A 0xC00000
58 #define ATV_COMM_EXEC__M 0x3
59 #define ATV_COMM_EXEC__PRE 0x0
60 #define ATV_COMM_EXEC_STOP 0x0
61 #define ATV_COMM_EXEC_ACTIVE 0x1
62 #define ATV_COMM_EXEC_HOLD 0x2
64 #define ATV_COMM_STATE__A 0xC00001
66 #define ATV_COMM_STATE__M 0xFFFF
67 #define ATV_COMM_STATE__PRE 0x0
[all …]
/OK3568_Linux_fs/external/mpp/mpp/hal/rkdec/avsd/
H A Dhal_avsd_vdpu1.c36 p_regs->sw02.dec_in_endian = 0; in set_defalut_parameters()
39 p_regs->sw02.dec_scmd_dis = 0; in set_defalut_parameters()
41 p_regs->sw02.dec_adv_pre_dis = 0; in set_defalut_parameters()
43 p_regs->sw02.dec_latency = 0; in set_defalut_parameters()
45 p_regs->sw02.dec_data_disc_e = 0; in set_defalut_parameters()
50 p_regs->sw02.dec_timeout_e = 0; in set_defalut_parameters()
52 p_regs->sw01.dec_irq_dis = 0; in set_defalut_parameters()
54 p_regs->sw02.dec_axi_rd_id = 0xFF; in set_defalut_parameters()
55 p_regs->sw03.dec_axi_wr_id = 0; in set_defalut_parameters()
57 p_regs->sw49.pred_bc_tap_0_0 = 0x3FF; in set_defalut_parameters()
[all …]
H A Dhal_avsd_vdpu2.c36 p_regs->sw54.dec_in_endian = 0; in set_defalut_parameters()
39 p_regs->sw50.dec_ascmd0_dis = 0; in set_defalut_parameters()
41 p_regs->sw50.adv_pref_dis = 0; in set_defalut_parameters()
43 p_regs->sw50.adtion_latency = 0; in set_defalut_parameters()
45 p_regs->sw56.dec_data_discd_en = 0; in set_defalut_parameters()
49 p_regs->sw55.timeout_det_sts = 0; in set_defalut_parameters()
51 p_regs->sw55.dec_irq_dis = 0; in set_defalut_parameters()
53 p_regs->sw56.dec_axi_id_rd = 0xFF; in set_defalut_parameters()
54 p_regs->sw56.dec_axi_id_wr = 0; in set_defalut_parameters()
56 p_regs->sw59.pred_bc_tap_0_0 = 0x3FF; in set_defalut_parameters()
[all …]
/OK3568_Linux_fs/u-boot/tools/
H A Datmelimage.c63 for (pos = 0; pos < ARRAY_SIZE(configs); pos++) { in atmel_find_pmecc_parameter_in_token()
64 if (strncmp(token, configs[pos], strlen(configs[pos])) == 0) { in atmel_find_pmecc_parameter_in_token()
73 case 0: in atmel_find_pmecc_parameter_in_token()
123 for (pos = 0; pos < ARRAY_SIZE(nand_pmecc_header); pos++) in atmel_verify_header()
124 if (ints[pos] >> 28 != 0xC) in atmel_verify_header()
133 for (pos = 0; pos < 7; pos++) { in atmel_verify_header()
134 debug("atmelimage: interrupt vector #%zu is 0x%08X\n", pos+1, in atmel_verify_header()
143 if ((ints[pos] & 0xff000000) == 0xea000000) in atmel_verify_header()
146 if ((ints[pos] & 0xfffff000) == 0xe59ff000) in atmel_verify_header()
147 /* valid LDR (I=0, P=1, U=1, B=0, W=0, L=1) */ in atmel_verify_header()
[all …]

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