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/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dcpu.h11 #define DEVICE_NOT_AVAILABLE 0
14 #define EXYNOS4_ADDR_BASE 0x10000000
17 #define EXYNOS4_I2C_SPACING 0x10000
19 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
20 #define EXYNOS4_PRO_ID 0x10000000
21 #define EXYNOS4_SYSREG_BASE 0x10010000
22 #define EXYNOS4_POWER_BASE 0x10020000
23 #define EXYNOS4_SWRESET 0x10020400
24 #define EXYNOS4_CLOCK_BASE 0x10030000
25 #define EXYNOS4_SYSTIMER_BASE 0x10050000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dsynopsys-dw-mshc.yaml51 reg = <0x12200000 0x1000>;
52 interrupts = <0 75 0>;
61 #size-cells = <0>;
69 data-addr = <0x200>;
70 fifo-depth = <0x80>;
H A Dexynos-dw-mshc.txt28 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
52 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
53 phase shift clocks should be 0.
74 reg = <0x12200000 0x1000>;
75 interrupts = <0 75 0>;
77 #size-cells = <0>;
84 fifo-depth = <0x80>;
89 samsung,dw-mshc-hs400-timing = <0 2>;
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dexynos5.dtsi19 reg = <0x10440000 0x1000>;
20 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
21 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
22 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
23 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
24 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
25 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
26 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
27 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
34 reg = <0x10481000 0x1000>,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dexynos5410.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
43 reg = <0x1>;
50 reg = <0x2>;
57 reg = <0x3>;
70 reg = <0x10040000 0x5000>;
78 reg = <0x10010000 0x30000>;
84 reg = <0x03810000 0x0C>;
92 reg = <0x10060000 0x100>;
[all …]
H A Dqcom-msm8660.dtsi18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0>;
44 reg = <0x0 0x0>;
49 interrupts = <1 9 0x304>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
79 io-channels = <&xoadc 0x00 0x01>, /* Battery */
80 <&xoadc 0x00 0x02>, /* DC in (charger) */
[all …]
H A Dexynos5250.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0>;
169 reg = <0x02020000 0x30000>;
172 ranges = <0 0x02020000 0x30000>;
174 smp-sram@0 {
176 reg = <0x0 0x1000>;
181 reg = <0x2f000 0x1000>;
187 reg = <0x10044000 0x20>;
188 #power-domain-cells = <0>;
[all …]
H A Dexynos5420.dtsi162 reg = <0x10d20000 0x1000>;
163 ranges = <0x0 0x10d20000 0x6000>;
168 reg = <0x4000 0x1000>;
173 reg = <0x5000 0x1000>;
179 reg = <0x10010000 0x30000>;
185 reg = <0x03810000 0x0C>;
195 reg = <0x11000000 0x10000>;
208 #size-cells = <0>;
209 reg = <0x12200000 0x2000>;
212 fifo-depth = <0x40>;
[all …]