arm/dts/exynos5.dtsi

19 		reg = <0x10440000 0x1000>;
20 		interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
21 				<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
22 				<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
23 				<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
24 				<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
25 				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
26 				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
27 				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
34 		reg =	<0x10481000 0x1000>,
35 			<0x10482000 0x1000>,
36 			<0x10484000 0x2000>,
37 			<0x10486000 0x2000>;
38 		interrupts = <1 9 0xf04>;
43 		reg = <0x12250000 0x20>;
45 		#size-cells = <0>;
53 		reg = <0x10440000 0x1000>;
54 		interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
55 				<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
56 				<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
57 				<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
58 				<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
59 				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
60 				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
61 				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
68 		reg =	<0x10481000 0x1000>,
69 			<0x10482000 0x1000>,
70 			<0x10484000 0x2000>,
71 			<0x10486000 0x2000>;
72 		interrupts = <1 9 0xf04>;
77 		reg = <0x12C60000 0x100>;
78 		interrupts = <0 56 0>;
80 		#size-cells = <0>;
85 		reg = <0x12C70000 0x100>;
86 		interrupts = <0 57 0>;
88 		#size-cells = <0>;
93 		reg = <0x12C80000 0x100>;
94 		interrupts = <0 58 0>;
96 		#size-cells = <0>;
101 		reg = <0x12C90000 0x100>;
102 		interrupts = <0 59 0>;
104 		#size-cells = <0>;
109 		#size-cells = <0>;
111 		reg = <0x12d20000 0x30>;
112 		interrupts = <0 68 0>;
117 		#size-cells = <0>;
119 		reg = <0x12d30000 0x30>;
120 		interrupts = <0 69 0>;
125 		#size-cells = <0>;
127 		reg = <0x12d40000 0x30>;
129 		interrupts = <0 70 0>;
134 		#size-cells = <0>;
136 		reg = <0x131a0000 0x30>;
137 		interrupts = <0 129 0>;
142 		#size-cells = <0>;
144 		reg = <0x131b0000 0x30>;
145 		interrupts = <0 130 0>;
150 		reg = <0x12110000 0x100>;
156 			reg = <0x12130000 0x100>;
162 		reg = <0x10060000 0x10000>;
168 		reg = <0x14400000 0x10000>;
175 		reg = <0x145b0000 0x1000>;
182 		reg = <0x12000000 0x10000>;
188 			reg = <0x12100000 0x100>;
194 		#size-cells = <0>;
196 		reg = <0x12200000 0x1000>;
197 		interrupts = <0 75 0>;
202 		#size-cells = <0>;
204 		reg = <0x12210000 0x1000>;
205 		interrupts = <0 76 0>;
210 		#size-cells = <0>;
212 		reg = <0x12220000 0x1000>;
213 		interrupts = <0 77 0>;
218 		#size-cells = <0>;
220 		reg = <0x12230000 0x1000>;
221 		interrupts = <0 78 0>;
226 		reg = <0x12C00000 0x100>;
227 		interrupts = <0 51 0>;
228 		id = <0>;
233 		reg = <0x12C10000 0x100>;
234 		interrupts = <0 52 0>;
240 		reg = <0x12C20000 0x100>;
241 		interrupts = <0 53 0>;
247 		reg = <0x12C30000 0x100>;
248 		interrupts = <0 54 0>;