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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_sh_mask.h26 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x03ffffffL
27 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x00000000
28 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x000003f0L
29 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x00000004
30 #define GPIOPAD_A__GPIO_A_MASK 0x7fffffffL
31 #define GPIOPAD_A__GPIO_A__SHIFT 0x00000000
32 #define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffffL
33 #define GPIOPAD_EN__GPIO_EN__SHIFT 0x00000000
34 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x00000020L
35 #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x00000005
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L
27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000
28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L
29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001
30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL
31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002
32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002
34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L
35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL
27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000
28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL
29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000
30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L
31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008
32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L
33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000
34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L
35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
H A Dtegra124-apalis-emc.dtsi94 nvidia,emc-auto-cal-config = <0xa1430000>;
95 nvidia,emc-auto-cal-config2 = <0x00000000>;
96 nvidia,emc-auto-cal-config3 = <0x00000000>;
97 nvidia,emc-auto-cal-interval = <0x001fffff>;
98 nvidia,emc-bgbias-ctl0 = <0x00000008>;
99 nvidia,emc-cfg = <0x73240000>;
100 nvidia,emc-cfg-2 = <0x000008c5>;
101 nvidia,emc-ctt-term-ctrl = <0x00000802>;
102 nvidia,emc-mode-1 = <0x80100003>;
103 nvidia,emc-mode-2 = <0x80200008>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi89 nvidia,emc-auto-cal-config = <0xa1430000>;
90 nvidia,emc-auto-cal-config2 = <0x00000000>;
91 nvidia,emc-auto-cal-config3 = <0x00000000>;
92 nvidia,emc-auto-cal-interval = <0x001fffff>;
93 nvidia,emc-bgbias-ctl0 = <0x00000008>;
94 nvidia,emc-cfg = <0x73240000>;
95 nvidia,emc-cfg-2 = <0x000008c5>;
96 nvidia,emc-ctt-term-ctrl = <0x00000802>;
97 nvidia,emc-mode-1 = <0x80100003>;
98 nvidia,emc-mode-2 = <0x80200008>;
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/media/rkisp1/
H A Drkisp1-regs.h12 #define RKISP1_CIF_ISP_CTRL_ISP_ENABLE BIT(0)
13 #define RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
32 #define RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
35 #define RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
40 #define RKISP1_CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
44 #define RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
47 #define RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
54 #define RKISP1_CIF_VI_DPCL_DMA_JPEG (0 << 0)
55 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI BIT(0)
56 #define RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
[all …]
/OK3568_Linux_fs/kernel/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c29 0xffffffffffffffff,
30 0xffffffffffffffff,
31 0xffffffffffffffff,
32 0xffffffffffffffff,
33 0xffffffffffffffff,
34 0xffffffffffffffff,
37 0x00000000
43 0x8001ffffffffffff,
44 0xffffffffffffffff,
45 0xffffffffffffffff,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk_sdmmc_handoff.dtsi58 0 /* Field: vco0.psrc */
61 0 /* Field: mpuclk */
62 0 /* Field: mpuclk.cnt */
63 0 /* Field: mpuclk.src */
64 0 /* Field: nocclk */
65 0 /* Field: nocclk.cnt */
66 0 /* Field: nocclk.src */
73 0 /* Field: cntr7clk.src */
76 0 /* Field: cntr9clk.src */
78 0 /* Field: nocdiv.l4mainclk */
[all …]
H A Drk3399-sdram-ddr3-4G-1600.dtsi9 0x2
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-ddr3-1866.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-ddr3-1600.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
H A Drk3399-sdram-lpddr4-100.dtsi6 0x2
7 0xa
8 0x3
9 0x2
10 0x1
11 0x0
12 0xf
13 0xf
14 0
15 0
[all …]
H A Drk3399-sdram-ddr3-1333.dtsi9 0x1
10 0xa
11 0x3
12 0x2
13 0x1
14 0x0
15 0xf
16 0xf
17 0
18 0
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/mb862xx/
H A Dmb862xx_reg.h9 #define MB862XX_MMIO_BASE 0x01fc0000
10 #define MB862XX_MMIO_HIGH_BASE 0x03fc0000
11 #define MB862XX_I2C_BASE 0x0000c000
12 #define MB862XX_DISP_BASE 0x00010000
13 #define MB862XX_CAP_BASE 0x00018000
14 #define MB862XX_DRAW_BASE 0x00030000
15 #define MB862XX_GEO_BASE 0x00038000
16 #define MB862XX_PIO_BASE 0x00038000
17 #define MB862XX_MMIO_SIZE 0x40000
20 #define GC_IST 0x00000020
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/hal/phydm/rtl8188e/
H A Dhalhwimg8188e_mac.c31 u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ in check_positive()
42 u8 pkg_type_for_para = (dm->package_type == 0) ? 15 : dm->package_type; in check_positive()
45 (dm->support_interface & 0xF0) << 16 | in check_positive()
48 (dm->support_interface & 0x0F) << 8 | in check_positive()
51 u32 driver2 = (dm->type_glna & 0xFF) << 0 | in check_positive()
52 (dm->type_gpa & 0xFF) << 8 | in check_positive()
53 (dm->type_alna & 0xFF) << 16 | in check_positive()
54 (dm->type_apa & 0xFF) << 24; in check_positive()
56 u32 driver3 = 0; in check_positive()
58 u32 driver4 = (dm->type_glna & 0xFF00) >> 8 | in check_positive()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189es/hal/phydm/rtl8188e/
H A Dhalhwimg8188e_mac.c35 u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ in CheckPositive()
43 (pDM_Odm->SupportInterface & 0xF0) << 16 | in CheckPositive()
46 (pDM_Odm->SupportInterface & 0x0F) << 8 | in CheckPositive()
49 u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | in CheckPositive()
50 (pDM_Odm->TypeGPA & 0xFF) << 8 | in CheckPositive()
51 (pDM_Odm->TypeALNA & 0xFF) << 16 | in CheckPositive()
52 (pDM_Odm->TypeAPA & 0xFF) << 24; in CheckPositive()
54 u4Byte driver3 = 0; in CheckPositive()
56 u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | in CheckPositive()
57 (pDM_Odm->TypeGPA & 0xFF00) | in CheckPositive()
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/dts/
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
H A Dglacier.dts18 dcr-parent = <&{/cpus/cpu@0}>;
31 #size-cells = <0>;
33 cpu@0 {
36 reg = <0x00000000>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
51 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
57 cell-index = <0>;
58 dcr-reg = <0x0c0 0x009>;
59 #address-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp1/
H A Dregs.h40 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
41 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
44 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
47 #define GRF_VI_CON0 0x430
48 #define ISP_CIF_DATA_WIDTH_MASK 0x60006000
49 #define ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
54 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
55 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
74 #define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
77 #define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/isp/
H A Dregs.h42 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
43 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
46 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
49 #define GRF_VI_CON0 0x430
50 #define ISP_CIF_DATA_WIDTH_MASK 0x60006000
51 #define ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
56 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
57 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
76 #define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
79 #define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
[all …]

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