1 /*
2 * Rockchip isp1 driver
3 *
4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef _RKISP1_REGS_H
36 #define _RKISP1_REGS_H
37 #include "dev.h"
38
39 #define CIF_ISP_PACK_4BYTE(a, b, c, d) \
40 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
41 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
42
43 #define CIF_ISP_PACK_2SHORT(a, b) \
44 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
45
46 /* GRF */
47 #define GRF_VI_CON0 0x430
48 #define ISP_CIF_DATA_WIDTH_MASK 0x60006000
49 #define ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
50 #define ISP_CIF_DATA_WIDTH_10B (BIT(13) | 3 << 29)
51 #define ISP_CIF_DATA_WIDTH_12B (2 << 13 | 3 << 29)
52
53 /* ISP_CTRL */
54 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
55 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
56 #define CIF_ISP_CTRL_ISP_MODE_ITU656 (1 << 1)
57 #define CIF_ISP_CTRL_ISP_MODE_ITU601 (2 << 1)
58 #define CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601 (3 << 1)
59 #define CIF_ISP_CTRL_ISP_MODE_DATA_MODE (4 << 1)
60 #define CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656 (5 << 1)
61 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656 (6 << 1)
62 #define CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
63 #define CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
64 #define CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
65 #define CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
66 #define CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
67 #define CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
68 #define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
69 #define CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(12)
70 #define CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA BIT(13)
71 #define CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA BIT(14)
72
73 /* ISP_ACQ_PROP */
74 #define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
75 #define CIF_ISP_ACQ_PROP_HSYNC_LOW BIT(1)
76 #define CIF_ISP_ACQ_PROP_VSYNC_LOW BIT(2)
77 #define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
78 #define CIF_ISP_ACQ_PROP_BAYER_PAT_GRBG (1 << 3)
79 #define CIF_ISP_ACQ_PROP_BAYER_PAT_GBRG (2 << 3)
80 #define CIF_ISP_ACQ_PROP_BAYER_PAT_BGGR (3 << 3)
81 #define CIF_ISP_ACQ_PROP_BAYER_PAT(pat) ((pat) << 3)
82 #define CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
83 #define CIF_ISP_ACQ_PROP_YCRYCB (1 << 7)
84 #define CIF_ISP_ACQ_PROP_CBYCRY (2 << 7)
85 #define CIF_ISP_ACQ_PROP_CRYCBY (3 << 7)
86 #define CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
87 #define CIF_ISP_ACQ_PROP_FIELD_SEL_EVEN (1 << 9)
88 #define CIF_ISP_ACQ_PROP_FIELD_SEL_ODD (2 << 9)
89 #define CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
90 #define CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO (1 << 12)
91 #define CIF_ISP_ACQ_PROP_IN_SEL_10B_MSB (2 << 12)
92 #define CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO (3 << 12)
93 #define CIF_ISP_ACQ_PROP_IN_SEL_8B_MSB (4 << 12)
94 #define CIF_ISP_ACQ_PROP_DMA_RGB BIT(15)
95 #define CIF_ISP_ACQ_PROP_DMA_YUV BIT(16)
96
97 /* VI_DPCL */
98 #define CIF_VI_DPCL_DMA_JPEG (0 << 0)
99 #define CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
100 #define CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
101 #define CIF_VI_DPCL_CHAN_MODE_MP (1 << 2)
102 #define CIF_VI_DPCL_CHAN_MODE_SP (2 << 2)
103 #define CIF_VI_DPCL_CHAN_MODE_MPSP (3 << 2)
104 #define CIF_VI_DPCL_DMA_SW_SPMUX (0 << 4)
105 #define CIF_VI_DPCL_DMA_SW_SI (1 << 4)
106 #define CIF_VI_DPCL_DMA_SW_IE (2 << 4)
107 #define CIF_VI_DPCL_DMA_SW_JPEG (3 << 4)
108 #define CIF_VI_DPCL_DMA_SW_ISP (4 << 4)
109 #define CIF_VI_DPCL_IF_SEL_PARALLEL (0 << 8)
110 #define CIF_VI_DPCL_IF_SEL_SMIA (1 << 8)
111 #define CIF_VI_DPCL_IF_SEL_MIPI (2 << 8)
112 #define CIF_VI_DPCL_DMA_IE_MUX_DMA BIT(10)
113 #define CIF_VI_DPCL_DMA_SP_MUX_DMA BIT(11)
114
115 /* ISP_IMSC - ISP_MIS - ISP_RIS - ISP_ICR - ISP_ISR */
116 #define CIF_ISP_OFF BIT(0)
117 #define CIF_ISP_FRAME BIT(1)
118 #define CIF_ISP_DATA_LOSS BIT(2)
119 #define CIF_ISP_PIC_SIZE_ERROR BIT(3)
120 #define CIF_ISP_AWB_DONE BIT(4)
121 #define CIF_ISP_FRAME_IN BIT(5)
122 #define CIF_ISP_V_START BIT(6)
123 #define CIF_ISP_H_START BIT(7)
124 #define CIF_ISP_FLASH_ON BIT(8)
125 #define CIF_ISP_FLASH_OFF BIT(9)
126 #define CIF_ISP_SHUTTER_ON BIT(10)
127 #define CIF_ISP_SHUTTER_OFF BIT(11)
128 #define CIF_ISP_AFM_SUM_OF BIT(12)
129 #define CIF_ISP_AFM_LUM_OF BIT(13)
130 #define CIF_ISP_AFM_FIN BIT(14)
131 #define CIF_ISP_HIST_MEASURE_RDY BIT(15)
132 #define CIF_ISP_FLASH_CAP BIT(17)
133 #define CIF_ISP_EXP_END BIT(18)
134 #define CIF_ISP_VSM_END BIT(19)
135
136 /* ISP_ERR */
137 #define CIF_ISP_ERR_INFORM_SIZE BIT(0)
138 #define CIF_ISP_ERR_IS_SIZE BIT(1)
139 #define CIF_ISP_ERR_OUTFORM_SIZE BIT(2)
140
141 /* MI_CTRL */
142 #define CIF_MI_CTRL_MP_ENABLE (1 << 0)
143 #define CIF_MI_CTRL_SP_ENABLE (2 << 0)
144 #define CIF_MI_CTRL_JPEG_ENABLE (4 << 0)
145 #define CIF_MI_CTRL_RAW_ENABLE (8 << 0)
146 #define CIF_MI_CTRL_HFLIP BIT(4)
147 #define CIF_MI_CTRL_VFLIP BIT(5)
148 #define CIF_MI_CTRL_ROT BIT(6)
149 #define CIF_MI_BYTE_SWAP BIT(7)
150 #define CIF_MI_SP_Y_FULL_YUV2RGB BIT(8)
151 #define CIF_MI_SP_CBCR_FULL_YUV2RGB BIT(9)
152 #define CIF_MI_SP_422NONCOSITEED BIT(10)
153 #define CIF_MI_MP_PINGPONG_ENABEL BIT(11)
154 #define CIF_MI_SP_PINGPONG_ENABEL BIT(12)
155 #define CIF_MI_MP_AUTOUPDATE_ENABLE BIT(13)
156 #define CIF_MI_SP_AUTOUPDATE_ENABLE BIT(14)
157 #define CIF_MI_LAST_PIXEL_SIG_ENABLE BIT(15)
158 #define CIF_MI_CTRL_BURST_LEN_LUM_4 (0 << 16)
159 #define CIF_MI_CTRL_BURST_LEN_LUM_8 (1 << 16)
160 #define CIF_MI_CTRL_BURST_LEN_LUM_16 (2 << 16)
161 #define CIF_MI_CTRL_BURST_LEN_CHROM_4 (0 << 18)
162 #define CIF_MI_CTRL_BURST_LEN_CHROM_8 (1 << 18)
163 #define CIF_MI_CTRL_BURST_LEN_CHROM_16 (2 << 18)
164 #define CIF_MI_CTRL_INIT_BASE_EN BIT(20)
165 #define CIF_MI_CTRL_INIT_OFFSET_EN BIT(21)
166 #define MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8 (0 << 22)
167 #define MI_CTRL_MP_WRITE_YUV_SPLA (1 << 22)
168 #define MI_CTRL_MP_WRITE_YUVINT (2 << 22)
169 #define MI_CTRL_MP_WRITE_RAW12 (2 << 22)
170 #define MI_CTRL_SP_WRITE_PLA (0 << 24)
171 #define MI_CTRL_SP_WRITE_SPLA (1 << 24)
172 #define MI_CTRL_SP_WRITE_INT (2 << 24)
173 #define MI_CTRL_SP_INPUT_YUV400 (0 << 26)
174 #define MI_CTRL_SP_INPUT_YUV420 (1 << 26)
175 #define MI_CTRL_SP_INPUT_YUV422 (2 << 26)
176 #define MI_CTRL_SP_INPUT_YUV444 (3 << 26)
177 #define MI_CTRL_SP_OUTPUT_YUV400 (0 << 28)
178 #define MI_CTRL_SP_OUTPUT_YUV420 (1 << 28)
179 #define MI_CTRL_SP_OUTPUT_YUV422 (2 << 28)
180 #define MI_CTRL_SP_OUTPUT_YUV444 (3 << 28)
181 #define MI_CTRL_SP_OUTPUT_RGB565 (4 << 28)
182 #define MI_CTRL_SP_OUTPUT_RGB666 (5 << 28)
183 #define MI_CTRL_SP_OUTPUT_RGB888 (6 << 28)
184
185 #define MI_CTRL_MP_FMT_MASK GENMASK(23, 22)
186 #define MI_CTRL_SP_FMT_MASK GENMASK(30, 24)
187
188 /* MI_INIT */
189 #define CIF_MI_INIT_SKIP BIT(2)
190 #define CIF_MI_INIT_SOFT_UPD BIT(4)
191
192 /* MI_CTRL_SHD */
193 #define CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
194 #define CIF_MI_CTRL_SHD_SP_IN_ENABLED BIT(1)
195 #define CIF_MI_CTRL_SHD_JPEG_IN_ENABLED BIT(2)
196 #define CIF_MI_CTRL_SHD_RAW_IN_ENABLED BIT(3)
197 #define CIF_MI_CTRL_SHD_MP_OUT_ENABLED BIT(16)
198 #define CIF_MI_CTRL_SHD_SP_OUT_ENABLED BIT(17)
199 #define CIF_MI_CTRL_SHD_JPEG_OUT_ENABLED BIT(18)
200 #define CIF_MI_CTRL_SHD_RAW_OUT_ENABLED BIT(19)
201
202 /* MI_CTRL2 */
203 #define CIF_MI_CTRL2_MIPI_RAW0_PINGPONG_EN BIT(2)
204 #define CIF_MI_CTRL2_MIPI_RAW0_AUTO_UPDATE BIT(1)
205 #define CIF_MI_CTRL2_MIPI_RAW0_ENABLE BIT(0)
206
207 /* RSZ_CTRL */
208 #define CIF_RSZ_CTRL_SCALE_HY_ENABLE BIT(0)
209 #define CIF_RSZ_CTRL_SCALE_HC_ENABLE BIT(1)
210 #define CIF_RSZ_CTRL_SCALE_VY_ENABLE BIT(2)
211 #define CIF_RSZ_CTRL_SCALE_VC_ENABLE BIT(3)
212 #define CIF_RSZ_CTRL_SCALE_HY_UP BIT(4)
213 #define CIF_RSZ_CTRL_SCALE_HC_UP BIT(5)
214 #define CIF_RSZ_CTRL_SCALE_VY_UP BIT(6)
215 #define CIF_RSZ_CTRL_SCALE_VC_UP BIT(7)
216 #define CIF_RSZ_CTRL_CFG_UPD BIT(8)
217 #define CIF_RSZ_CTRL_CFG_UPD_AUTO BIT(9)
218 #define CIF_RSZ_SCALER_FACTOR BIT(16)
219
220 /* MI_IMSC - MI_MIS - MI_RIS - MI_ICR - MI_ISR */
221 #define CIF_MI_FRAME(stream) BIT((stream)->id)
222 #define CIF_MI_MBLK_LINE BIT(2)
223 #define CIF_MI_FILL_MP_Y BIT(3)
224 #define CIF_MI_WRAP_MP_Y BIT(4)
225 #define CIF_MI_WRAP_MP_CB BIT(5)
226 #define CIF_MI_WRAP_MP_CR BIT(6)
227 #define CIF_MI_WRAP_SP_Y BIT(7)
228 #define CIF_MI_WRAP_SP_CB BIT(8)
229 #define CIF_MI_WRAP_SP_CR BIT(9)
230 #define CIF_MI_DMA_READY BIT(11)
231
232 /* MI_STATUS */
233 #define CIF_MI_STATUS_MP_Y_FIFO_FULL BIT(0)
234 #define CIF_MI_STATUS_SP_Y_FIFO_FULL BIT(4)
235
236 /* MI_DMA_CTRL */
237 #define CIF_MI_DMA_CTRL_BURST_LEN_LUM_4 (0 << 0)
238 #define CIF_MI_DMA_CTRL_BURST_LEN_LUM_8 BIT(0)
239 #define CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 BIT(1)
240 #define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_4 (0 << 2)
241 #define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_8 BIT(2)
242 #define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16 BIT(3)
243 #define CIF_MI_DMA_CTRL_READ_FMT_PLANAR (0 << 4)
244 #define CIF_MI_DMA_CTRL_READ_FMT_SPLANAR (1 << 4)
245 #define CIF_MI_DMA_CTRL_READ_FMT_PACKED (2 << 4)
246 #define CIF_MI_DMA_CTRL_FMT_YUV400 (0 << 6)
247 #define CIF_MI_DMA_CTRL_FMT_YUV420 (1 << 6)
248 #define CIF_MI_DMA_CTRL_FMT_YUV422 (2 << 6)
249 #define CIF_MI_DMA_CTRL_FMT_YUV444 (3 << 6)
250 #define CIF_MI_DMA_CTRL_BYTE_SWAP BIT(8)
251 #define CIF_MI_DMA_CTRL_CONTINUOUS_ENA BIT(9)
252 #define CIF_MI_DMA_CTRL_RGB_BAYER_NO (0 << 12)
253 #define CIF_MI_DMA_CTRL_RGB_BAYER_8BIT (1 << 12)
254 #define CIF_MI_DMA_CTRL_RGB_BAYER_16BIT (2 << 12)
255 /* MI_DMA_START */
256 #define CIF_MI_DMA_START_ENABLE BIT(0)
257 /* MI_XTD_FORMAT_CTRL */
258 #define CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP BIT(0)
259 #define CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
260 #define CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
261
262 /* CCL */
263 #define CIF_CCL_CIF_CLK_DIS BIT(2)
264 /* VI_ISP_CLK_CTRL */
265 #define CIF_CLK_CTRL_ISP_RAW BIT(0)
266 #define CIF_CLK_CTRL_ISP_RGB BIT(1)
267 #define CIF_CLK_CTRL_ISP_YUV BIT(2)
268 #define CIF_CLK_CTRL_ISP_3A BIT(3)
269 #define CIF_CLK_CTRL_MIPI_RAW BIT(4)
270 #define CIF_CLK_CTRL_ISP_IE BIT(5)
271 #define CIF_CLK_CTRL_RSZ_RAM BIT(6)
272 #define CIF_CLK_CTRL_JPEG_RAM BIT(7)
273 #define CIF_CLK_CTRL_ACLK_ISP BIT(8)
274 #define CIF_CLK_CTRL_MI_IDC BIT(9)
275 #define CIF_CLK_CTRL_MI_MP BIT(10)
276 #define CIF_CLK_CTRL_MI_JPEG BIT(11)
277 #define CIF_CLK_CTRL_MI_DP BIT(12)
278 #define CIF_CLK_CTRL_MI_Y12 BIT(13)
279 #define CIF_CLK_CTRL_MI_SP BIT(14)
280 #define CIF_CLK_CTRL_MI_RAW0 BIT(15)
281 #define CIF_CLK_CTRL_MI_RAW1 BIT(16)
282 #define CIF_CLK_CTRL_MI_READ BIT(17)
283 #define CIF_CLK_CTRL_MI_RAWRD BIT(18)
284 #define CIF_CLK_CTRL_CP BIT(19)
285 #define CIF_CLK_CTRL_IE BIT(20)
286 #define CIF_CLK_CTRL_SI BIT(21)
287 #define CIF_CLK_CTRL_RSZM BIT(22)
288 #define CIF_CLK_CTRL_DPMUX BIT(23)
289 #define CIF_CLK_CTRL_JPEG BIT(24)
290 #define CIF_CLK_CTRL_RSZS BIT(25)
291 #define CIF_CLK_CTRL_MIPI BIT(26)
292 #define CIF_CLK_CTRL_MARVINMI BIT(27)
293 /* ICCL */
294 #define CIF_ICCL_ISP_CLK BIT(0)
295 #define CIF_ICCL_CP_CLK BIT(1)
296 #define CIF_ICCL_RES_2 BIT(2)
297 #define CIF_ICCL_MRSZ_CLK BIT(3)
298 #define CIF_ICCL_SRSZ_CLK BIT(4)
299 #define CIF_ICCL_JPEG_CLK BIT(5)
300 #define CIF_ICCL_MI_CLK BIT(6)
301 #define CIF_ICCL_RES_7 BIT(7)
302 #define CIF_ICCL_IE_CLK BIT(8)
303 #define CIF_ICCL_SIMP_CLK BIT(9)
304 #define CIF_ICCL_SMIA_CLK BIT(10)
305 #define CIF_ICCL_MIPI_CLK BIT(11)
306 #define CIF_ICCL_DCROP_CLK BIT(12)
307 /* IRCL */
308 #define CIF_IRCL_ISP_SW_RST BIT(0)
309 #define CIF_IRCL_CP_SW_RST BIT(1)
310 #define CIF_IRCL_YCS_SW_RST BIT(2)
311 #define CIF_IRCL_MRSZ_SW_RST BIT(3)
312 #define CIF_IRCL_SRSZ_SW_RST BIT(4)
313 #define CIF_IRCL_JPEG_SW_RST BIT(5)
314 #define CIF_IRCL_MI_SW_RST BIT(6)
315 #define CIF_IRCL_CIF_SW_RST BIT(7)
316 #define CIF_IRCL_IE_SW_RST BIT(8)
317 #define CIF_IRCL_SI_SW_RST BIT(9)
318 #define CIF_IRCL_MIPI_SW_RST BIT(11)
319
320 /* C_PROC_CTR */
321 #define CIF_C_PROC_CTR_ENABLE BIT(0)
322 #define CIF_C_PROC_YOUT_FULL BIT(1)
323 #define CIF_C_PROC_YIN_FULL BIT(2)
324 #define CIF_C_PROC_COUT_FULL BIT(3)
325 #define CIF_C_PROC_CTRL_RESERVED 0xFFFFFFFE
326 #define CIF_C_PROC_CONTRAST_RESERVED 0xFFFFFF00
327 #define CIF_C_PROC_BRIGHTNESS_RESERVED 0xFFFFFF00
328 #define CIF_C_PROC_HUE_RESERVED 0xFFFFFF00
329 #define CIF_C_PROC_SATURATION_RESERVED 0xFFFFFF00
330 #define CIF_C_PROC_MACC_RESERVED 0xE000E000
331 #define CIF_C_PROC_TONE_RESERVED 0xF000
332 /* DUAL_CROP_CTRL */
333 #define CIF_DUAL_CROP_MP_MODE_BYPASS (0 << 0)
334 #define CIF_DUAL_CROP_MP_MODE_YUV (1 << 0)
335 #define CIF_DUAL_CROP_MP_MODE_RAW (2 << 0)
336 #define CIF_DUAL_CROP_SP_MODE_BYPASS (0 << 2)
337 #define CIF_DUAL_CROP_SP_MODE_YUV (1 << 2)
338 #define CIF_DUAL_CROP_SP_MODE_RAW (2 << 2)
339 #define CIF_DUAL_CROP_CFG_UPD_PERMANENT BIT(4)
340 #define CIF_DUAL_CROP_CFG_UPD BIT(5)
341 #define CIF_DUAL_CROP_GEN_CFG_UPD BIT(6)
342
343 /* IMG_EFF_CTRL */
344 #define CIF_IMG_EFF_CTRL_ENABLE BIT(0)
345 #define CIF_IMG_EFF_CTRL_MODE_BLACKWHITE (0 << 1)
346 #define CIF_IMG_EFF_CTRL_MODE_NEGATIVE (1 << 1)
347 #define CIF_IMG_EFF_CTRL_MODE_SEPIA (2 << 1)
348 #define CIF_IMG_EFF_CTRL_MODE_COLOR_SEL (3 << 1)
349 #define CIF_IMG_EFF_CTRL_MODE_EMBOSS (4 << 1)
350 #define CIF_IMG_EFF_CTRL_MODE_SKETCH (5 << 1)
351 #define CIF_IMG_EFF_CTRL_MODE_SHARPEN (6 << 1)
352 #define CIF_IMG_EFF_CTRL_MODE_RKSHARPEN (7 << 1)
353 #define CIF_IMG_EFF_CTRL_CFG_UPD BIT(4)
354 #define CIF_IMG_EFF_CTRL_YCBCR_FULL BIT(5)
355
356 #define CIF_IMG_EFF_CTRL_MODE_BLACKWHITE_SHIFT 0
357 #define CIF_IMG_EFF_CTRL_MODE_NEGATIVE_SHIFT 1
358 #define CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT 2
359 #define CIF_IMG_EFF_CTRL_MODE_COLOR_SEL_SHIFT 3
360 #define CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT 4
361 #define CIF_IMG_EFF_CTRL_MODE_SKETCH_SHIFT 5
362 #define CIF_IMG_EFF_CTRL_MODE_SHARPEN_SHIFT 6
363 #define CIF_IMG_EFF_CTRL_MODE_MASK 0xE
364
365 /* IMG_EFF_COLOR_SEL */
366 #define CIF_IMG_EFF_COLOR_RGB 0
367 #define CIF_IMG_EFF_COLOR_B (1 << 0)
368 #define CIF_IMG_EFF_COLOR_G (2 << 0)
369 #define CIF_IMG_EFF_COLOR_GB (3 << 0)
370 #define CIF_IMG_EFF_COLOR_R (4 << 0)
371 #define CIF_IMG_EFF_COLOR_RB (5 << 0)
372 #define CIF_IMG_EFF_COLOR_RG (6 << 0)
373 #define CIF_IMG_EFF_COLOR_RGB2 (7 << 0)
374
375 /* MIPI_CTRL */
376 #define CIF_MIPI_CTRL_OUTPUT_ENA BIT(0)
377 #define CIF_MIPI_CTRL_FLUSH_FIFO BIT(1)
378 #define CIF_MIPI_CTRL_SHUTDOWNLANES(a) (((a) & 0xF) << 8)
379 #define CIF_MIPI_CTRL_NUM_LANES(a) (((a) & 0x3) << 12)
380 #define CIF_MIPI_CTRL_ERR_SOT_HS_SKIP BIT(16)
381 #define CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP BIT(17)
382 #define CIF_MIPI_CTRL_CLOCKLANE_ENA BIT(18)
383
384 /* MIPI_DATA_SEL */
385 #define CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6)
386 #define CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0)
387 /* MIPI DATA_TYPE */
388 #define CIF_CSI2_DT_YUV420_8b 0x18
389 #define CIF_CSI2_DT_YUV420_10b 0x19
390 #define CIF_CSI2_DT_YUV422_8b 0x1E
391 #define CIF_CSI2_DT_YUV422_10b 0x1F
392 #define CIF_CSI2_DT_RGB565 0x22
393 #define CIF_CSI2_DT_RGB666 0x23
394 #define CIF_CSI2_DT_RGB888 0x24
395 #define CIF_CSI2_DT_RAW8 0x2A
396 #define CIF_CSI2_DT_RAW10 0x2B
397 #define CIF_CSI2_DT_RAW12 0x2C
398
399 /* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */
400 #define CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)
401 #define CIF_MIPI_ERR_SOT(a) (((a) & 0xF) << 4)
402 #define CIF_MIPI_ERR_SOT_SYNC(a) (((a) & 0xF) << 8)
403 #define CIF_MIPI_ERR_EOT_SYNC(a) (((a) & 0xF) << 12)
404 #define CIF_MIPI_ERR_CTRL(a) (((a) & 0xF) << 16)
405 #define CIF_MIPI_ERR_PROTOCOL BIT(20)
406 #define CIF_MIPI_ERR_ECC1 BIT(21)
407 #define CIF_MIPI_ERR_ECC2 BIT(22)
408 #define CIF_MIPI_ERR_CS BIT(23)
409 #define CIF_MIPI_FRAME_END BIT(24)
410 #define CIF_MIPI_ADD_DATA_OVFLW BIT(25)
411 #define CIF_MIPI_ADD_DATA_WATER_MARK BIT(26)
412
413 #define CIF_MIPI_ERR_CSI (CIF_MIPI_ERR_PROTOCOL | \
414 CIF_MIPI_ERR_ECC1 | \
415 CIF_MIPI_ERR_ECC2 | \
416 CIF_MIPI_ERR_CS)
417
418 #define CIF_MIPI_ERR_DPHY (CIF_MIPI_ERR_SOT(0xF) | \
419 CIF_MIPI_ERR_SOT_SYNC(0xF) | \
420 CIF_MIPI_ERR_EOT_SYNC(0xF) | \
421 CIF_MIPI_ERR_CTRL(0xF))
422
423 /* SUPER_IMPOSE */
424 #define CIF_SUPER_IMP_CTRL_NORMAL_MODE BIT(0)
425 #define CIF_SUPER_IMP_CTRL_REF_IMG_MEM BIT(1)
426 #define CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2)
427
428 /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
429 #define CIF_ISP_HIST_PROP_MODE_DIS_V10 (0 << 0)
430 #define CIF_ISP_HIST_PROP_MODE_RGB_V10 (1 << 0)
431 #define CIF_ISP_HIST_PROP_MODE_RED_V10 (2 << 0)
432 #define CIF_ISP_HIST_PROP_MODE_GREEN_V10 (3 << 0)
433 #define CIF_ISP_HIST_PROP_MODE_BLUE_V10 (4 << 0)
434 #define CIF_ISP_HIST_PROP_MODE_LUM_V10 (5 << 0)
435 #define CIF_ISP_HIST_PROP_MODE_MASK_V10 0x7
436 #define CIF_ISP_HIST_PREDIV_SET_V10(x) (((x) & 0x7F) << 3)
437 #define CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3) \
438 (((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\
439 (((v2) & 0x1F) << 16) | \
440 (((v3) & 0x1F) << 24))
441
442 #define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10 0xFFFFF000
443 #define CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10 0xFFFFF800
444 #define CIF_ISP_HIST_WEIGHT_RESERVED_V10 0xE0E0E0E0
445 #define CIF_ISP_MAX_HIST_PREDIVIDER_V10 0x0000007F
446 #define CIF_ISP_HIST_ROW_NUM_V10 5
447 #define CIF_ISP_HIST_COLUMN_NUM_V10 5
448
449 /* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
450 #define CIF_ISP_HIST_CTRL_EN_SET_V12(x) (((x) & 0x01) << 0)
451 #define CIF_ISP_HIST_CTRL_EN_MASK_V12 CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
452 #define CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x) (((x) & 0x7F) << 1)
453 #define CIF_ISP_HIST_CTRL_MODE_SET_V12(x) (((x) & 0x07) << 8)
454 #define CIF_ISP_HIST_CTRL_MODE_MASK_V12 CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
455 #define CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x) (((x) & 0x01) << 11)
456 #define CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x) (((x) & 0xFFF) << 12)
457 #define CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x) (((x) & 0x07) << 24)
458 #define CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x) (((x) & 0x01) << 27)
459 #define CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 28)
460 #define CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x) (((x) & 0x01) << 30)
461 #define CIF_ISP_HIST_ROW_NUM_V12 15
462 #define CIF_ISP_HIST_COLUMN_NUM_V12 15
463 #define CIF_ISP_HIST_WEIGHT_REG_SIZE_V12 \
464 (CIF_ISP_HIST_ROW_NUM_V12 * CIF_ISP_HIST_COLUMN_NUM_V12)
465
466 #define CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3) \
467 (((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
468 (((v2) & 0x3F) << 16) |\
469 (((v3) & 0x3F) << 24))
470
471 #define CIF_ISP_HIST_OFFS_SET_V12(v0, v1) \
472 (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
473 #define CIF_ISP_HIST_SIZE_SET_V12(v0, v1) \
474 (((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
475
476 #define CIF_ISP_HIST_GET_BIN0_V12(x) \
477 ((x) & 0xFFFF)
478 #define CIF_ISP_HIST_GET_BIN1_V12(x) \
479 (((x) >> 16) & 0xFFFF)
480
481 /* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
482 #define ISP_AFM_CTRL_ENABLE BIT(0)
483
484 /* SHUTTER CONTROL */
485 #define CIF_ISP_SH_CTRL_SH_ENA BIT(0)
486 #define CIF_ISP_SH_CTRL_REP_EN BIT(1)
487 #define CIF_ISP_SH_CTRL_SRC_SH_TRIG BIT(2)
488 #define CIF_ISP_SH_CTRL_EDGE_POS BIT(3)
489 #define CIF_ISP_SH_CTRL_POL_LOW BIT(4)
490
491 /* FLASH MODULE */
492 /* ISP_FLASH_CMD */
493 #define CIF_FLASH_CMD_PRELIGHT_ON BIT(0)
494 #define CIF_FLASH_CMD_FLASH_ON BIT(1)
495 #define CIF_FLASH_CMD_PRE_FLASH_ON BIT(2)
496 /* ISP_FLASH_CONFIG */
497 #define CIF_FLASH_CONFIG_PRELIGHT_END BIT(0)
498 #define CIF_FLASH_CONFIG_VSYNC_POS BIT(1)
499 #define CIF_FLASH_CONFIG_PRELIGHT_LOW BIT(2)
500 #define CIF_FLASH_CONFIG_SRC_FL_TRIG BIT(3)
501 #define CIF_FLASH_CONFIG_DELAY(a) (((a) & 0xF) << 4)
502
503 /* Demosaic: ISP_DEMOSAIC */
504 #define CIF_ISP_DEMOSAIC_BYPASS BIT(10)
505 #define CIF_ISP_DEMOSAIC_TH(x) ((x) & 0xFF)
506
507 /* AWB */
508 /* ISP_AWB_PROP */
509 #define CIF_ISP_AWB_YMAX_CMP_EN BIT(2)
510 #define CIF_ISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
511 #define CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0))
512 #define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
513 #define CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC
514 #define CIF_ISP_AWB_MODE_READ(x) ((x) & 3)
515 #define CIF_ISP_AWB_SET_FRAMES_V12(x) (((x) & 0x07) << 28)
516 #define CIF_ISP_AWB_SET_FRAMES_MASK_V12 CIF_ISP_AWB_SET_FRAMES_V12(0x07)
517 /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */
518 #define CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16)
519 #define CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF)
520 #define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FF)
521 #define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FF)
522 /* ISP_AWB_REF */
523 #define CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8)
524 #define CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF)
525 #define CIF_ISP_AWB_REF_CB_READ(x) ((x) & 0xFF)
526 /* ISP_AWB_THRESH */
527 #define CIF_ISP_AWB_MAX_CS_SET(x) (((x) & 0xFF) << 8)
528 #define CIF_ISP_AWB_MAX_CS_READ(x) (((x) >> 8) & 0xFF)
529 #define CIF_ISP_AWB_MIN_C_READ(x) ((x) & 0xFF)
530 #define CIF_ISP_AWB_MIN_Y_SET(x) (((x) & 0xFF) << 16)
531 #define CIF_ISP_AWB_MIN_Y_READ(x) (((x) >> 16) & 0xFF)
532 #define CIF_ISP_AWB_MAX_Y_SET(x) (((x) & 0xFF) << 24)
533 #define CIF_ISP_AWB_MAX_Y_READ(x) (((x) >> 24) & 0xFF)
534 /* ISP_AWB_MEAN */
535 #define CIF_ISP_AWB_GET_MEAN_CR_R(x) ((x) & 0xFF)
536 #define CIF_ISP_AWB_GET_MEAN_CB_B(x) (((x) >> 8) & 0xFF)
537 #define CIF_ISP_AWB_GET_MEAN_Y_G(x) (((x) >> 16) & 0xFF)
538 /* ISP_AWB_WHITE_CNT */
539 #define CIF_ISP_AWB_GET_PIXEL_CNT(x) ((x) & 0x3FFFFFF)
540
541 #define CIF_ISP_AWB_GAINS_MAX_VAL 0x000003FF
542 #define CIF_ISP_AWB_WINDOW_OFFSET_MAX 0x00000FFF
543 #define CIF_ISP_AWB_WINDOW_MAX_SIZE 0x00001FFF
544 #define CIF_ISP_AWB_CBCR_MAX_REF 0x000000FF
545 #define CIF_ISP_AWB_THRES_MAX_YC 0x000000FF
546
547 /* AE */
548 /* ISP_EXP_CTRL */
549 #define CIF_ISP_EXP_ENA BIT(0)
550 #define CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1)
551 #define CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 2)
552 /*
553 *'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)
554 *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
555 */
556 #define CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31)
557
558 /* ISP_EXP_H_SIZE */
559 #define CIF_ISP_EXP_H_SIZE_SET_V10(x) ((x) & 0x7FF)
560 #define CIF_ISP_EXP_HEIGHT_MASK_V10 0x000007FF
561 /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
562 #define CIF_ISP_EXP_V_SIZE_SET_V10(x) ((x) & 0x7FE)
563
564 /* ISP_EXP_H_OFFSET */
565 #define CIF_ISP_EXP_H_OFFSET_SET_V10(x) ((x) & 0x1FFF)
566 #define CIF_ISP_EXP_MAX_HOFFS_V10 2424
567 /* ISP_EXP_V_OFFSET */
568 #define CIF_ISP_EXP_V_OFFSET_SET_V10(x) ((x) & 0x1FFF)
569 #define CIF_ISP_EXP_MAX_VOFFS_V10 1806
570
571 #define CIF_ISP_EXP_ROW_NUM_V10 5
572 #define CIF_ISP_EXP_COLUMN_NUM_V10 5
573 #define CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
574 (CIF_ISP_EXP_ROW_NUM_V10 * CIF_ISP_EXP_COLUMN_NUM_V10)
575 #define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 516
576 #define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 35
577 #define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 390
578 #define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 28
579 #define CIF_ISP_EXP_MAX_HSIZE_V10 \
580 (CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
581 #define CIF_ISP_EXP_MIN_HSIZE_V10 \
582 (CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
583 #define CIF_ISP_EXP_MAX_VSIZE_V10 \
584 (CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1)
585 #define CIF_ISP_EXP_MIN_VSIZE_V10 \
586 (CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1)
587
588 /* ISP_EXP_H_SIZE */
589 #define CIF_ISP_EXP_H_SIZE_SET_V12(x) ((x) & 0x7FF)
590 #define CIF_ISP_EXP_HEIGHT_MASK_V12 0x000007FF
591 /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
592 #define CIF_ISP_EXP_V_SIZE_SET_V12(x) (((x) & 0x7FE) << 16)
593
594 /* ISP_EXP_H_OFFSET */
595 #define CIF_ISP_EXP_H_OFFSET_SET_V12(x) ((x) & 0x1FFF)
596 #define CIF_ISP_EXP_MAX_HOFFS_V12 0x1FFF
597 /* ISP_EXP_V_OFFSET */
598 #define CIF_ISP_EXP_V_OFFSET_SET_V12(x) (((x) & 0x1FFF) << 16)
599 #define CIF_ISP_EXP_MAX_VOFFS_V12 0x1FFF
600
601 #define CIF_ISP_EXP_ROW_NUM_V12 15
602 #define CIF_ISP_EXP_COLUMN_NUM_V12 15
603 #define CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
604 (CIF_ISP_EXP_ROW_NUM_V12 * CIF_ISP_EXP_COLUMN_NUM_V12)
605 #define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 0x7FF
606 #define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 0xE
607 #define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 0x7FE
608 #define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 0xE
609 #define CIF_ISP_EXP_MAX_HSIZE_V12 \
610 (CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
611 #define CIF_ISP_EXP_MIN_HSIZE_V12 \
612 (CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
613 #define CIF_ISP_EXP_MAX_VSIZE_V12 \
614 (CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1)
615 #define CIF_ISP_EXP_MIN_VSIZE_V12 \
616 (CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1)
617
618 #define CIF_ISP_EXP_GET_MEAN_xy0_V12(x) ((x) & 0xFF)
619 #define CIF_ISP_EXP_GET_MEAN_xy1_V12(x) (((x) >> 8) & 0xFF)
620 #define CIF_ISP_EXP_GET_MEAN_xy2_V12(x) (((x) >> 16) & 0xFF)
621 #define CIF_ISP_EXP_GET_MEAN_xy3_V12(x) (((x) >> 24) & 0xFF)
622
623 /* LSC: ISP_LSC_CTRL */
624 #define CIF_ISP_LSC_CTRL_ENA BIT(0)
625 #define CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00
626 #define CIF_ISP_LSC_GRAD_RESERVED_V10 0xF000F000
627 #define CIF_ISP_LSC_SAMPLE_RESERVED_V10 0xF000F000
628 #define CIF_ISP_LSC_GRAD_RESERVED_V12 0xE000E000
629 #define CIF_ISP_LSC_SAMPLE_RESERVED_V12 0xE000E000
630 #define CIF_ISP_LSC_SECTORS_MAX 17
631 #define CIF_ISP_LSC_TABLE_DATA_V10(v0, v1) \
632 (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
633 #define CIF_ISP_LSC_TABLE_DATA_V12(v0, v1) \
634 (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
635 #define CIF_ISP_LSC_SECT_SIZE(v0, v1) \
636 (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
637 #define CIF_ISP_LSC_GRAD_SIZE(v0, v1) \
638 (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
639
640 /* LSC: ISP_LSC_TABLE_SEL */
641 #define CIF_ISP_LSC_TABLE_0 0
642 #define CIF_ISP_LSC_TABLE_1 1
643
644 /* LSC: ISP_LSC_STATUS */
645 #define CIF_ISP_LSC_ACTIVE_TABLE BIT(1)
646 #define CIF_ISP_LSC_TABLE_ADDRESS_0 0
647 #define CIF_ISP_LSC_TABLE_ADDRESS_153 153
648
649 /* FLT */
650 /* ISP_FILT_MODE */
651 #define CIF_ISP_FLT_ENA BIT(0)
652
653 /*
654 * 0: green filter static mode (active filter factor = FILT_FAC_MID)
655 * 1: dynamic noise reduction/sharpen Default
656 */
657 #define CIF_ISP_FLT_MODE_DNR BIT(1)
658 #define CIF_ISP_FLT_MODE_MAX 1
659 #define CIF_ISP_FLT_CHROMA_V_MODE(x) (((x) & 0x3) << 4)
660 #define CIF_ISP_FLT_CHROMA_H_MODE(x) (((x) & 0x3) << 6)
661 #define CIF_ISP_FLT_CHROMA_MODE_MAX 3
662 #define CIF_ISP_FLT_GREEN_STAGE1(x) (((x) & 0xF) << 8)
663 #define CIF_ISP_FLT_GREEN_STAGE1_MAX 8
664 #define CIF_ISP_FLT_THREAD_RESERVED 0xFFFFFC00
665 #define CIF_ISP_FLT_FAC_RESERVED 0xFFFFFFC0
666 #define CIF_ISP_FLT_LUM_WEIGHT_RESERVED 0xFFF80000
667
668 #define CIF_ISP_CTK_COEFF_RESERVED 0xFFFFF800
669 #define CIF_ISP_XTALK_OFFSET_RESERVED 0xFFFFF000
670
671 #define CIF_ISP_FLT_LEVEL_OLD_LP BIT(16)
672
673 /* GOC */
674 #define CIF_ISP_GAMMA_OUT_MODE_EQU BIT(0)
675 #define CIF_ISP_GOC_MODE_MAX 1
676 #define CIF_ISP_GOC_RESERVED 0xFFFFF800
677 /* ISP_CTRL BIT 11*/
678 #define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA_READ(x) (((x) >> 11) & 1)
679
680 /* DPCC */
681 /* ISP_DPCC_MODE */
682 #define CIF_ISP_DPCC_ENA BIT(0)
683 #define CIF_ISP_DPCC_MODE_MAX 0x07
684 #define CIF_ISP_DPCC_OUTPUTMODE_MAX 0x0F
685 #define CIF_ISP_DPCC_SETUSE_MAX 0x0F
686 #define CIF_ISP_DPCC_METHODS_SET_RESERVED 0xFFFFE000
687 #define CIF_ISP_DPCC_LINE_THRESH_RESERVED 0xFFFF0000
688 #define CIF_ISP_DPCC_LINE_MAD_FAC_RESERVED 0xFFFFC0C0
689 #define CIF_ISP_DPCC_PG_FAC_RESERVED 0xFFFFC0C0
690 #define CIF_ISP_DPCC_RND_THRESH_RESERVED 0xFFFF0000
691 #define CIF_ISP_DPCC_RG_FAC_RESERVED 0xFFFFC0C0
692 #define CIF_ISP_DPCC_RO_LIMIT_RESERVED 0xFFFFF000
693 #define CIF_ISP_DPCC_RND_OFFS_RESERVED 0xFFFFF000
694
695 /* BLS */
696 /* ISP_BLS_CTRL */
697 #define CIF_ISP_BLS_ENA BIT(0)
698 #define CIF_ISP_BLS_MODE_MEASURED BIT(1)
699 #define CIF_ISP_BLS_MODE_FIXED 0
700 #define CIF_ISP_BLS_WINDOW_1 (1 << 2)
701 #define CIF_ISP_BLS_WINDOW_2 (2 << 2)
702
703 /* GAMMA-IN */
704 #define CIFISP_DEGAMMA_X_RESERVED \
705 ((1 << 31) | (1 << 27) | (1 << 23) | (1 << 19) |\
706 (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
707 #define CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000
708
709 /* GAMMA-OUT */
710 #define CIF_ISP_GAMMA_REG_VALUE_V12(x, y) \
711 (((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
712
713 /* AFM */
714 #define CIF_ISP_AFM_ENA BIT(0)
715 #define CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000
716 #define CIF_ISP_AFM_VAR_SHIFT_RESERVED 0xFFF8FFF8
717 #define CIF_ISP_AFM_WINDOW_X_RESERVED 0xE000
718 #define CIF_ISP_AFM_WINDOW_Y_RESERVED 0xF000
719 #define CIF_ISP_AFM_WINDOW_X_MIN 0x5
720 #define CIF_ISP_AFM_WINDOW_Y_MIN 0x2
721 #define CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16)
722 #define CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF)
723 #define CIF_ISP_AFM_SET_SHIFT_a_V12(x, y) (((x) & 0x7) << 16 | ((y) & 0x7) << 0)
724 #define CIF_ISP_AFM_SET_SHIFT_b_V12(x, y) (((x) & 0x7) << 20 | ((y) & 0x7) << 4)
725 #define CIF_ISP_AFM_SET_SHIFT_c_V12(x, y) (((x) & 0x7) << 24 | ((y) & 0x7) << 8)
726 #define CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x) (((x) & 0x70000) >> 16)
727 #define CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x) ((x) & 0x7)
728
729 /* DPF */
730 #define CIF_ISP_DPF_MODE_EN BIT(0)
731 #define CIF_ISP_DPF_MODE_B_FLT_DIS BIT(1)
732 #define CIF_ISP_DPF_MODE_GB_FLT_DIS BIT(2)
733 #define CIF_ISP_DPF_MODE_GR_FLT_DIS BIT(3)
734 #define CIF_ISP_DPF_MODE_R_FLT_DIS BIT(4)
735 #define CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9 BIT(5)
736 #define CIF_ISP_DPF_MODE_NLL_SEGMENTATION BIT(6)
737 #define CIF_ISP_DPF_MODE_AWB_GAIN_COMP BIT(7)
738 #define CIF_ISP_DPF_MODE_LSC_GAIN_COMP BIT(8)
739 #define CIF_ISP_DPF_MODE_USE_NF_GAIN BIT(9)
740 #define CIF_ISP_DPF_NF_GAIN_RESERVED 0xFFFFF000
741 #define CIF_ISP_DPF_SPATIAL_COEFF_MAX 0x1F
742 #define CIF_ISP_DPF_NLL_COEFF_N_MAX 0x3FF
743
744 /* CSI0 */
745 #define CIF_ISP_CSI0_IMASK_LINECNT BIT(12)
746 #define CIF_ISP_CSI0_IMASK_RAW1_OUT_V_END BIT(11)
747 #define CIF_ISP_CSI0_IMASK_RAW0_OUT_V_END BIT(10)
748 #define CIF_ISP_CSI0_IMASK_FRAME_END(a) (((a) & 0x3F) << 0)
749
750 #define CIF_ISP_CSI0_IMASK2_PHY_ERRSOTHS(a) (((a) & 0x0F) << 4)
751 #define CIF_ISP_CSI0_IMASK2_PHY_ERRCONTROL(a) (((a) & 0x0F) << 16)
752 #define CIF_ISP_CSI0_IMASK1_PHY_ERRSOTSYNC(a) (((a) & 0x0F) << 8)
753 #define CIF_ISP_CSI0_IMASK1_PHY_ERREOTSYNC(a) (((a) & 0x0F) << 4)
754
755 #define CIF_ISP_CSI0_DMATX0_VC(a) (((a) & 0xFF) << 8)
756 #define CIF_ISP_CSI0_DMATX0_SIMG_SWP BIT(2)
757 #define CIF_ISP_CSI0_DMATX0_SIMG_MODE BIT(1)
758 #define CIF_ISP_CSI0_DMATX0_EN BIT(0)
759
760 /* =================================================================== */
761 /* CIF Registers */
762 /* =================================================================== */
763 #define CIF_CTRL_BASE 0x00000000
764 #define CIF_CCL (CIF_CTRL_BASE + 0x00000000)
765 #define CIF_VI_ID (CIF_CTRL_BASE + 0x00000008)
766 #define CIF_VI_ISP_CLK_CTRL_V12 (CIF_CTRL_BASE + 0x0000000C)
767 #define CIF_ICCL (CIF_CTRL_BASE + 0x00000010)
768 #define CIF_IRCL (CIF_CTRL_BASE + 0x00000014)
769 #define CIF_VI_DPCL (CIF_CTRL_BASE + 0x00000018)
770
771 #define CIF_IMG_EFF_BASE 0x00000200
772 #define CIF_IMG_EFF_CTRL (CIF_IMG_EFF_BASE + 0x00000000)
773 #define CIF_IMG_EFF_COLOR_SEL (CIF_IMG_EFF_BASE + 0x00000004)
774 #define CIF_IMG_EFF_MAT_1 (CIF_IMG_EFF_BASE + 0x00000008)
775 #define CIF_IMG_EFF_MAT_2 (CIF_IMG_EFF_BASE + 0x0000000C)
776 #define CIF_IMG_EFF_MAT_3 (CIF_IMG_EFF_BASE + 0x00000010)
777 #define CIF_IMG_EFF_MAT_4 (CIF_IMG_EFF_BASE + 0x00000014)
778 #define CIF_IMG_EFF_MAT_5 (CIF_IMG_EFF_BASE + 0x00000018)
779 #define CIF_IMG_EFF_TINT (CIF_IMG_EFF_BASE + 0x0000001C)
780 #define CIF_IMG_EFF_CTRL_SHD (CIF_IMG_EFF_BASE + 0x00000020)
781 #define CIF_IMG_EFF_SHARPEN (CIF_IMG_EFF_BASE + 0x00000024)
782
783 #define CIF_RKSHARP_CTRL (CIF_IMG_EFF_BASE + 0x00000030)
784 #define CIF_RKSHARP_YAVG_THR (CIF_IMG_EFF_BASE + 0x00000034)
785 #define CIF_RKSHARP_DELTA_P0_P1 (CIF_IMG_EFF_BASE + 0x00000038)
786 #define CIF_RKSHARP_DELTA_P2_P3 (CIF_IMG_EFF_BASE + 0x0000003c)
787 #define CIF_RKSHARP_DELTA_P4 (CIF_IMG_EFF_BASE + 0x00000040)
788 #define CIF_RKSHARP_NPIXEL_P0_P1_P2_P3 (CIF_IMG_EFF_BASE + 0x00000044)
789 #define CIF_RKSHARP_NPIXEL_P4 (CIF_IMG_EFF_BASE + 0x00000048)
790 #define CIF_RKSHARP_GAUSS_FLAT_COE1 (CIF_IMG_EFF_BASE + 0x0000004c)
791 #define CIF_RKSHARP_GAUSS_FLAT_COE2 (CIF_IMG_EFF_BASE + 0x00000050)
792 #define CIF_RKSHARP_GAUSS_FLAT_COE3 (CIF_IMG_EFF_BASE + 0x00000054)
793 #define CIF_RKSHARP_GAUSS_NOISE_COE1 (CIF_IMG_EFF_BASE + 0x00000058)
794 #define CIF_RKSHARP_GAUSS_NOISE_COE2 (CIF_IMG_EFF_BASE + 0x0000005c)
795 #define CIF_RKSHARP_GAUSS_NOISE_COE3 (CIF_IMG_EFF_BASE + 0x00000060)
796 #define CIF_RKSHARP_GAUSS_OTHER_COE1 (CIF_IMG_EFF_BASE + 0x00000064)
797 #define CIF_RKSHARP_GAUSS_OTHER_COE2 (CIF_IMG_EFF_BASE + 0x00000068)
798 #define CIF_RKSHARP_GAUSS_OTHER_COE3 (CIF_IMG_EFF_BASE + 0x0000006c)
799 #define CIF_RKSHARP_LINE1_FILTER_COE1 (CIF_IMG_EFF_BASE + 0x00000070)
800 #define CIF_RKSHARP_LINE1_FILTER_COE2 (CIF_IMG_EFF_BASE + 0x00000074)
801 #define CIF_RKSHARP_LINE2_FILTER_COE1 (CIF_IMG_EFF_BASE + 0x00000078)
802 #define CIF_RKSHARP_LINE2_FILTER_COE2 (CIF_IMG_EFF_BASE + 0x0000007c)
803 #define CIF_RKSHARP_LINE2_FILTER_COE3 (CIF_IMG_EFF_BASE + 0x00000080)
804 #define CIF_RKSHARP_LINE3_FILTER_COE1 (CIF_IMG_EFF_BASE + 0x00000084)
805 #define CIF_RKSHARP_LINE3_FILTER_COE2 (CIF_IMG_EFF_BASE + 0x00000088)
806 #define CIF_RKSHARP_GRAD_SEQ_P0_P1 (CIF_IMG_EFF_BASE + 0x0000008c)
807 #define CIF_RKSHARP_GRAD_SEQ_P2_P3 (CIF_IMG_EFF_BASE + 0x00000090)
808 #define CIF_RKSHARP_SHARP_FACTOR_P0_P1_P2 (CIF_IMG_EFF_BASE + 0x00000094)
809 #define CIF_RKSHARP_SHARP_FACTOR_P3_P4 (CIF_IMG_EFF_BASE + 0x00000098)
810 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE11_COE14 (CIF_IMG_EFF_BASE + 0x0000009c)
811 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE15_COE23 (CIF_IMG_EFF_BASE + 0x000000a0)
812 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE24_COE32 (CIF_IMG_EFF_BASE + 0x000000a4)
813 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE33_COE35 (CIF_IMG_EFF_BASE + 0x000000a8)
814 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE11_COE14 (CIF_IMG_EFF_BASE + 0x000000ac)
815 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE15_COE23 (CIF_IMG_EFF_BASE + 0x000000b0)
816 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE24_COE32 (CIF_IMG_EFF_BASE + 0x000000b4)
817 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE33_COE35 (CIF_IMG_EFF_BASE + 0x000000b8)
818 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE11_COE14 (CIF_IMG_EFF_BASE + 0x000000bc)
819 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE15_COE23 (CIF_IMG_EFF_BASE + 0x000000c0)
820 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE24_COE32 (CIF_IMG_EFF_BASE + 0x000000c4)
821 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE33_COE35 (CIF_IMG_EFF_BASE + 0x000000c8)
822
823 #define CIF_SUPER_IMP_BASE 0x00000300
824 #define CIF_SUPER_IMP_CTRL (CIF_SUPER_IMP_BASE + 0x00000000)
825 #define CIF_SUPER_IMP_OFFSET_X (CIF_SUPER_IMP_BASE + 0x00000004)
826 #define CIF_SUPER_IMP_OFFSET_Y (CIF_SUPER_IMP_BASE + 0x00000008)
827 #define CIF_SUPER_IMP_COLOR_Y (CIF_SUPER_IMP_BASE + 0x0000000C)
828 #define CIF_SUPER_IMP_COLOR_CB (CIF_SUPER_IMP_BASE + 0x00000010)
829 #define CIF_SUPER_IMP_COLOR_CR (CIF_SUPER_IMP_BASE + 0x00000014)
830
831 #define CIF_ISP_BASE 0x00000400
832 #define CIF_ISP_CTRL (CIF_ISP_BASE + 0x00000000)
833 #define CIF_ISP_ACQ_PROP (CIF_ISP_BASE + 0x00000004)
834 #define CIF_ISP_ACQ_H_OFFS (CIF_ISP_BASE + 0x00000008)
835 #define CIF_ISP_ACQ_V_OFFS (CIF_ISP_BASE + 0x0000000C)
836 #define CIF_ISP_ACQ_H_SIZE (CIF_ISP_BASE + 0x00000010)
837 #define CIF_ISP_ACQ_V_SIZE (CIF_ISP_BASE + 0x00000014)
838 #define CIF_ISP_ACQ_NR_FRAMES (CIF_ISP_BASE + 0x00000018)
839 #define CIF_ISP_GAMMA_DX_LO (CIF_ISP_BASE + 0x0000001C)
840 #define CIF_ISP_GAMMA_DX_HI (CIF_ISP_BASE + 0x00000020)
841 #define CIF_ISP_GAMMA_R_Y0 (CIF_ISP_BASE + 0x00000024)
842 #define CIF_ISP_GAMMA_R_Y1 (CIF_ISP_BASE + 0x00000028)
843 #define CIF_ISP_GAMMA_R_Y2 (CIF_ISP_BASE + 0x0000002C)
844 #define CIF_ISP_GAMMA_R_Y3 (CIF_ISP_BASE + 0x00000030)
845 #define CIF_ISP_GAMMA_R_Y4 (CIF_ISP_BASE + 0x00000034)
846 #define CIF_ISP_GAMMA_R_Y5 (CIF_ISP_BASE + 0x00000038)
847 #define CIF_ISP_GAMMA_R_Y6 (CIF_ISP_BASE + 0x0000003C)
848 #define CIF_ISP_GAMMA_R_Y7 (CIF_ISP_BASE + 0x00000040)
849 #define CIF_ISP_GAMMA_R_Y8 (CIF_ISP_BASE + 0x00000044)
850 #define CIF_ISP_GAMMA_R_Y9 (CIF_ISP_BASE + 0x00000048)
851 #define CIF_ISP_GAMMA_R_Y10 (CIF_ISP_BASE + 0x0000004C)
852 #define CIF_ISP_GAMMA_R_Y11 (CIF_ISP_BASE + 0x00000050)
853 #define CIF_ISP_GAMMA_R_Y12 (CIF_ISP_BASE + 0x00000054)
854 #define CIF_ISP_GAMMA_R_Y13 (CIF_ISP_BASE + 0x00000058)
855 #define CIF_ISP_GAMMA_R_Y14 (CIF_ISP_BASE + 0x0000005C)
856 #define CIF_ISP_GAMMA_R_Y15 (CIF_ISP_BASE + 0x00000060)
857 #define CIF_ISP_GAMMA_R_Y16 (CIF_ISP_BASE + 0x00000064)
858 #define CIF_ISP_GAMMA_G_Y0 (CIF_ISP_BASE + 0x00000068)
859 #define CIF_ISP_GAMMA_G_Y1 (CIF_ISP_BASE + 0x0000006C)
860 #define CIF_ISP_GAMMA_G_Y2 (CIF_ISP_BASE + 0x00000070)
861 #define CIF_ISP_GAMMA_G_Y3 (CIF_ISP_BASE + 0x00000074)
862 #define CIF_ISP_GAMMA_G_Y4 (CIF_ISP_BASE + 0x00000078)
863 #define CIF_ISP_GAMMA_G_Y5 (CIF_ISP_BASE + 0x0000007C)
864 #define CIF_ISP_GAMMA_G_Y6 (CIF_ISP_BASE + 0x00000080)
865 #define CIF_ISP_GAMMA_G_Y7 (CIF_ISP_BASE + 0x00000084)
866 #define CIF_ISP_GAMMA_G_Y8 (CIF_ISP_BASE + 0x00000088)
867 #define CIF_ISP_GAMMA_G_Y9 (CIF_ISP_BASE + 0x0000008C)
868 #define CIF_ISP_GAMMA_G_Y10 (CIF_ISP_BASE + 0x00000090)
869 #define CIF_ISP_GAMMA_G_Y11 (CIF_ISP_BASE + 0x00000094)
870 #define CIF_ISP_GAMMA_G_Y12 (CIF_ISP_BASE + 0x00000098)
871 #define CIF_ISP_GAMMA_G_Y13 (CIF_ISP_BASE + 0x0000009C)
872 #define CIF_ISP_GAMMA_G_Y14 (CIF_ISP_BASE + 0x000000A0)
873 #define CIF_ISP_GAMMA_G_Y15 (CIF_ISP_BASE + 0x000000A4)
874 #define CIF_ISP_GAMMA_G_Y16 (CIF_ISP_BASE + 0x000000A8)
875 #define CIF_ISP_GAMMA_B_Y0 (CIF_ISP_BASE + 0x000000AC)
876 #define CIF_ISP_GAMMA_B_Y1 (CIF_ISP_BASE + 0x000000B0)
877 #define CIF_ISP_GAMMA_B_Y2 (CIF_ISP_BASE + 0x000000B4)
878 #define CIF_ISP_GAMMA_B_Y3 (CIF_ISP_BASE + 0x000000B8)
879 #define CIF_ISP_GAMMA_B_Y4 (CIF_ISP_BASE + 0x000000BC)
880 #define CIF_ISP_GAMMA_B_Y5 (CIF_ISP_BASE + 0x000000C0)
881 #define CIF_ISP_GAMMA_B_Y6 (CIF_ISP_BASE + 0x000000C4)
882 #define CIF_ISP_GAMMA_B_Y7 (CIF_ISP_BASE + 0x000000C8)
883 #define CIF_ISP_GAMMA_B_Y8 (CIF_ISP_BASE + 0x000000CC)
884 #define CIF_ISP_GAMMA_B_Y9 (CIF_ISP_BASE + 0x000000D0)
885 #define CIF_ISP_GAMMA_B_Y10 (CIF_ISP_BASE + 0x000000D4)
886 #define CIF_ISP_GAMMA_B_Y11 (CIF_ISP_BASE + 0x000000D8)
887 #define CIF_ISP_GAMMA_B_Y12 (CIF_ISP_BASE + 0x000000DC)
888 #define CIF_ISP_GAMMA_B_Y13 (CIF_ISP_BASE + 0x000000E0)
889 #define CIF_ISP_GAMMA_B_Y14 (CIF_ISP_BASE + 0x000000E4)
890 #define CIF_ISP_GAMMA_B_Y15 (CIF_ISP_BASE + 0x000000E8)
891 #define CIF_ISP_GAMMA_B_Y16 (CIF_ISP_BASE + 0x000000EC)
892
893 #define CIF_ISP_AWB_PROP_V10 (CIF_ISP_BASE + 0x00000110)
894 #define CIF_ISP_AWB_WND_H_OFFS_V10 (CIF_ISP_BASE + 0x00000114)
895 #define CIF_ISP_AWB_WND_V_OFFS_V10 (CIF_ISP_BASE + 0x00000118)
896 #define CIF_ISP_AWB_WND_H_SIZE_V10 (CIF_ISP_BASE + 0x0000011C)
897 #define CIF_ISP_AWB_WND_V_SIZE_V10 (CIF_ISP_BASE + 0x00000120)
898 #define CIF_ISP_AWB_FRAMES_V10 (CIF_ISP_BASE + 0x00000124)
899 #define CIF_ISP_AWB_REF_V10 (CIF_ISP_BASE + 0x00000128)
900 #define CIF_ISP_AWB_THRESH_V10 (CIF_ISP_BASE + 0x0000012C)
901 #define CIF_ISP_AWB_GAIN_G_V10 (CIF_ISP_BASE + 0x00000138)
902 #define CIF_ISP_AWB_GAIN_RB_V10 (CIF_ISP_BASE + 0x0000013C)
903 #define CIF_ISP_AWB_WHITE_CNT_V10 (CIF_ISP_BASE + 0x00000140)
904 #define CIF_ISP_AWB_MEAN_V10 (CIF_ISP_BASE + 0x00000144)
905
906 #define CIF_ISP_AWB_PROP_V12 (CIF_ISP_BASE + 0x00000110)
907 #define CIF_ISP_AWB_SIZE_V12 (CIF_ISP_BASE + 0x00000114)
908 #define CIF_ISP_AWB_OFFS_V12 (CIF_ISP_BASE + 0x00000118)
909 #define CIF_ISP_AWB_REF_V12 (CIF_ISP_BASE + 0x0000011C)
910 #define CIF_ISP_AWB_THRESH_V12 (CIF_ISP_BASE + 0x00000120)
911 #define CIF_ISP_X_COOR12_V12 (CIF_ISP_BASE + 0x00000124)
912 #define CIF_ISP_X_COOR34_V12 (CIF_ISP_BASE + 0x00000128)
913 #define CIF_ISP_AWB_WHITE_CNT_V12 (CIF_ISP_BASE + 0x0000012C)
914 #define CIF_ISP_AWB_MEAN_V12 (CIF_ISP_BASE + 0x00000130)
915 #define CIF_ISP_DEGAIN_V12 (CIF_ISP_BASE + 0x00000134)
916 #define CIF_ISP_AWB_GAIN_G_V12 (CIF_ISP_BASE + 0x00000138)
917 #define CIF_ISP_AWB_GAIN_RB_V12 (CIF_ISP_BASE + 0x0000013C)
918 #define CIF_ISP_REGION_LINE_V12 (CIF_ISP_BASE + 0x00000140)
919 #define CIF_ISP_WP_CNT_REGION0_V12 (CIF_ISP_BASE + 0x00000160)
920 #define CIF_ISP_WP_CNT_REGION1_V12 (CIF_ISP_BASE + 0x00000164)
921 #define CIF_ISP_WP_CNT_REGION2_V12 (CIF_ISP_BASE + 0x00000168)
922 #define CIF_ISP_WP_CNT_REGION3_V12 (CIF_ISP_BASE + 0x0000016C)
923
924 #define CIF_ISP_CC_COEFF_0 (CIF_ISP_BASE + 0x00000170)
925 #define CIF_ISP_CC_COEFF_1 (CIF_ISP_BASE + 0x00000174)
926 #define CIF_ISP_CC_COEFF_2 (CIF_ISP_BASE + 0x00000178)
927 #define CIF_ISP_CC_COEFF_3 (CIF_ISP_BASE + 0x0000017C)
928 #define CIF_ISP_CC_COEFF_4 (CIF_ISP_BASE + 0x00000180)
929 #define CIF_ISP_CC_COEFF_5 (CIF_ISP_BASE + 0x00000184)
930 #define CIF_ISP_CC_COEFF_6 (CIF_ISP_BASE + 0x00000188)
931 #define CIF_ISP_CC_COEFF_7 (CIF_ISP_BASE + 0x0000018C)
932 #define CIF_ISP_CC_COEFF_8 (CIF_ISP_BASE + 0x00000190)
933 #define CIF_ISP_OUT_H_OFFS (CIF_ISP_BASE + 0x00000194)
934 #define CIF_ISP_OUT_V_OFFS (CIF_ISP_BASE + 0x00000198)
935 #define CIF_ISP_OUT_H_SIZE (CIF_ISP_BASE + 0x0000019C)
936 #define CIF_ISP_OUT_V_SIZE (CIF_ISP_BASE + 0x000001A0)
937 #define CIF_ISP_DEMOSAIC (CIF_ISP_BASE + 0x000001A4)
938 #define CIF_ISP_FLAGS_SHD (CIF_ISP_BASE + 0x000001A8)
939 #define CIF_ISP_OUT_H_OFFS_SHD (CIF_ISP_BASE + 0x000001AC)
940 #define CIF_ISP_OUT_V_OFFS_SHD (CIF_ISP_BASE + 0x000001B0)
941 #define CIF_ISP_OUT_H_SIZE_SHD (CIF_ISP_BASE + 0x000001B4)
942 #define CIF_ISP_OUT_V_SIZE_SHD (CIF_ISP_BASE + 0x000001B8)
943 #define CIF_ISP_IMSC (CIF_ISP_BASE + 0x000001BC)
944 #define CIF_ISP_RIS (CIF_ISP_BASE + 0x000001C0)
945 #define CIF_ISP_MIS (CIF_ISP_BASE + 0x000001C4)
946 #define CIF_ISP_ICR (CIF_ISP_BASE + 0x000001C8)
947 #define CIF_ISP_ISR (CIF_ISP_BASE + 0x000001CC)
948 #define CIF_ISP_CT_COEFF_0 (CIF_ISP_BASE + 0x000001D0)
949 #define CIF_ISP_CT_COEFF_1 (CIF_ISP_BASE + 0x000001D4)
950 #define CIF_ISP_CT_COEFF_2 (CIF_ISP_BASE + 0x000001D8)
951 #define CIF_ISP_CT_COEFF_3 (CIF_ISP_BASE + 0x000001DC)
952 #define CIF_ISP_CT_COEFF_4 (CIF_ISP_BASE + 0x000001E0)
953 #define CIF_ISP_CT_COEFF_5 (CIF_ISP_BASE + 0x000001E4)
954 #define CIF_ISP_CT_COEFF_6 (CIF_ISP_BASE + 0x000001E8)
955 #define CIF_ISP_CT_COEFF_7 (CIF_ISP_BASE + 0x000001EC)
956 #define CIF_ISP_CT_COEFF_8 (CIF_ISP_BASE + 0x000001F0)
957 #define CIF_ISP_GAMMA_OUT_MODE_V10 (CIF_ISP_BASE + 0x000001F4)
958 #define CIF_ISP_GAMMA_OUT_Y_0_V10 (CIF_ISP_BASE + 0x000001F8)
959 #define CIF_ISP_GAMMA_OUT_Y_1_V10 (CIF_ISP_BASE + 0x000001FC)
960 #define CIF_ISP_GAMMA_OUT_Y_2_V10 (CIF_ISP_BASE + 0x00000200)
961 #define CIF_ISP_GAMMA_OUT_Y_3_V10 (CIF_ISP_BASE + 0x00000204)
962 #define CIF_ISP_GAMMA_OUT_Y_4_V10 (CIF_ISP_BASE + 0x00000208)
963 #define CIF_ISP_GAMMA_OUT_Y_5_V10 (CIF_ISP_BASE + 0x0000020C)
964 #define CIF_ISP_GAMMA_OUT_Y_6_V10 (CIF_ISP_BASE + 0x00000210)
965 #define CIF_ISP_GAMMA_OUT_Y_7_V10 (CIF_ISP_BASE + 0x00000214)
966 #define CIF_ISP_GAMMA_OUT_Y_8_V10 (CIF_ISP_BASE + 0x00000218)
967 #define CIF_ISP_GAMMA_OUT_Y_9_V10 (CIF_ISP_BASE + 0x0000021C)
968 #define CIF_ISP_GAMMA_OUT_Y_10_V10 (CIF_ISP_BASE + 0x00000220)
969 #define CIF_ISP_GAMMA_OUT_Y_11_V10 (CIF_ISP_BASE + 0x00000224)
970 #define CIF_ISP_GAMMA_OUT_Y_12_V10 (CIF_ISP_BASE + 0x00000228)
971 #define CIF_ISP_GAMMA_OUT_Y_13_V10 (CIF_ISP_BASE + 0x0000022C)
972 #define CIF_ISP_GAMMA_OUT_Y_14_V10 (CIF_ISP_BASE + 0x00000230)
973 #define CIF_ISP_GAMMA_OUT_Y_15_V10 (CIF_ISP_BASE + 0x00000234)
974 #define CIF_ISP_GAMMA_OUT_Y_16_V10 (CIF_ISP_BASE + 0x00000238)
975 #define CIF_ISP_ERR (CIF_ISP_BASE + 0x0000023C)
976 #define CIF_ISP_ERR_CLR (CIF_ISP_BASE + 0x00000240)
977 #define CIF_ISP_FRAME_COUNT (CIF_ISP_BASE + 0x00000244)
978 #define CIF_ISP_CT_OFFSET_R (CIF_ISP_BASE + 0x00000248)
979 #define CIF_ISP_CT_OFFSET_G (CIF_ISP_BASE + 0x0000024C)
980 #define CIF_ISP_CT_OFFSET_B (CIF_ISP_BASE + 0x00000250)
981 #define CIF_ISP_GAMMA_OUT_MODE_V12 (CIF_ISP_BASE + 0x00000300)
982 #define CIF_ISP_GAMMA_OUT_Y_0_V12 (CIF_ISP_BASE + 0x00000304)
983
984 #define CIF_ISP_FLASH_BASE 0x00000660
985 #define CIF_ISP_FLASH_CMD (CIF_ISP_FLASH_BASE + 0x00000000)
986 #define CIF_ISP_FLASH_CONFIG (CIF_ISP_FLASH_BASE + 0x00000004)
987 #define CIF_ISP_FLASH_PREDIV (CIF_ISP_FLASH_BASE + 0x00000008)
988 #define CIF_ISP_FLASH_DELAY (CIF_ISP_FLASH_BASE + 0x0000000C)
989 #define CIF_ISP_FLASH_TIME (CIF_ISP_FLASH_BASE + 0x00000010)
990 #define CIF_ISP_FLASH_MAXP (CIF_ISP_FLASH_BASE + 0x00000014)
991
992 #define CIF_ISP_SH_BASE 0x00000680
993 #define CIF_ISP_SH_CTRL (CIF_ISP_SH_BASE + 0x00000000)
994 #define CIF_ISP_SH_PREDIV (CIF_ISP_SH_BASE + 0x00000004)
995 #define CIF_ISP_SH_DELAY (CIF_ISP_SH_BASE + 0x00000008)
996 #define CIF_ISP_SH_TIME (CIF_ISP_SH_BASE + 0x0000000C)
997
998 #define CIF_C_PROC_BASE 0x00000800
999 #define CIF_C_PROC_CTRL (CIF_C_PROC_BASE + 0x00000000)
1000 #define CIF_C_PROC_CONTRAST (CIF_C_PROC_BASE + 0x00000004)
1001 #define CIF_C_PROC_BRIGHTNESS (CIF_C_PROC_BASE + 0x00000008)
1002 #define CIF_C_PROC_SATURATION (CIF_C_PROC_BASE + 0x0000000C)
1003 #define CIF_C_PROC_HUE (CIF_C_PROC_BASE + 0x00000010)
1004
1005 #define CIF_DUAL_CROP_BASE 0x00000880
1006 #define CIF_DUAL_CROP_CTRL (CIF_DUAL_CROP_BASE + 0x00000000)
1007 #define CIF_DUAL_CROP_M_H_OFFS (CIF_DUAL_CROP_BASE + 0x00000004)
1008 #define CIF_DUAL_CROP_M_V_OFFS (CIF_DUAL_CROP_BASE + 0x00000008)
1009 #define CIF_DUAL_CROP_M_H_SIZE (CIF_DUAL_CROP_BASE + 0x0000000C)
1010 #define CIF_DUAL_CROP_M_V_SIZE (CIF_DUAL_CROP_BASE + 0x00000010)
1011 #define CIF_DUAL_CROP_S_H_OFFS (CIF_DUAL_CROP_BASE + 0x00000014)
1012 #define CIF_DUAL_CROP_S_V_OFFS (CIF_DUAL_CROP_BASE + 0x00000018)
1013 #define CIF_DUAL_CROP_S_H_SIZE (CIF_DUAL_CROP_BASE + 0x0000001C)
1014 #define CIF_DUAL_CROP_S_V_SIZE (CIF_DUAL_CROP_BASE + 0x00000020)
1015 #define CIF_DUAL_CROP_M_H_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000024)
1016 #define CIF_DUAL_CROP_M_V_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000028)
1017 #define CIF_DUAL_CROP_M_H_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x0000002C)
1018 #define CIF_DUAL_CROP_M_V_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x00000030)
1019 #define CIF_DUAL_CROP_S_H_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000034)
1020 #define CIF_DUAL_CROP_S_V_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000038)
1021 #define CIF_DUAL_CROP_S_H_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x0000003C)
1022 #define CIF_DUAL_CROP_S_V_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x00000040)
1023
1024 #define CIF_MRSZ_BASE 0x00000C00
1025 #define CIF_MRSZ_CTRL (CIF_MRSZ_BASE + 0x00000000)
1026 #define CIF_MRSZ_SCALE_HY (CIF_MRSZ_BASE + 0x00000004)
1027 #define CIF_MRSZ_SCALE_HCB (CIF_MRSZ_BASE + 0x00000008)
1028 #define CIF_MRSZ_SCALE_HCR (CIF_MRSZ_BASE + 0x0000000C)
1029 #define CIF_MRSZ_SCALE_VY (CIF_MRSZ_BASE + 0x00000010)
1030 #define CIF_MRSZ_SCALE_VC (CIF_MRSZ_BASE + 0x00000014)
1031 #define CIF_MRSZ_PHASE_HY (CIF_MRSZ_BASE + 0x00000018)
1032 #define CIF_MRSZ_PHASE_HC (CIF_MRSZ_BASE + 0x0000001C)
1033 #define CIF_MRSZ_PHASE_VY (CIF_MRSZ_BASE + 0x00000020)
1034 #define CIF_MRSZ_PHASE_VC (CIF_MRSZ_BASE + 0x00000024)
1035 #define CIF_MRSZ_SCALE_LUT_ADDR (CIF_MRSZ_BASE + 0x00000028)
1036 #define CIF_MRSZ_SCALE_LUT (CIF_MRSZ_BASE + 0x0000002C)
1037 #define CIF_MRSZ_CTRL_SHD (CIF_MRSZ_BASE + 0x00000030)
1038 #define CIF_MRSZ_SCALE_HY_SHD (CIF_MRSZ_BASE + 0x00000034)
1039 #define CIF_MRSZ_SCALE_HCB_SHD (CIF_MRSZ_BASE + 0x00000038)
1040 #define CIF_MRSZ_SCALE_HCR_SHD (CIF_MRSZ_BASE + 0x0000003C)
1041 #define CIF_MRSZ_SCALE_VY_SHD (CIF_MRSZ_BASE + 0x00000040)
1042 #define CIF_MRSZ_SCALE_VC_SHD (CIF_MRSZ_BASE + 0x00000044)
1043 #define CIF_MRSZ_PHASE_HY_SHD (CIF_MRSZ_BASE + 0x00000048)
1044 #define CIF_MRSZ_PHASE_HC_SHD (CIF_MRSZ_BASE + 0x0000004C)
1045 #define CIF_MRSZ_PHASE_VY_SHD (CIF_MRSZ_BASE + 0x00000050)
1046 #define CIF_MRSZ_PHASE_VC_SHD (CIF_MRSZ_BASE + 0x00000054)
1047
1048 #define CIF_SRSZ_BASE 0x00001000
1049 #define CIF_SRSZ_CTRL (CIF_SRSZ_BASE + 0x00000000)
1050 #define CIF_SRSZ_SCALE_HY (CIF_SRSZ_BASE + 0x00000004)
1051 #define CIF_SRSZ_SCALE_HCB (CIF_SRSZ_BASE + 0x00000008)
1052 #define CIF_SRSZ_SCALE_HCR (CIF_SRSZ_BASE + 0x0000000C)
1053 #define CIF_SRSZ_SCALE_VY (CIF_SRSZ_BASE + 0x00000010)
1054 #define CIF_SRSZ_SCALE_VC (CIF_SRSZ_BASE + 0x00000014)
1055 #define CIF_SRSZ_PHASE_HY (CIF_SRSZ_BASE + 0x00000018)
1056 #define CIF_SRSZ_PHASE_HC (CIF_SRSZ_BASE + 0x0000001C)
1057 #define CIF_SRSZ_PHASE_VY (CIF_SRSZ_BASE + 0x00000020)
1058 #define CIF_SRSZ_PHASE_VC (CIF_SRSZ_BASE + 0x00000024)
1059 #define CIF_SRSZ_SCALE_LUT_ADDR (CIF_SRSZ_BASE + 0x00000028)
1060 #define CIF_SRSZ_SCALE_LUT (CIF_SRSZ_BASE + 0x0000002C)
1061 #define CIF_SRSZ_CTRL_SHD (CIF_SRSZ_BASE + 0x00000030)
1062 #define CIF_SRSZ_SCALE_HY_SHD (CIF_SRSZ_BASE + 0x00000034)
1063 #define CIF_SRSZ_SCALE_HCB_SHD (CIF_SRSZ_BASE + 0x00000038)
1064 #define CIF_SRSZ_SCALE_HCR_SHD (CIF_SRSZ_BASE + 0x0000003C)
1065 #define CIF_SRSZ_SCALE_VY_SHD (CIF_SRSZ_BASE + 0x00000040)
1066 #define CIF_SRSZ_SCALE_VC_SHD (CIF_SRSZ_BASE + 0x00000044)
1067 #define CIF_SRSZ_PHASE_HY_SHD (CIF_SRSZ_BASE + 0x00000048)
1068 #define CIF_SRSZ_PHASE_HC_SHD (CIF_SRSZ_BASE + 0x0000004C)
1069 #define CIF_SRSZ_PHASE_VY_SHD (CIF_SRSZ_BASE + 0x00000050)
1070 #define CIF_SRSZ_PHASE_VC_SHD (CIF_SRSZ_BASE + 0x00000054)
1071
1072 #define CIF_MI_BASE 0x00001400
1073 #define CIF_MI_CTRL (CIF_MI_BASE + 0x00000000)
1074 #define CIF_MI_INIT (CIF_MI_BASE + 0x00000004)
1075 #define CIF_MI_MP_Y_BASE_AD_INIT (CIF_MI_BASE + 0x00000008)
1076 #define CIF_MI_MP_Y_SIZE_INIT (CIF_MI_BASE + 0x0000000C)
1077 #define CIF_MI_MP_Y_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000010)
1078 #define CIF_MI_MP_Y_OFFS_CNT_START (CIF_MI_BASE + 0x00000014)
1079 #define CIF_MI_MP_Y_IRQ_OFFS_INIT (CIF_MI_BASE + 0x00000018)
1080 #define CIF_MI_MP_CB_BASE_AD_INIT (CIF_MI_BASE + 0x0000001C)
1081 #define CIF_MI_MP_CB_SIZE_INIT (CIF_MI_BASE + 0x00000020)
1082 #define CIF_MI_MP_CB_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000024)
1083 #define CIF_MI_MP_CB_OFFS_CNT_START (CIF_MI_BASE + 0x00000028)
1084 #define CIF_MI_MP_CR_BASE_AD_INIT (CIF_MI_BASE + 0x0000002C)
1085 #define CIF_MI_MP_CR_SIZE_INIT (CIF_MI_BASE + 0x00000030)
1086 #define CIF_MI_MP_CR_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000034)
1087 #define CIF_MI_MP_CR_OFFS_CNT_START (CIF_MI_BASE + 0x00000038)
1088 #define CIF_MI_SP_Y_BASE_AD_INIT (CIF_MI_BASE + 0x0000003C)
1089 #define CIF_MI_SP_Y_SIZE_INIT (CIF_MI_BASE + 0x00000040)
1090 #define CIF_MI_SP_Y_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000044)
1091 #define CIF_MI_SP_Y_OFFS_CNT_START (CIF_MI_BASE + 0x00000048)
1092 #define CIF_MI_SP_Y_LLENGTH (CIF_MI_BASE + 0x0000004C)
1093 #define CIF_MI_SP_CB_BASE_AD_INIT (CIF_MI_BASE + 0x00000050)
1094 #define CIF_MI_SP_CB_SIZE_INIT (CIF_MI_BASE + 0x00000054)
1095 #define CIF_MI_SP_CB_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000058)
1096 #define CIF_MI_SP_CB_OFFS_CNT_START (CIF_MI_BASE + 0x0000005C)
1097 #define CIF_MI_SP_CR_BASE_AD_INIT (CIF_MI_BASE + 0x00000060)
1098 #define CIF_MI_SP_CR_SIZE_INIT (CIF_MI_BASE + 0x00000064)
1099 #define CIF_MI_SP_CR_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000068)
1100 #define CIF_MI_SP_CR_OFFS_CNT_START (CIF_MI_BASE + 0x0000006C)
1101 #define CIF_MI_BYTE_CNT (CIF_MI_BASE + 0x00000070)
1102 #define CIF_MI_CTRL_SHD (CIF_MI_BASE + 0x00000074)
1103 #define CIF_MI_MP_Y_BASE_AD_SHD (CIF_MI_BASE + 0x00000078)
1104 #define CIF_MI_MP_Y_SIZE_SHD (CIF_MI_BASE + 0x0000007C)
1105 #define CIF_MI_MP_Y_OFFS_CNT_SHD (CIF_MI_BASE + 0x00000080)
1106 #define CIF_MI_MP_Y_IRQ_OFFS_SHD (CIF_MI_BASE + 0x00000084)
1107 #define CIF_MI_MP_CB_BASE_AD_SHD (CIF_MI_BASE + 0x00000088)
1108 #define CIF_MI_MP_CB_SIZE_SHD (CIF_MI_BASE + 0x0000008C)
1109 #define CIF_MI_MP_CB_OFFS_CNT_SHD (CIF_MI_BASE + 0x00000090)
1110 #define CIF_MI_MP_CR_BASE_AD_SHD (CIF_MI_BASE + 0x00000094)
1111 #define CIF_MI_MP_CR_SIZE_SHD (CIF_MI_BASE + 0x00000098)
1112 #define CIF_MI_MP_CR_OFFS_CNT_SHD (CIF_MI_BASE + 0x0000009C)
1113 #define CIF_MI_SP_Y_BASE_AD_SHD (CIF_MI_BASE + 0x000000A0)
1114 #define CIF_MI_SP_Y_SIZE_SHD (CIF_MI_BASE + 0x000000A4)
1115 #define CIF_MI_SP_Y_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000A8)
1116 #define CIF_MI_SP_CB_BASE_AD_SHD (CIF_MI_BASE + 0x000000B0)
1117 #define CIF_MI_SP_CB_SIZE_SHD (CIF_MI_BASE + 0x000000B4)
1118 #define CIF_MI_SP_CB_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000B8)
1119 #define CIF_MI_SP_CR_BASE_AD_SHD (CIF_MI_BASE + 0x000000BC)
1120 #define CIF_MI_SP_CR_SIZE_SHD (CIF_MI_BASE + 0x000000C0)
1121 #define CIF_MI_SP_CR_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000C4)
1122 #define CIF_MI_DMA_Y_PIC_START_AD (CIF_MI_BASE + 0x000000C8)
1123 #define CIF_MI_DMA_Y_PIC_WIDTH (CIF_MI_BASE + 0x000000CC)
1124 #define CIF_MI_DMA_Y_LLENGTH (CIF_MI_BASE + 0x000000D0)
1125 #define CIF_MI_DMA_Y_PIC_SIZE (CIF_MI_BASE + 0x000000D4)
1126 #define CIF_MI_DMA_CB_PIC_START_AD (CIF_MI_BASE + 0x000000D8)
1127 #define CIF_MI_DMA_CR_PIC_START_AD (CIF_MI_BASE + 0x000000E8)
1128 #define CIF_MI_IMSC (CIF_MI_BASE + 0x000000F8)
1129 #define CIF_MI_RIS (CIF_MI_BASE + 0x000000FC)
1130 #define CIF_MI_MIS (CIF_MI_BASE + 0x00000100)
1131 #define CIF_MI_ICR (CIF_MI_BASE + 0x00000104)
1132 #define CIF_MI_ISR (CIF_MI_BASE + 0x00000108)
1133 #define CIF_MI_STATUS (CIF_MI_BASE + 0x0000010C)
1134 #define CIF_MI_STATUS_CLR (CIF_MI_BASE + 0x00000110)
1135 #define CIF_MI_SP_Y_PIC_WIDTH (CIF_MI_BASE + 0x00000114)
1136 #define CIF_MI_SP_Y_PIC_HEIGHT (CIF_MI_BASE + 0x00000118)
1137 #define CIF_MI_SP_Y_PIC_SIZE (CIF_MI_BASE + 0x0000011C)
1138 #define CIF_MI_DMA_CTRL (CIF_MI_BASE + 0x00000120)
1139 #define CIF_MI_DMA_START (CIF_MI_BASE + 0x00000124)
1140 #define CIF_MI_DMA_STATUS (CIF_MI_BASE + 0x00000128)
1141 #define CIF_MI_PIXEL_COUNT (CIF_MI_BASE + 0x0000012C)
1142 #define CIF_MI_MP_Y_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000130)
1143 #define CIF_MI_MP_CB_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000134)
1144 #define CIF_MI_MP_CR_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000138)
1145 #define CIF_MI_SP_Y_BASE_AD_INIT2 (CIF_MI_BASE + 0x0000013C)
1146 #define CIF_MI_SP_CB_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000140)
1147 #define CIF_MI_SP_CR_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000144)
1148 #define CIF_MI_XTD_FORMAT_CTRL (CIF_MI_BASE + 0x00000148)
1149 #define CIF_MI_CTRL2 (CIF_MI_BASE + 0x00000150)
1150 #define CIF_MI_RAW0_BASE_AD_INIT (CIF_MI_BASE + 0x00000160)
1151 #define CIF_MI_RAW0_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000164)
1152 #define CIF_MI_RAW0_IRQ_OFFS_INIT (CIF_MI_BASE + 0x00000168)
1153 #define CIF_MI_RAW0_SIZE_INIT (CIF_MI_BASE + 0x0000016c)
1154 #define CIF_MI_RAW0_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000170)
1155 #define CIF_MI_RAW0_LENGTH (CIF_MI_BASE + 0x00000174)
1156 #define CIF_MI_RAW0_OFFS_CNT_START_SHD (CIF_MI_BASE + 0x00000178)
1157 #define CIF_MI_RAW0_BASE_AS_SHD (CIF_MI_BASE + 0x00000180)
1158 #define CIF_MI_RAW0_IRQ_OFFS_INI_SHD (CIF_MI_BASE + 0x00000184)
1159 #define CIF_MI_RAW0_SIZE_INIT_SHD (CIF_MI_BASE + 0x00000188)
1160 #define CIF_MI_RAW0_OFFS_CNT_INIT_SHD (CIF_MI_BASE + 0x0000018c)
1161
1162 #define CIF_SMIA_BASE 0x00001A00
1163 #define CIF_SMIA_CTRL (CIF_SMIA_BASE + 0x00000000)
1164 #define CIF_SMIA_STATUS (CIF_SMIA_BASE + 0x00000004)
1165 #define CIF_SMIA_IMSC (CIF_SMIA_BASE + 0x00000008)
1166 #define CIF_SMIA_RIS (CIF_SMIA_BASE + 0x0000000C)
1167 #define CIF_SMIA_MIS (CIF_SMIA_BASE + 0x00000010)
1168 #define CIF_SMIA_ICR (CIF_SMIA_BASE + 0x00000014)
1169 #define CIF_SMIA_ISR (CIF_SMIA_BASE + 0x00000018)
1170 #define CIF_SMIA_DATA_FORMAT_SEL (CIF_SMIA_BASE + 0x0000001C)
1171 #define CIF_SMIA_SOF_EMB_DATA_LINES (CIF_SMIA_BASE + 0x00000020)
1172 #define CIF_SMIA_EMB_HSTART (CIF_SMIA_BASE + 0x00000024)
1173 #define CIF_SMIA_EMB_HSIZE (CIF_SMIA_BASE + 0x00000028)
1174 #define CIF_SMIA_EMB_VSTART (CIF_SMIA_BASE + 0x0000002c)
1175 #define CIF_SMIA_NUM_LINES (CIF_SMIA_BASE + 0x00000030)
1176 #define CIF_SMIA_EMB_DATA_FIFO (CIF_SMIA_BASE + 0x00000034)
1177 #define CIF_SMIA_EMB_DATA_WATERMARK (CIF_SMIA_BASE + 0x00000038)
1178
1179 #define CIF_MIPI_BASE 0x00001C00
1180 #define CIF_MIPI_CTRL (CIF_MIPI_BASE + 0x00000000)
1181 #define CIF_MIPI_STATUS (CIF_MIPI_BASE + 0x00000004)
1182 #define CIF_MIPI_IMSC (CIF_MIPI_BASE + 0x00000008)
1183 #define CIF_MIPI_RIS (CIF_MIPI_BASE + 0x0000000C)
1184 #define CIF_MIPI_MIS (CIF_MIPI_BASE + 0x00000010)
1185 #define CIF_MIPI_ICR (CIF_MIPI_BASE + 0x00000014)
1186 #define CIF_MIPI_ISR (CIF_MIPI_BASE + 0x00000018)
1187 #define CIF_MIPI_CUR_DATA_ID (CIF_MIPI_BASE + 0x0000001C)
1188 #define CIF_MIPI_IMG_DATA_SEL (CIF_MIPI_BASE + 0x00000020)
1189 #define CIF_MIPI_ADD_DATA_SEL_1 (CIF_MIPI_BASE + 0x00000024)
1190 #define CIF_MIPI_ADD_DATA_SEL_2 (CIF_MIPI_BASE + 0x00000028)
1191 #define CIF_MIPI_ADD_DATA_SEL_3 (CIF_MIPI_BASE + 0x0000002C)
1192 #define CIF_MIPI_ADD_DATA_SEL_4 (CIF_MIPI_BASE + 0x00000030)
1193 #define CIF_MIPI_ADD_DATA_FIFO (CIF_MIPI_BASE + 0x00000034)
1194 #define CIF_MIPI_FIFO_FILL_LEVEL (CIF_MIPI_BASE + 0x00000038)
1195 #define CIF_MIPI_COMPRESSED_MODE (CIF_MIPI_BASE + 0x0000003C)
1196 #define CIF_MIPI_FRAME (CIF_MIPI_BASE + 0x00000040)
1197 #define CIF_MIPI_GEN_SHORT_DT (CIF_MIPI_BASE + 0x00000044)
1198 #define CIF_MIPI_GEN_SHORT_8_9 (CIF_MIPI_BASE + 0x00000048)
1199 #define CIF_MIPI_GEN_SHORT_A_B (CIF_MIPI_BASE + 0x0000004C)
1200 #define CIF_MIPI_GEN_SHORT_C_D (CIF_MIPI_BASE + 0x00000050)
1201 #define CIF_MIPI_GEN_SHORT_E_F (CIF_MIPI_BASE + 0x00000054)
1202
1203 #define CIF_ISP_AFM_BASE 0x00002000
1204 #define CIF_ISP_AFM_CTRL (CIF_ISP_AFM_BASE + 0x00000000)
1205 #define CIF_ISP_AFM_LT_A (CIF_ISP_AFM_BASE + 0x00000004)
1206 #define CIF_ISP_AFM_RB_A (CIF_ISP_AFM_BASE + 0x00000008)
1207 #define CIF_ISP_AFM_LT_B (CIF_ISP_AFM_BASE + 0x0000000C)
1208 #define CIF_ISP_AFM_RB_B (CIF_ISP_AFM_BASE + 0x00000010)
1209 #define CIF_ISP_AFM_LT_C (CIF_ISP_AFM_BASE + 0x00000014)
1210 #define CIF_ISP_AFM_RB_C (CIF_ISP_AFM_BASE + 0x00000018)
1211 #define CIF_ISP_AFM_THRES (CIF_ISP_AFM_BASE + 0x0000001C)
1212 #define CIF_ISP_AFM_VAR_SHIFT (CIF_ISP_AFM_BASE + 0x00000020)
1213 #define CIF_ISP_AFM_SUM_A (CIF_ISP_AFM_BASE + 0x00000024)
1214 #define CIF_ISP_AFM_SUM_B (CIF_ISP_AFM_BASE + 0x00000028)
1215 #define CIF_ISP_AFM_SUM_C (CIF_ISP_AFM_BASE + 0x0000002C)
1216 #define CIF_ISP_AFM_LUM_A (CIF_ISP_AFM_BASE + 0x00000030)
1217 #define CIF_ISP_AFM_LUM_B (CIF_ISP_AFM_BASE + 0x00000034)
1218 #define CIF_ISP_AFM_LUM_C (CIF_ISP_AFM_BASE + 0x00000038)
1219
1220 #define CIF_ISP_LSC_BASE 0x00002200
1221 #define CIF_ISP_LSC_CTRL (CIF_ISP_LSC_BASE + 0x00000000)
1222 #define CIF_ISP_LSC_R_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000004)
1223 #define CIF_ISP_LSC_GR_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000008)
1224 #define CIF_ISP_LSC_B_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x0000000C)
1225 #define CIF_ISP_LSC_GB_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000010)
1226 #define CIF_ISP_LSC_R_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000014)
1227 #define CIF_ISP_LSC_GR_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000018)
1228 #define CIF_ISP_LSC_B_TABLE_DATA (CIF_ISP_LSC_BASE + 0x0000001C)
1229 #define CIF_ISP_LSC_GB_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000020)
1230 #define CIF_ISP_LSC_XGRAD_01 (CIF_ISP_LSC_BASE + 0x00000024)
1231 #define CIF_ISP_LSC_XGRAD_23 (CIF_ISP_LSC_BASE + 0x00000028)
1232 #define CIF_ISP_LSC_XGRAD_45 (CIF_ISP_LSC_BASE + 0x0000002C)
1233 #define CIF_ISP_LSC_XGRAD_67 (CIF_ISP_LSC_BASE + 0x00000030)
1234 #define CIF_ISP_LSC_YGRAD_01 (CIF_ISP_LSC_BASE + 0x00000034)
1235 #define CIF_ISP_LSC_YGRAD_23 (CIF_ISP_LSC_BASE + 0x00000038)
1236 #define CIF_ISP_LSC_YGRAD_45 (CIF_ISP_LSC_BASE + 0x0000003C)
1237 #define CIF_ISP_LSC_YGRAD_67 (CIF_ISP_LSC_BASE + 0x00000040)
1238 #define CIF_ISP_LSC_XSIZE_01 (CIF_ISP_LSC_BASE + 0x00000044)
1239 #define CIF_ISP_LSC_XSIZE_23 (CIF_ISP_LSC_BASE + 0x00000048)
1240 #define CIF_ISP_LSC_XSIZE_45 (CIF_ISP_LSC_BASE + 0x0000004C)
1241 #define CIF_ISP_LSC_XSIZE_67 (CIF_ISP_LSC_BASE + 0x00000050)
1242 #define CIF_ISP_LSC_YSIZE_01 (CIF_ISP_LSC_BASE + 0x00000054)
1243 #define CIF_ISP_LSC_YSIZE_23 (CIF_ISP_LSC_BASE + 0x00000058)
1244 #define CIF_ISP_LSC_YSIZE_45 (CIF_ISP_LSC_BASE + 0x0000005C)
1245 #define CIF_ISP_LSC_YSIZE_67 (CIF_ISP_LSC_BASE + 0x00000060)
1246 #define CIF_ISP_LSC_TABLE_SEL (CIF_ISP_LSC_BASE + 0x00000064)
1247 #define CIF_ISP_LSC_STATUS (CIF_ISP_LSC_BASE + 0x00000068)
1248
1249 #define CIF_ISP_IS_BASE 0x00002300
1250 #define CIF_ISP_IS_CTRL (CIF_ISP_IS_BASE + 0x00000000)
1251 #define CIF_ISP_IS_RECENTER (CIF_ISP_IS_BASE + 0x00000004)
1252 #define CIF_ISP_IS_H_OFFS (CIF_ISP_IS_BASE + 0x00000008)
1253 #define CIF_ISP_IS_V_OFFS (CIF_ISP_IS_BASE + 0x0000000C)
1254 #define CIF_ISP_IS_H_SIZE (CIF_ISP_IS_BASE + 0x00000010)
1255 #define CIF_ISP_IS_V_SIZE (CIF_ISP_IS_BASE + 0x00000014)
1256 #define CIF_ISP_IS_MAX_DX (CIF_ISP_IS_BASE + 0x00000018)
1257 #define CIF_ISP_IS_MAX_DY (CIF_ISP_IS_BASE + 0x0000001C)
1258 #define CIF_ISP_IS_DISPLACE (CIF_ISP_IS_BASE + 0x00000020)
1259 #define CIF_ISP_IS_H_OFFS_SHD (CIF_ISP_IS_BASE + 0x00000024)
1260 #define CIF_ISP_IS_V_OFFS_SHD (CIF_ISP_IS_BASE + 0x00000028)
1261 #define CIF_ISP_IS_H_SIZE_SHD (CIF_ISP_IS_BASE + 0x0000002C)
1262 #define CIF_ISP_IS_V_SIZE_SHD (CIF_ISP_IS_BASE + 0x00000030)
1263
1264 #define CIF_ISP_HIST_BASE_V10 0x00002400
1265 #define CIF_ISP_HIST_PROP_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000000)
1266 #define CIF_ISP_HIST_H_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000004)
1267 #define CIF_ISP_HIST_V_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000008)
1268 #define CIF_ISP_HIST_H_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000000C)
1269 #define CIF_ISP_HIST_V_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000010)
1270 #define CIF_ISP_HIST_BIN_0_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000014)
1271 #define CIF_ISP_HIST_BIN_1_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000018)
1272 #define CIF_ISP_HIST_BIN_2_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000001C)
1273 #define CIF_ISP_HIST_BIN_3_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000020)
1274 #define CIF_ISP_HIST_BIN_4_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000024)
1275 #define CIF_ISP_HIST_BIN_5_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000028)
1276 #define CIF_ISP_HIST_BIN_6_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000002C)
1277 #define CIF_ISP_HIST_BIN_7_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000030)
1278 #define CIF_ISP_HIST_BIN_8_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000034)
1279 #define CIF_ISP_HIST_BIN_9_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000038)
1280 #define CIF_ISP_HIST_BIN_10_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000003C)
1281 #define CIF_ISP_HIST_BIN_11_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000040)
1282 #define CIF_ISP_HIST_BIN_12_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000044)
1283 #define CIF_ISP_HIST_BIN_13_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000048)
1284 #define CIF_ISP_HIST_BIN_14_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000004C)
1285 #define CIF_ISP_HIST_BIN_15_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000050)
1286 #define CIF_ISP_HIST_WEIGHT_00TO30_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000054)
1287 #define CIF_ISP_HIST_WEIGHT_40TO21_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000058)
1288 #define CIF_ISP_HIST_WEIGHT_31TO12_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000005C)
1289 #define CIF_ISP_HIST_WEIGHT_22TO03_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000060)
1290 #define CIF_ISP_HIST_WEIGHT_13TO43_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000064)
1291 #define CIF_ISP_HIST_WEIGHT_04TO34_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000068)
1292 #define CIF_ISP_HIST_WEIGHT_44_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000006C)
1293
1294 #define CIF_ISP_FILT_BASE 0x00002500
1295 #define CIF_ISP_FILT_MODE (CIF_ISP_FILT_BASE + 0x00000000)
1296 #define CIF_ISP_FILT_THRESH_BL0 (CIF_ISP_FILT_BASE + 0x00000028)
1297 #define CIF_ISP_FILT_THRESH_BL1 (CIF_ISP_FILT_BASE + 0x0000002c)
1298 #define CIF_ISP_FILT_THRESH_SH0 (CIF_ISP_FILT_BASE + 0x00000030)
1299 #define CIF_ISP_FILT_THRESH_SH1 (CIF_ISP_FILT_BASE + 0x00000034)
1300 #define CIF_ISP_FILT_LUM_WEIGHT (CIF_ISP_FILT_BASE + 0x00000038)
1301 #define CIF_ISP_FILT_FAC_SH1 (CIF_ISP_FILT_BASE + 0x0000003c)
1302 #define CIF_ISP_FILT_FAC_SH0 (CIF_ISP_FILT_BASE + 0x00000040)
1303 #define CIF_ISP_FILT_FAC_MID (CIF_ISP_FILT_BASE + 0x00000044)
1304 #define CIF_ISP_FILT_FAC_BL0 (CIF_ISP_FILT_BASE + 0x00000048)
1305 #define CIF_ISP_FILT_FAC_BL1 (CIF_ISP_FILT_BASE + 0x0000004C)
1306 #define CIF_ISP_FILT_ISP_CAC_CTRL (CIF_ISP_FILT_BASE + 0x00000080)
1307 #define CIF_ISP_FILT_CAC_COUNT_START (CIF_ISP_FILT_BASE + 0x00000084)
1308 #define CIF_ISP_FILT_CAC_A (CIF_ISP_FILT_BASE + 0x00000088)
1309 #define CIF_ISP_FILT_CAC_B (CIF_ISP_FILT_BASE + 0x0000008c)
1310 #define CIF_ISP_FILT_CAC_C (CIF_ISP_FILT_BASE + 0x00000090)
1311 #define CIF_ISP_FILT_CAC_X_NORM (CIF_ISP_FILT_BASE + 0x00000094)
1312 #define CIF_ISP_FILT_CAC_Y_NORM (CIF_ISP_FILT_BASE + 0x00000098)
1313 #define CIF_ISP_FILT_LU_DIVID (CIF_ISP_FILT_BASE + 0x000000a0)
1314 #define CIF_ISP_FILT_THGRAD_DIVID0123 (CIF_ISP_FILT_BASE + 0x000000a4)
1315 #define CIF_ISP_FILT_THGRAD_DIVID4 (CIF_ISP_FILT_BASE + 0x000000a8)
1316 #define CIF_ISP_FILT_THDIFF_DIVID0123 (CIF_ISP_FILT_BASE + 0x000000ac)
1317 #define CIF_ISP_FILT_THDIFF_DIVID4 (CIF_ISP_FILT_BASE + 0x000000b0)
1318 #define CIF_ISP_FILT_THCSC_DIVID0123 (CIF_ISP_FILT_BASE + 0x000000b4)
1319 #define CIF_ISP_FILT_THCSC_DIVID4 (CIF_ISP_FILT_BASE + 0x000000b8)
1320 #define CIF_ISP_FILT_THVAR_DIVID01 (CIF_ISP_FILT_BASE + 0x000000bc)
1321 #define CIF_ISP_FILT_THVAR_DIVID23 (CIF_ISP_FILT_BASE + 0x000000c0)
1322 #define CIF_ISP_FILT_THVAR_DIVID4 (CIF_ISP_FILT_BASE + 0x000000c4)
1323 #define CIF_ISP_FILT_TH_GRAD (CIF_ISP_FILT_BASE + 0x000000c8)
1324 #define CIF_ISP_FILT_TH_DIFF (CIF_ISP_FILT_BASE + 0x000000cc)
1325 #define CIF_ISP_FILT_TH_CSC (CIF_ISP_FILT_BASE + 0x000000d0)
1326 #define CIF_ISP_FILT_TH_VAR (CIF_ISP_FILT_BASE + 0x000000d4)
1327 #define CIF_ISP_FILT_LELEL_SEL (CIF_ISP_FILT_BASE + 0x000000d8)
1328 #define CIF_ISP_FILT_R_FCT (CIF_ISP_FILT_BASE + 0x000000dc)
1329 #define CIF_ISP_FILT_B_FCT (CIF_ISP_FILT_BASE + 0x000000e0)
1330
1331 #define CIF_ISP_CAC_BASE 0x00002580
1332 #define CIF_ISP_CAC_CTRL (CIF_ISP_CAC_BASE + 0x00000000)
1333 #define CIF_ISP_CAC_COUNT_START (CIF_ISP_CAC_BASE + 0x00000004)
1334 #define CIF_ISP_CAC_A (CIF_ISP_CAC_BASE + 0x00000008)
1335 #define CIF_ISP_CAC_B (CIF_ISP_CAC_BASE + 0x0000000C)
1336 #define CIF_ISP_CAC_C (CIF_ISP_CAC_BASE + 0x00000010)
1337 #define CIF_ISP_X_NORM (CIF_ISP_CAC_BASE + 0x00000014)
1338 #define CIF_ISP_Y_NORM (CIF_ISP_CAC_BASE + 0x00000018)
1339
1340 #define CIF_ISP_EXP_BASE 0x00002600
1341 #define CIF_ISP_EXP_CTRL (CIF_ISP_EXP_BASE + 0x00000000)
1342 #define CIF_ISP_EXP_H_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000004)
1343 #define CIF_ISP_EXP_V_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000008)
1344 #define CIF_ISP_EXP_H_SIZE_V10 (CIF_ISP_EXP_BASE + 0x0000000C)
1345 #define CIF_ISP_EXP_V_SIZE_V10 (CIF_ISP_EXP_BASE + 0x00000010)
1346 #define CIF_ISP_EXP_SIZE_V12 (CIF_ISP_EXP_BASE + 0x00000004)
1347 #define CIF_ISP_EXP_OFFS_V12 (CIF_ISP_EXP_BASE + 0x00000008)
1348 #define CIF_ISP_EXP_MEAN_V12 (CIF_ISP_EXP_BASE + 0x0000000c)
1349 #define CIF_ISP_EXP_MEAN_00_V10 (CIF_ISP_EXP_BASE + 0x00000014)
1350 #define CIF_ISP_EXP_MEAN_10_V10 (CIF_ISP_EXP_BASE + 0x00000018)
1351 #define CIF_ISP_EXP_MEAN_20_V10 (CIF_ISP_EXP_BASE + 0x0000001c)
1352 #define CIF_ISP_EXP_MEAN_30_V10 (CIF_ISP_EXP_BASE + 0x00000020)
1353 #define CIF_ISP_EXP_MEAN_40_V10 (CIF_ISP_EXP_BASE + 0x00000024)
1354 #define CIF_ISP_EXP_MEAN_01_V10 (CIF_ISP_EXP_BASE + 0x00000028)
1355 #define CIF_ISP_EXP_MEAN_11_V10 (CIF_ISP_EXP_BASE + 0x0000002c)
1356 #define CIF_ISP_EXP_MEAN_21_V10 (CIF_ISP_EXP_BASE + 0x00000030)
1357 #define CIF_ISP_EXP_MEAN_31_V10 (CIF_ISP_EXP_BASE + 0x00000034)
1358 #define CIF_ISP_EXP_MEAN_41_V10 (CIF_ISP_EXP_BASE + 0x00000038)
1359 #define CIF_ISP_EXP_MEAN_02_V10 (CIF_ISP_EXP_BASE + 0x0000003c)
1360 #define CIF_ISP_EXP_MEAN_12_V10 (CIF_ISP_EXP_BASE + 0x00000040)
1361 #define CIF_ISP_EXP_MEAN_22_V10 (CIF_ISP_EXP_BASE + 0x00000044)
1362 #define CIF_ISP_EXP_MEAN_32_V10 (CIF_ISP_EXP_BASE + 0x00000048)
1363 #define CIF_ISP_EXP_MEAN_42_V10 (CIF_ISP_EXP_BASE + 0x0000004c)
1364 #define CIF_ISP_EXP_MEAN_03_V10 (CIF_ISP_EXP_BASE + 0x00000050)
1365 #define CIF_ISP_EXP_MEAN_13_V10 (CIF_ISP_EXP_BASE + 0x00000054)
1366 #define CIF_ISP_EXP_MEAN_23_V10 (CIF_ISP_EXP_BASE + 0x00000058)
1367 #define CIF_ISP_EXP_MEAN_33_V10 (CIF_ISP_EXP_BASE + 0x0000005c)
1368 #define CIF_ISP_EXP_MEAN_43_V10 (CIF_ISP_EXP_BASE + 0x00000060)
1369 #define CIF_ISP_EXP_MEAN_04_V10 (CIF_ISP_EXP_BASE + 0x00000064)
1370 #define CIF_ISP_EXP_MEAN_14_V10 (CIF_ISP_EXP_BASE + 0x00000068)
1371 #define CIF_ISP_EXP_MEAN_24_V10 (CIF_ISP_EXP_BASE + 0x0000006c)
1372 #define CIF_ISP_EXP_MEAN_34_V10 (CIF_ISP_EXP_BASE + 0x00000070)
1373 #define CIF_ISP_EXP_MEAN_44_V10 (CIF_ISP_EXP_BASE + 0x00000074)
1374
1375 #define CIF_ISP_BLS_BASE 0x00002700
1376 #define CIF_ISP_BLS_CTRL (CIF_ISP_BLS_BASE + 0x00000000)
1377 #define CIF_ISP_BLS_SAMPLES (CIF_ISP_BLS_BASE + 0x00000004)
1378 #define CIF_ISP_BLS_H1_START (CIF_ISP_BLS_BASE + 0x00000008)
1379 #define CIF_ISP_BLS_H1_STOP (CIF_ISP_BLS_BASE + 0x0000000c)
1380 #define CIF_ISP_BLS_V1_START (CIF_ISP_BLS_BASE + 0x00000010)
1381 #define CIF_ISP_BLS_V1_STOP (CIF_ISP_BLS_BASE + 0x00000014)
1382 #define CIF_ISP_BLS_H2_START (CIF_ISP_BLS_BASE + 0x00000018)
1383 #define CIF_ISP_BLS_H2_STOP (CIF_ISP_BLS_BASE + 0x0000001c)
1384 #define CIF_ISP_BLS_V2_START (CIF_ISP_BLS_BASE + 0x00000020)
1385 #define CIF_ISP_BLS_V2_STOP (CIF_ISP_BLS_BASE + 0x00000024)
1386 #define CIF_ISP_BLS_A_FIXED (CIF_ISP_BLS_BASE + 0x00000028)
1387 #define CIF_ISP_BLS_B_FIXED (CIF_ISP_BLS_BASE + 0x0000002c)
1388 #define CIF_ISP_BLS_C_FIXED (CIF_ISP_BLS_BASE + 0x00000030)
1389 #define CIF_ISP_BLS_D_FIXED (CIF_ISP_BLS_BASE + 0x00000034)
1390 #define CIF_ISP_BLS_A_MEASURED (CIF_ISP_BLS_BASE + 0x00000038)
1391 #define CIF_ISP_BLS_B_MEASURED (CIF_ISP_BLS_BASE + 0x0000003c)
1392 #define CIF_ISP_BLS_C_MEASURED (CIF_ISP_BLS_BASE + 0x00000040)
1393 #define CIF_ISP_BLS_D_MEASURED (CIF_ISP_BLS_BASE + 0x00000044)
1394
1395 #define CIF_ISP_DPF_BASE 0x00002800
1396 #define CIF_ISP_DPF_MODE (CIF_ISP_DPF_BASE + 0x00000000)
1397 #define CIF_ISP_DPF_STRENGTH_R (CIF_ISP_DPF_BASE + 0x00000004)
1398 #define CIF_ISP_DPF_STRENGTH_G (CIF_ISP_DPF_BASE + 0x00000008)
1399 #define CIF_ISP_DPF_STRENGTH_B (CIF_ISP_DPF_BASE + 0x0000000C)
1400 #define CIF_ISP_DPF_S_WEIGHT_G_1_4 (CIF_ISP_DPF_BASE + 0x00000010)
1401 #define CIF_ISP_DPF_S_WEIGHT_G_5_6 (CIF_ISP_DPF_BASE + 0x00000014)
1402 #define CIF_ISP_DPF_S_WEIGHT_RB_1_4 (CIF_ISP_DPF_BASE + 0x00000018)
1403 #define CIF_ISP_DPF_S_WEIGHT_RB_5_6 (CIF_ISP_DPF_BASE + 0x0000001C)
1404 #define CIF_ISP_DPF_NULL_COEFF_0 (CIF_ISP_DPF_BASE + 0x00000020)
1405 #define CIF_ISP_DPF_NULL_COEFF_1 (CIF_ISP_DPF_BASE + 0x00000024)
1406 #define CIF_ISP_DPF_NULL_COEFF_2 (CIF_ISP_DPF_BASE + 0x00000028)
1407 #define CIF_ISP_DPF_NULL_COEFF_3 (CIF_ISP_DPF_BASE + 0x0000002C)
1408 #define CIF_ISP_DPF_NULL_COEFF_4 (CIF_ISP_DPF_BASE + 0x00000030)
1409 #define CIF_ISP_DPF_NULL_COEFF_5 (CIF_ISP_DPF_BASE + 0x00000034)
1410 #define CIF_ISP_DPF_NULL_COEFF_6 (CIF_ISP_DPF_BASE + 0x00000038)
1411 #define CIF_ISP_DPF_NULL_COEFF_7 (CIF_ISP_DPF_BASE + 0x0000003C)
1412 #define CIF_ISP_DPF_NULL_COEFF_8 (CIF_ISP_DPF_BASE + 0x00000040)
1413 #define CIF_ISP_DPF_NULL_COEFF_9 (CIF_ISP_DPF_BASE + 0x00000044)
1414 #define CIF_ISP_DPF_NULL_COEFF_10 (CIF_ISP_DPF_BASE + 0x00000048)
1415 #define CIF_ISP_DPF_NULL_COEFF_11 (CIF_ISP_DPF_BASE + 0x0000004C)
1416 #define CIF_ISP_DPF_NULL_COEFF_12 (CIF_ISP_DPF_BASE + 0x00000050)
1417 #define CIF_ISP_DPF_NULL_COEFF_13 (CIF_ISP_DPF_BASE + 0x00000054)
1418 #define CIF_ISP_DPF_NULL_COEFF_14 (CIF_ISP_DPF_BASE + 0x00000058)
1419 #define CIF_ISP_DPF_NULL_COEFF_15 (CIF_ISP_DPF_BASE + 0x0000005C)
1420 #define CIF_ISP_DPF_NULL_COEFF_16 (CIF_ISP_DPF_BASE + 0x00000060)
1421 #define CIF_ISP_DPF_NF_GAIN_R (CIF_ISP_DPF_BASE + 0x00000064)
1422 #define CIF_ISP_DPF_NF_GAIN_GR (CIF_ISP_DPF_BASE + 0x00000068)
1423 #define CIF_ISP_DPF_NF_GAIN_GB (CIF_ISP_DPF_BASE + 0x0000006C)
1424 #define CIF_ISP_DPF_NF_GAIN_B (CIF_ISP_DPF_BASE + 0x00000070)
1425
1426 #define CIF_ISP_DPCC_BASE 0x00002900
1427 #define CIF_ISP_DPCC_MODE (CIF_ISP_DPCC_BASE + 0x00000000)
1428 #define CIF_ISP_DPCC_OUTPUT_MODE (CIF_ISP_DPCC_BASE + 0x00000004)
1429 #define CIF_ISP_DPCC_SET_USE (CIF_ISP_DPCC_BASE + 0x00000008)
1430 #define CIF_ISP_DPCC_METHODS_SET_1 (CIF_ISP_DPCC_BASE + 0x0000000C)
1431 #define CIF_ISP_DPCC_METHODS_SET_2 (CIF_ISP_DPCC_BASE + 0x00000010)
1432 #define CIF_ISP_DPCC_METHODS_SET_3 (CIF_ISP_DPCC_BASE + 0x00000014)
1433 #define CIF_ISP_DPCC_LINE_THRESH_1 (CIF_ISP_DPCC_BASE + 0x00000018)
1434 #define CIF_ISP_DPCC_LINE_MAD_FAC_1 (CIF_ISP_DPCC_BASE + 0x0000001C)
1435 #define CIF_ISP_DPCC_PG_FAC_1 (CIF_ISP_DPCC_BASE + 0x00000020)
1436 #define CIF_ISP_DPCC_RND_THRESH_1 (CIF_ISP_DPCC_BASE + 0x00000024)
1437 #define CIF_ISP_DPCC_RG_FAC_1 (CIF_ISP_DPCC_BASE + 0x00000028)
1438 #define CIF_ISP_DPCC_LINE_THRESH_2 (CIF_ISP_DPCC_BASE + 0x0000002C)
1439 #define CIF_ISP_DPCC_LINE_MAD_FAC_2 (CIF_ISP_DPCC_BASE + 0x00000030)
1440 #define CIF_ISP_DPCC_PG_FAC_2 (CIF_ISP_DPCC_BASE + 0x00000034)
1441 #define CIF_ISP_DPCC_RND_THRESH_2 (CIF_ISP_DPCC_BASE + 0x00000038)
1442 #define CIF_ISP_DPCC_RG_FAC_2 (CIF_ISP_DPCC_BASE + 0x0000003C)
1443 #define CIF_ISP_DPCC_LINE_THRESH_3 (CIF_ISP_DPCC_BASE + 0x00000040)
1444 #define CIF_ISP_DPCC_LINE_MAD_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000044)
1445 #define CIF_ISP_DPCC_PG_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000048)
1446 #define CIF_ISP_DPCC_RND_THRESH_3 (CIF_ISP_DPCC_BASE + 0x0000004C)
1447 #define CIF_ISP_DPCC_RG_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000050)
1448 #define CIF_ISP_DPCC_RO_LIMITS (CIF_ISP_DPCC_BASE + 0x00000054)
1449 #define CIF_ISP_DPCC_RND_OFFS (CIF_ISP_DPCC_BASE + 0x00000058)
1450 #define CIF_ISP_DPCC_BPT_CTRL (CIF_ISP_DPCC_BASE + 0x0000005C)
1451 #define CIF_ISP_DPCC_BPT_NUMBER (CIF_ISP_DPCC_BASE + 0x00000060)
1452 #define CIF_ISP_DPCC_BPT_ADDR (CIF_ISP_DPCC_BASE + 0x00000064)
1453 #define CIF_ISP_DPCC_BPT_DATA (CIF_ISP_DPCC_BASE + 0x00000068)
1454
1455 #define CIF_ISP_WDR_BASE 0x00002A00
1456 #define CIF_ISP_WDR_CTRL (CIF_ISP_WDR_BASE + 0x00000000)
1457 #define CIF_ISP_WDR_TONECURVE_1 (CIF_ISP_WDR_BASE + 0x00000004)
1458 #define CIF_ISP_WDR_TONECURVE_2 (CIF_ISP_WDR_BASE + 0x00000008)
1459 #define CIF_ISP_WDR_TONECURVE_3 (CIF_ISP_WDR_BASE + 0x0000000C)
1460 #define CIF_ISP_WDR_TONECURVE_4 (CIF_ISP_WDR_BASE + 0x00000010)
1461 #define CIF_ISP_WDR_TONECURVE_YM_0 (CIF_ISP_WDR_BASE + 0x00000014)
1462 #define CIF_ISP_WDR_TONECURVE_YM_1 (CIF_ISP_WDR_BASE + 0x00000018)
1463 #define CIF_ISP_WDR_TONECURVE_YM_2 (CIF_ISP_WDR_BASE + 0x0000001C)
1464 #define CIF_ISP_WDR_TONECURVE_YM_3 (CIF_ISP_WDR_BASE + 0x00000020)
1465 #define CIF_ISP_WDR_TONECURVE_YM_4 (CIF_ISP_WDR_BASE + 0x00000024)
1466 #define CIF_ISP_WDR_TONECURVE_YM_5 (CIF_ISP_WDR_BASE + 0x00000028)
1467 #define CIF_ISP_WDR_TONECURVE_YM_6 (CIF_ISP_WDR_BASE + 0x0000002C)
1468 #define CIF_ISP_WDR_TONECURVE_YM_7 (CIF_ISP_WDR_BASE + 0x00000030)
1469 #define CIF_ISP_WDR_TONECURVE_YM_8 (CIF_ISP_WDR_BASE + 0x00000034)
1470 #define CIF_ISP_WDR_TONECURVE_YM_9 (CIF_ISP_WDR_BASE + 0x00000038)
1471 #define CIF_ISP_WDR_TONECURVE_YM_10 (CIF_ISP_WDR_BASE + 0x0000003C)
1472 #define CIF_ISP_WDR_TONECURVE_YM_11 (CIF_ISP_WDR_BASE + 0x00000040)
1473 #define CIF_ISP_WDR_TONECURVE_YM_12 (CIF_ISP_WDR_BASE + 0x00000044)
1474 #define CIF_ISP_WDR_TONECURVE_YM_13 (CIF_ISP_WDR_BASE + 0x00000048)
1475 #define CIF_ISP_WDR_TONECURVE_YM_14 (CIF_ISP_WDR_BASE + 0x0000004C)
1476 #define CIF_ISP_WDR_TONECURVE_YM_15 (CIF_ISP_WDR_BASE + 0x00000050)
1477 #define CIF_ISP_WDR_TONECURVE_YM_16 (CIF_ISP_WDR_BASE + 0x00000054)
1478 #define CIF_ISP_WDR_TONECURVE_YM_17 (CIF_ISP_WDR_BASE + 0x00000058)
1479 #define CIF_ISP_WDR_TONECURVE_YM_18 (CIF_ISP_WDR_BASE + 0x0000005C)
1480 #define CIF_ISP_WDR_TONECURVE_YM_19 (CIF_ISP_WDR_BASE + 0x00000060)
1481 #define CIF_ISP_WDR_TONECURVE_YM_20 (CIF_ISP_WDR_BASE + 0x00000064)
1482 #define CIF_ISP_WDR_TONECURVE_YM_21 (CIF_ISP_WDR_BASE + 0x00000068)
1483 #define CIF_ISP_WDR_TONECURVE_YM_22 (CIF_ISP_WDR_BASE + 0x0000006C)
1484 #define CIF_ISP_WDR_TONECURVE_YM_23 (CIF_ISP_WDR_BASE + 0x00000070)
1485 #define CIF_ISP_WDR_TONECURVE_YM_24 (CIF_ISP_WDR_BASE + 0x00000074)
1486 #define CIF_ISP_WDR_TONECURVE_YM_25 (CIF_ISP_WDR_BASE + 0x00000078)
1487 #define CIF_ISP_WDR_TONECURVE_YM_26 (CIF_ISP_WDR_BASE + 0x0000007C)
1488 #define CIF_ISP_WDR_TONECURVE_YM_27 (CIF_ISP_WDR_BASE + 0x00000080)
1489 #define CIF_ISP_WDR_TONECURVE_YM_28 (CIF_ISP_WDR_BASE + 0x00000084)
1490 #define CIF_ISP_WDR_TONECURVE_YM_29 (CIF_ISP_WDR_BASE + 0x00000088)
1491 #define CIF_ISP_WDR_TONECURVE_YM_30 (CIF_ISP_WDR_BASE + 0x0000008C)
1492 #define CIF_ISP_WDR_TONECURVE_YM_31 (CIF_ISP_WDR_BASE + 0x00000090)
1493 #define CIF_ISP_WDR_TONECURVE_YM_32 (CIF_ISP_WDR_BASE + 0x00000094)
1494 #define CIF_ISP_WDR_OFFSET (CIF_ISP_WDR_BASE + 0x00000098)
1495 #define CIF_ISP_WDR_DELTAMIN (CIF_ISP_WDR_BASE + 0x0000009C)
1496 #define CIF_ISP_WDR_TONECURVE_1_SHD (CIF_ISP_WDR_BASE + 0x000000A0)
1497 #define CIF_ISP_WDR_TONECURVE_2_SHD (CIF_ISP_WDR_BASE + 0x000000A4)
1498 #define CIF_ISP_WDR_TONECURVE_3_SHD (CIF_ISP_WDR_BASE + 0x000000A8)
1499 #define CIF_ISP_WDR_TONECURVE_4_SHD (CIF_ISP_WDR_BASE + 0x000000AC)
1500 #define CIF_ISP_WDR_TONECURVE_YM_0_SHD (CIF_ISP_WDR_BASE + 0x000000B0)
1501 #define CIF_ISP_WDR_TONECURVE_YM_1_SHD (CIF_ISP_WDR_BASE + 0x000000B4)
1502 #define CIF_ISP_WDR_TONECURVE_YM_2_SHD (CIF_ISP_WDR_BASE + 0x000000B8)
1503 #define CIF_ISP_WDR_TONECURVE_YM_3_SHD (CIF_ISP_WDR_BASE + 0x000000BC)
1504 #define CIF_ISP_WDR_TONECURVE_YM_4_SHD (CIF_ISP_WDR_BASE + 0x000000C0)
1505 #define CIF_ISP_WDR_TONECURVE_YM_5_SHD (CIF_ISP_WDR_BASE + 0x000000C4)
1506 #define CIF_ISP_WDR_TONECURVE_YM_6_SHD (CIF_ISP_WDR_BASE + 0x000000C8)
1507 #define CIF_ISP_WDR_TONECURVE_YM_7_SHD (CIF_ISP_WDR_BASE + 0x000000CC)
1508 #define CIF_ISP_WDR_TONECURVE_YM_8_SHD (CIF_ISP_WDR_BASE + 0x000000D0)
1509 #define CIF_ISP_WDR_TONECURVE_YM_9_SHD (CIF_ISP_WDR_BASE + 0x000000D4)
1510 #define CIF_ISP_WDR_TONECURVE_YM_10_SHD (CIF_ISP_WDR_BASE + 0x000000D8)
1511 #define CIF_ISP_WDR_TONECURVE_YM_11_SHD (CIF_ISP_WDR_BASE + 0x000000DC)
1512 #define CIF_ISP_WDR_TONECURVE_YM_12_SHD (CIF_ISP_WDR_BASE + 0x000000E0)
1513 #define CIF_ISP_WDR_TONECURVE_YM_13_SHD (CIF_ISP_WDR_BASE + 0x000000E4)
1514 #define CIF_ISP_WDR_TONECURVE_YM_14_SHD (CIF_ISP_WDR_BASE + 0x000000E8)
1515 #define CIF_ISP_WDR_TONECURVE_YM_15_SHD (CIF_ISP_WDR_BASE + 0x000000EC)
1516 #define CIF_ISP_WDR_TONECURVE_YM_16_SHD (CIF_ISP_WDR_BASE + 0x000000F0)
1517 #define CIF_ISP_WDR_TONECURVE_YM_17_SHD (CIF_ISP_WDR_BASE + 0x000000F4)
1518 #define CIF_ISP_WDR_TONECURVE_YM_18_SHD (CIF_ISP_WDR_BASE + 0x000000F8)
1519 #define CIF_ISP_WDR_TONECURVE_YM_19_SHD (CIF_ISP_WDR_BASE + 0x000000FC)
1520 #define CIF_ISP_WDR_TONECURVE_YM_20_SHD (CIF_ISP_WDR_BASE + 0x00000100)
1521 #define CIF_ISP_WDR_TONECURVE_YM_21_SHD (CIF_ISP_WDR_BASE + 0x00000104)
1522 #define CIF_ISP_WDR_TONECURVE_YM_22_SHD (CIF_ISP_WDR_BASE + 0x00000108)
1523 #define CIF_ISP_WDR_TONECURVE_YM_23_SHD (CIF_ISP_WDR_BASE + 0x0000010C)
1524 #define CIF_ISP_WDR_TONECURVE_YM_24_SHD (CIF_ISP_WDR_BASE + 0x00000110)
1525 #define CIF_ISP_WDR_TONECURVE_YM_25_SHD (CIF_ISP_WDR_BASE + 0x00000114)
1526 #define CIF_ISP_WDR_TONECURVE_YM_26_SHD (CIF_ISP_WDR_BASE + 0x00000118)
1527 #define CIF_ISP_WDR_TONECURVE_YM_27_SHD (CIF_ISP_WDR_BASE + 0x0000011C)
1528 #define CIF_ISP_WDR_TONECURVE_YM_28_SHD (CIF_ISP_WDR_BASE + 0x00000120)
1529 #define CIF_ISP_WDR_TONECURVE_YM_29_SHD (CIF_ISP_WDR_BASE + 0x00000124)
1530 #define CIF_ISP_WDR_TONECURVE_YM_30_SHD (CIF_ISP_WDR_BASE + 0x00000128)
1531 #define CIF_ISP_WDR_TONECURVE_YM_31_SHD (CIF_ISP_WDR_BASE + 0x0000012C)
1532 #define CIF_ISP_WDR_TONECURVE_YM_32_SHD (CIF_ISP_WDR_BASE + 0x00000130)
1533
1534 #define CIF_ISP_RKWDR_CTRL0 (CIF_ISP_WDR_BASE + 0x00000150)
1535 #define CIF_ISP_RKWDR_CTRL1 (CIF_ISP_WDR_BASE + 0x00000154)
1536 #define CIF_ISP_RKWDR_BLKOFF0 (CIF_ISP_WDR_BASE + 0x00000158)
1537 #define CIF_ISP_RKWDR_AVGCLIP (CIF_ISP_WDR_BASE + 0x0000015c)
1538 #define CIF_ISP_RKWDR_COE_0 (CIF_ISP_WDR_BASE + 0x00000160)
1539 #define CIF_ISP_RKWDR_COE_1 (CIF_ISP_WDR_BASE + 0x00000164)
1540 #define CIF_ISP_RKWDR_COE_2 (CIF_ISP_WDR_BASE + 0x00000168)
1541 #define CIF_ISP_RKWDR_COE_OFF (CIF_ISP_WDR_BASE + 0x0000016c)
1542 #define CIF_ISP_RKWDR_OVERL (CIF_ISP_WDR_BASE + 0x00000170)
1543 #define CIF_ISP_RKWDR_BLKOFF1 (CIF_ISP_WDR_BASE + 0x00000174)
1544 #define CIF_ISP_RKWDR_BLKMEAN8_ROW0_0TO3 (CIF_ISP_WDR_BASE + 0x00000180)
1545 #define CIF_ISP_RKWDR_BLKMEAN8_ROW0_4TO7 (CIF_ISP_WDR_BASE + 0x00000184)
1546 #define CIF_ISP_RKWDR_BLKMEAN8_ROW1_0TO3 (CIF_ISP_WDR_BASE + 0x00000188)
1547 #define CIF_ISP_RKWDR_BLKMEAN8_ROW1_4TO7 (CIF_ISP_WDR_BASE + 0x0000018c)
1548 #define CIF_ISP_RKWDR_BLKMEAN8_ROW2_0TO3 (CIF_ISP_WDR_BASE + 0x00000190)
1549 #define CIF_ISP_RKWDR_BLKMEAN8_ROW2_4TO7 (CIF_ISP_WDR_BASE + 0x00000194)
1550 #define CIF_ISP_RKWDR_BLKMEAN8_ROW3_0TO3 (CIF_ISP_WDR_BASE + 0x00000198)
1551 #define CIF_ISP_RKWDR_BLKMEAN8_ROW3_4TO7 (CIF_ISP_WDR_BASE + 0x0000019c)
1552 #define CIF_ISP_RKWDR_BLKMEAN8_ROW4_0TO3 (CIF_ISP_WDR_BASE + 0x000001a0)
1553 #define CIF_ISP_RKWDR_BLKMEAN8_ROW4_4TO7 (CIF_ISP_WDR_BASE + 0x000001a4)
1554 #define CIF_ISP_RKWDR_BLKMEAN8_ROW5_0TO3 (CIF_ISP_WDR_BASE + 0x000001a8)
1555 #define CIF_ISP_RKWDR_BLKMEAN8_ROW5_4TO7 (CIF_ISP_WDR_BASE + 0x000001ac)
1556 #define CIF_ISP_RKWDR_BLKMEAN8_ROW6_0TO3 (CIF_ISP_WDR_BASE + 0x000001b0)
1557 #define CIF_ISP_RKWDR_BLKMEAN8_ROW6_4TO7 (CIF_ISP_WDR_BASE + 0x000001b4)
1558 #define CIF_ISP_RKWDR_BLKMEAN8_ROW7_0TO3 (CIF_ISP_WDR_BASE + 0x000001b8)
1559 #define CIF_ISP_RKWDR_BLKMEAN8_ROW7_4TO7 (CIF_ISP_WDR_BASE + 0x000001bc)
1560 #define CIF_ISP_RKWDR_BLKMEAN8_ROW8_0TO3 (CIF_ISP_WDR_BASE + 0x000001c0)
1561 #define CIF_ISP_RKWDR_BLKMEAN8_ROW8_4TO7 (CIF_ISP_WDR_BASE + 0x000001c4)
1562 #define CIF_ISP_RKWDR_BLKMEAN8_ROW9_0TO3 (CIF_ISP_WDR_BASE + 0x000001c8)
1563 #define CIF_ISP_RKWDR_BLKMEAN8_ROW9_4TO7 (CIF_ISP_WDR_BASE + 0x000001cc)
1564
1565 #define CIF_ISP_HIST_BASE_V12 0x00002C00
1566 #define CIF_ISP_HIST_CTRL_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000000)
1567 #define CIF_ISP_HIST_SIZE_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000004)
1568 #define CIF_ISP_HIST_OFFS_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000008)
1569 #define CIF_ISP_HIST_DBG1_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000000C)
1570 #define CIF_ISP_HIST_DBG2_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000001C)
1571 #define CIF_ISP_HIST_DBG3_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000002C)
1572 #define CIF_ISP_HIST_WEIGHT_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000003C)
1573 #define CIF_ISP_HIST_BIN_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000120)
1574
1575 #define CIF_ISP_VSM_BASE 0x00002F00
1576 #define CIF_ISP_VSM_MODE (CIF_ISP_VSM_BASE + 0x00000000)
1577 #define CIF_ISP_VSM_H_OFFS (CIF_ISP_VSM_BASE + 0x00000004)
1578 #define CIF_ISP_VSM_V_OFFS (CIF_ISP_VSM_BASE + 0x00000008)
1579 #define CIF_ISP_VSM_H_SIZE (CIF_ISP_VSM_BASE + 0x0000000C)
1580 #define CIF_ISP_VSM_V_SIZE (CIF_ISP_VSM_BASE + 0x00000010)
1581 #define CIF_ISP_VSM_H_SEGMENTS (CIF_ISP_VSM_BASE + 0x00000014)
1582 #define CIF_ISP_VSM_V_SEGMENTS (CIF_ISP_VSM_BASE + 0x00000018)
1583 #define CIF_ISP_VSM_DELTA_H (CIF_ISP_VSM_BASE + 0x0000001C)
1584 #define CIF_ISP_VSM_DELTA_V (CIF_ISP_VSM_BASE + 0x00000020)
1585
1586 #define CIF_ISP_CSI0_BASE 0x00007000
1587 #define CIF_ISP_CSI0_CTRL0 (CIF_ISP_CSI0_BASE + 0x00000000)
1588 #define CIF_ISP_CSI0_CTRL1 (CIF_ISP_CSI0_BASE + 0x00000004)
1589 #define CIF_ISP_CSI0_CTRL2 (CIF_ISP_CSI0_BASE + 0x00000008)
1590 #define CIF_ISP_CSI0_CSI2_RESETN (CIF_ISP_CSI0_BASE + 0x00000010)
1591 #define CIF_ISP_CSI0_PHY_STATE_RO (CIF_ISP_CSI0_BASE + 0x00000014)
1592 #define CIF_ISP_CSI0_DATA_IDS_1 (CIF_ISP_CSI0_BASE + 0x00000018)
1593 #define CIF_ISP_CSI0_DATA_IDS_2 (CIF_ISP_CSI0_BASE + 0x0000001c)
1594 #define CIF_ISP_CSI0_ERR1 (CIF_ISP_CSI0_BASE + 0x00000020)
1595 #define CIF_ISP_CSI0_ERR2 (CIF_ISP_CSI0_BASE + 0x00000024)
1596 #define CIF_ISP_CSI0_ERR3 (CIF_ISP_CSI0_BASE + 0x00000028)
1597 #define CIF_ISP_CSI0_MASK1 (CIF_ISP_CSI0_BASE + 0x0000002c)
1598 #define CIF_ISP_CSI0_MASK2 (CIF_ISP_CSI0_BASE + 0x00000030)
1599 #define CIF_ISP_CSI0_MASK3 (CIF_ISP_CSI0_BASE + 0x00000034)
1600 #define CIF_ISP_CSI0_SET_HEARDER (CIF_ISP_CSI0_BASE + 0x00000038)
1601 #define CIF_ISP_CSI0_CUR_HEADER_RO (CIF_ISP_CSI0_BASE + 0x0000003c)
1602 #define CIF_ISP_CSI0_DMATX0_CTRL (CIF_ISP_CSI0_BASE + 0x00000040)
1603 #define CIF_ISP_CSI0_DMATX0_LINECNT_RO (CIF_ISP_CSI0_BASE + 0x00000044)
1604 #define CIF_ISP_CSI0_DMATX0_PIC_SIZE (CIF_ISP_CSI0_BASE + 0x00000048)
1605 #define CIF_ISP_CSI0_DMATX0_PIC_OFF (CIF_ISP_CSI0_BASE + 0x0000004c)
1606 #define CIF_ISP_CSI0_FRAME_NUM_RO (CIF_ISP_CSI0_BASE + 0x00000070)
1607 #define CIF_ISP_CSI0_ISP_LINECNT_RO (CIF_ISP_CSI0_BASE + 0x00000074)
1608 #define CIF_ISP_CSI0_TX_IBUF_STATUS_RO (CIF_ISP_CSI0_BASE + 0x00000078)
1609 #define CIF_ISP_CSI0_VERSION (CIF_ISP_CSI0_BASE + 0x0000007c)
1610
1611 void disable_dcrop(struct rkisp1_stream *stream, bool async);
1612 void config_dcrop(struct rkisp1_stream *stream, struct v4l2_rect *rect,
1613 bool async);
1614
1615 void dump_rsz_regs(struct rkisp1_stream *stream);
1616 void disable_rsz(struct rkisp1_stream *stream, bool async);
1617 void config_rsz(struct rkisp1_stream *stream, struct v4l2_rect *in_y,
1618 struct v4l2_rect *in_c, struct v4l2_rect *out_y,
1619 struct v4l2_rect *out_c, bool async);
1620
1621 void config_mi_ctrl(struct rkisp1_stream *stream, u32 burst);
1622
1623 void mp_clr_frame_end_int(void __iomem *base);
1624 void sp_clr_frame_end_int(void __iomem *base);
1625
1626 bool mp_is_frame_end_int_masked(void __iomem *base);
1627 bool sp_is_frame_end_int_masked(void __iomem *base);
1628 bool mp_is_stream_stopped(void __iomem *base);
1629 bool sp_is_stream_stopped(void __iomem *base);
1630
mi_set_y_size(struct rkisp1_stream * stream,int val)1631 static inline void mi_set_y_size(struct rkisp1_stream *stream, int val)
1632 {
1633 void __iomem *base = stream->ispdev->base_addr;
1634
1635 writel(val, base + stream->config->mi.y_size_init);
1636 }
1637
mi_set_cb_size(struct rkisp1_stream * stream,int val)1638 static inline void mi_set_cb_size(struct rkisp1_stream *stream, int val)
1639 {
1640 void __iomem *base = stream->ispdev->base_addr;
1641
1642 writel(val, base + stream->config->mi.cb_size_init);
1643 }
1644
mi_set_cr_size(struct rkisp1_stream * stream,int val)1645 static inline void mi_set_cr_size(struct rkisp1_stream *stream, int val)
1646 {
1647 void __iomem *base = stream->ispdev->base_addr;
1648
1649 writel(val, base + stream->config->mi.cr_size_init);
1650 }
1651
mi_set_y_addr(struct rkisp1_stream * stream,int val)1652 static inline void mi_set_y_addr(struct rkisp1_stream *stream, int val)
1653 {
1654 void __iomem *base = stream->ispdev->base_addr;
1655
1656 writel(val, base + stream->config->mi.y_base_ad_init);
1657 }
1658
mi_set_cb_addr(struct rkisp1_stream * stream,int val)1659 static inline void mi_set_cb_addr(struct rkisp1_stream *stream, int val)
1660 {
1661 void __iomem *base = stream->ispdev->base_addr;
1662
1663 writel(val, base + stream->config->mi.cb_base_ad_init);
1664 }
1665
mi_set_cr_addr(struct rkisp1_stream * stream,int val)1666 static inline void mi_set_cr_addr(struct rkisp1_stream *stream, int val)
1667 {
1668 void __iomem *base = stream->ispdev->base_addr;
1669
1670 writel(val, base + stream->config->mi.cr_base_ad_init);
1671 }
1672
mi_set_y_offset(struct rkisp1_stream * stream,int val)1673 static inline void mi_set_y_offset(struct rkisp1_stream *stream, int val)
1674 {
1675 void __iomem *base = stream->ispdev->base_addr;
1676
1677 writel(val, base + stream->config->mi.y_offs_cnt_init);
1678 }
1679
mi_set_cb_offset(struct rkisp1_stream * stream,int val)1680 static inline void mi_set_cb_offset(struct rkisp1_stream *stream, int val)
1681 {
1682 void __iomem *base = stream->ispdev->base_addr;
1683
1684 writel(val, base + stream->config->mi.cb_offs_cnt_init);
1685 }
1686
mi_set_cr_offset(struct rkisp1_stream * stream,int val)1687 static inline void mi_set_cr_offset(struct rkisp1_stream *stream, int val)
1688 {
1689 void __iomem *base = stream->ispdev->base_addr;
1690
1691 writel(val, base + stream->config->mi.cr_offs_cnt_init);
1692 }
1693
mi_frame_end_int_enable(struct rkisp1_stream * stream)1694 static inline void mi_frame_end_int_enable(struct rkisp1_stream *stream)
1695 {
1696 void __iomem *base = stream->ispdev->base_addr;
1697 void __iomem *addr = base + CIF_MI_IMSC;
1698
1699 writel(CIF_MI_FRAME(stream) | readl(addr), addr);
1700 }
1701
mi_frame_end_int_disable(struct rkisp1_stream * stream)1702 static inline void mi_frame_end_int_disable(struct rkisp1_stream *stream)
1703 {
1704 void __iomem *base = stream->ispdev->base_addr;
1705 void __iomem *addr = base + CIF_MI_IMSC;
1706
1707 writel(~CIF_MI_FRAME(stream) & readl(addr), addr);
1708 }
1709
mi_frame_end_int_clear(struct rkisp1_stream * stream)1710 static inline void mi_frame_end_int_clear(struct rkisp1_stream *stream)
1711 {
1712 void __iomem *base = stream->ispdev->base_addr;
1713 void __iomem *addr = base + CIF_MI_ICR;
1714
1715 writel(CIF_MI_FRAME(stream), addr);
1716 }
1717
mp_set_chain_mode(void __iomem * base)1718 static inline void mp_set_chain_mode(void __iomem *base)
1719 {
1720 u32 dpcl = readl(base + CIF_VI_DPCL);
1721
1722 dpcl |= CIF_VI_DPCL_CHAN_MODE_MP;
1723 writel(dpcl, base + CIF_VI_DPCL);
1724 }
1725
sp_set_chain_mode(void __iomem * base)1726 static inline void sp_set_chain_mode(void __iomem *base)
1727 {
1728 u32 dpcl = readl(base + CIF_VI_DPCL);
1729
1730 dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
1731 writel(dpcl, base + CIF_VI_DPCL);
1732 }
1733
mp_set_data_path(void __iomem * base)1734 static inline void mp_set_data_path(void __iomem *base)
1735 {
1736 u32 dpcl = readl(base + CIF_VI_DPCL);
1737
1738 dpcl = dpcl | CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
1739 writel(dpcl, base + CIF_VI_DPCL);
1740 }
1741
sp_set_data_path(void __iomem * base)1742 static inline void sp_set_data_path(void __iomem *base)
1743 {
1744 u32 dpcl = readl(base + CIF_VI_DPCL);
1745
1746 dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
1747 writel(dpcl, base + CIF_VI_DPCL);
1748 }
1749
mp_set_uv_swap(void __iomem * base)1750 static inline void mp_set_uv_swap(void __iomem *base)
1751 {
1752 void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
1753 u32 reg = readl(addr) & ~BIT(0);
1754
1755 writel(reg | CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP, addr);
1756 }
1757
sp_set_uv_swap(void __iomem * base)1758 static inline void sp_set_uv_swap(void __iomem *base)
1759 {
1760 void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
1761 u32 reg = readl(addr) & ~BIT(1);
1762
1763 writel(reg | CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP, addr);
1764 }
1765
sp_set_y_width(void __iomem * base,u32 val)1766 static inline void sp_set_y_width(void __iomem *base, u32 val)
1767 {
1768 writel(val, base + CIF_MI_SP_Y_PIC_WIDTH);
1769 }
1770
sp_set_y_height(void __iomem * base,u32 val)1771 static inline void sp_set_y_height(void __iomem *base, u32 val)
1772 {
1773 writel(val, base + CIF_MI_SP_Y_PIC_HEIGHT);
1774 }
1775
sp_set_y_line_length(void __iomem * base,u32 val)1776 static inline void sp_set_y_line_length(void __iomem *base, u32 val)
1777 {
1778 writel(val, base + CIF_MI_SP_Y_LLENGTH);
1779 }
1780
mp_mi_ctrl_set_format(void __iomem * base,u32 val)1781 static inline void mp_mi_ctrl_set_format(void __iomem *base, u32 val)
1782 {
1783 void __iomem *addr = base + CIF_MI_CTRL;
1784 u32 reg = readl(addr) & ~MI_CTRL_MP_FMT_MASK;
1785
1786 writel(reg | val, addr);
1787 }
1788
sp_mi_ctrl_set_format(void __iomem * base,u32 val)1789 static inline void sp_mi_ctrl_set_format(void __iomem *base, u32 val)
1790 {
1791 void __iomem *addr = base + CIF_MI_CTRL;
1792 u32 reg = readl(addr) & ~MI_CTRL_SP_FMT_MASK;
1793
1794 writel(reg | val, addr);
1795 }
1796
mi_ctrl_mpyuv_enable(void __iomem * base)1797 static inline void mi_ctrl_mpyuv_enable(void __iomem *base)
1798 {
1799 void __iomem *addr = base + CIF_MI_CTRL;
1800
1801 writel(CIF_MI_CTRL_MP_ENABLE | readl(addr), addr);
1802 }
1803
mi_ctrl_mpyuv_disable(void __iomem * base)1804 static inline void mi_ctrl_mpyuv_disable(void __iomem *base)
1805 {
1806 void __iomem *addr = base + CIF_MI_CTRL;
1807
1808 writel(~CIF_MI_CTRL_MP_ENABLE & readl(addr), addr);
1809 }
1810
mi_ctrl_mp_disable(void __iomem * base)1811 static inline void mi_ctrl_mp_disable(void __iomem *base)
1812 {
1813 void __iomem *addr = base + CIF_MI_CTRL;
1814
1815 writel(~(CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE) & readl(addr),
1816 addr);
1817 }
1818
mi_ctrl_spyuv_enable(void __iomem * base)1819 static inline void mi_ctrl_spyuv_enable(void __iomem *base)
1820 {
1821 void __iomem *addr = base + CIF_MI_CTRL;
1822
1823 writel(CIF_MI_CTRL_SP_ENABLE | readl(addr), addr);
1824 }
1825
mi_ctrl_spyuv_disable(void __iomem * base)1826 static inline void mi_ctrl_spyuv_disable(void __iomem *base)
1827 {
1828 void __iomem *addr = base + CIF_MI_CTRL;
1829
1830 writel(~CIF_MI_CTRL_SP_ENABLE & readl(addr), addr);
1831 }
1832
mi_ctrl_sp_disable(void __iomem * base)1833 static inline void mi_ctrl_sp_disable(void __iomem *base)
1834 {
1835 mi_ctrl_spyuv_disable(base);
1836 }
1837
mi_ctrl_mpraw_enable(void __iomem * base)1838 static inline void mi_ctrl_mpraw_enable(void __iomem *base)
1839 {
1840 void __iomem *addr = base + CIF_MI_CTRL;
1841
1842 writel(CIF_MI_CTRL_RAW_ENABLE | readl(addr), addr);
1843 }
1844
mi_ctrl_mpraw_disable(void __iomem * base)1845 static inline void mi_ctrl_mpraw_disable(void __iomem *base)
1846 {
1847 void __iomem *addr = base + CIF_MI_CTRL;
1848
1849 writel(~CIF_MI_CTRL_RAW_ENABLE & readl(addr), addr);
1850 }
1851
mp_mi_ctrl_autoupdate_en(void __iomem * base)1852 static inline void mp_mi_ctrl_autoupdate_en(void __iomem *base)
1853 {
1854 void __iomem *addr = base + CIF_MI_CTRL;
1855
1856 writel(readl(addr) | CIF_MI_MP_AUTOUPDATE_ENABLE, addr);
1857 }
1858
sp_mi_ctrl_autoupdate_en(void __iomem * base)1859 static inline void sp_mi_ctrl_autoupdate_en(void __iomem *base)
1860 {
1861 void __iomem *addr = base + CIF_MI_CTRL;
1862
1863 writel(readl(addr) | CIF_MI_SP_AUTOUPDATE_ENABLE, addr);
1864 }
1865
force_cfg_update(void __iomem * base)1866 static inline void force_cfg_update(void __iomem *base)
1867 {
1868 writel(CIF_MI_INIT_SOFT_UPD, base + CIF_MI_INIT);
1869 }
1870
dmatx0_ctrl(void __iomem * base,u32 val)1871 static inline void dmatx0_ctrl(void __iomem *base, u32 val)
1872 {
1873 writel(val, base + CIF_ISP_CSI0_DMATX0_CTRL);
1874 }
1875
dmatx0_enable(void __iomem * base)1876 static inline void dmatx0_enable(void __iomem *base)
1877 {
1878 void __iomem *addr = base + CIF_ISP_CSI0_DMATX0_CTRL;
1879
1880 writel(CIF_ISP_CSI0_DMATX0_EN | readl(addr), addr);
1881 }
1882
dmatx0_disable(void __iomem * base)1883 static inline void dmatx0_disable(void __iomem *base)
1884 {
1885 void __iomem *addr = base + CIF_ISP_CSI0_DMATX0_CTRL;
1886
1887 writel(~CIF_ISP_CSI0_DMATX0_EN & readl(addr), addr);
1888 }
1889
dmatx0_set_pic_size(void __iomem * base,u32 width,u32 height)1890 static inline void dmatx0_set_pic_size(void __iomem *base,
1891 u32 width, u32 height)
1892 {
1893 writel(height << 16 | width,
1894 base + CIF_ISP_CSI0_DMATX0_PIC_SIZE);
1895 }
1896
dmatx0_set_pic_off(void __iomem * base,u32 val)1897 static inline void dmatx0_set_pic_off(void __iomem *base, u32 val)
1898 {
1899 writel(val, base + CIF_ISP_CSI0_DMATX0_PIC_OFF);
1900 }
1901
mi_raw0_set_size(void __iomem * base,u32 val)1902 static inline void mi_raw0_set_size(void __iomem *base, u32 val)
1903 {
1904 writel(val, base + CIF_MI_RAW0_SIZE_INIT);
1905 }
1906
mi_raw0_set_offs(void __iomem * base,u32 val)1907 static inline void mi_raw0_set_offs(void __iomem *base, u32 val)
1908 {
1909 writel(val, base + CIF_MI_RAW0_OFFS_CNT_INIT);
1910 }
1911
mi_raw0_set_length(void __iomem * base,u32 val)1912 static inline void mi_raw0_set_length(void __iomem *base, u32 val)
1913 {
1914 writel(val, base + CIF_MI_RAW0_LENGTH);
1915 }
1916
mi_raw0_set_irq_offs(void __iomem * base,u32 val)1917 static inline void mi_raw0_set_irq_offs(void __iomem *base, u32 val)
1918 {
1919 writel(val, base + CIF_MI_RAW0_IRQ_OFFS_INIT);
1920 }
1921
mi_raw0_set_addr(void __iomem * base,u32 val)1922 static inline void mi_raw0_set_addr(void __iomem *base, u32 val)
1923 {
1924 writel(val, base + CIF_MI_RAW0_BASE_AD_INIT);
1925 }
1926
mi_mipi_raw0_enable(void __iomem * base)1927 static inline void mi_mipi_raw0_enable(void __iomem *base)
1928 {
1929 void __iomem *addr = base + CIF_MI_CTRL2;
1930
1931 writel(CIF_MI_CTRL2_MIPI_RAW0_ENABLE | readl(addr), addr);
1932 }
1933
mi_mipi_raw0_disable(void __iomem * base)1934 static inline void mi_mipi_raw0_disable(void __iomem *base)
1935 {
1936 void __iomem *addr = base + CIF_MI_CTRL2;
1937
1938 writel(~CIF_MI_CTRL2_MIPI_RAW0_ENABLE & readl(addr), addr);
1939 }
1940
mi_ctrl2(void __iomem * base,u32 val)1941 static inline void mi_ctrl2(void __iomem *base, u32 val)
1942 {
1943 writel(val, base + CIF_MI_CTRL2);
1944 }
1945
mi_dmarx_ready_enable(struct rkisp1_stream * stream)1946 static inline void mi_dmarx_ready_enable(struct rkisp1_stream *stream)
1947 {
1948 void __iomem *base = stream->ispdev->base_addr;
1949 void __iomem *addr = base + CIF_MI_IMSC;
1950
1951 writel(CIF_MI_DMA_READY | readl(addr), addr);
1952 }
1953
mi_dmarx_ready_disable(struct rkisp1_stream * stream)1954 static inline void mi_dmarx_ready_disable(struct rkisp1_stream *stream)
1955 {
1956 void __iomem *base = stream->ispdev->base_addr;
1957 void __iomem *addr = base + CIF_MI_IMSC;
1958
1959 writel(~CIF_MI_DMA_READY & readl(addr), addr);
1960 }
1961
dmarx_set_uv_swap(void __iomem * base)1962 static inline void dmarx_set_uv_swap(void __iomem *base)
1963 {
1964 void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
1965 u32 reg = readl(addr) & ~BIT(2);
1966
1967 writel(reg | CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP, addr);
1968 }
1969
dmarx_set_y_width(void __iomem * base,u32 val)1970 static inline void dmarx_set_y_width(void __iomem *base, u32 val)
1971 {
1972 writel(val, base + CIF_MI_DMA_Y_PIC_WIDTH);
1973 }
1974
dmarx_set_y_line_length(void __iomem * base,u32 val)1975 static inline void dmarx_set_y_line_length(void __iomem *base, u32 val)
1976 {
1977 writel(val, base + CIF_MI_DMA_Y_LLENGTH);
1978 }
1979
dmarx_ctrl(void __iomem * base,u32 val)1980 static inline void dmarx_ctrl(void __iomem *base, u32 val)
1981 {
1982 void __iomem *addr = base + CIF_MI_DMA_CTRL;
1983
1984 writel(val | readl(addr), addr);
1985 }
1986
mi_dmarx_start(void __iomem * base)1987 static inline void mi_dmarx_start(void __iomem *base)
1988 {
1989 void __iomem *addr = base + CIF_MI_DMA_START;
1990
1991 writel(CIF_MI_DMA_START_ENABLE, addr);
1992 }
1993
1994 #endif /* _RKISP1_REGS_H */
1995