1 /*
2 * Rockchip isp1 driver
3 *
4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef _RKISP_REGS_H
36 #define _RKISP_REGS_H
37 #include "dev.h"
38 #include "regs_v2x.h"
39 #include "regs_v3x.h"
40
41 #define CIF_ISP_PACK_4BYTE(a, b, c, d) \
42 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
43 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
44
45 #define CIF_ISP_PACK_2SHORT(a, b) \
46 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
47
48 /* GRF */
49 #define GRF_VI_CON0 0x430
50 #define ISP_CIF_DATA_WIDTH_MASK 0x60006000
51 #define ISP_CIF_DATA_WIDTH_8B (0 << 13 | 3 << 29)
52 #define ISP_CIF_DATA_WIDTH_10B (BIT(13) | 3 << 29)
53 #define ISP_CIF_DATA_WIDTH_12B (2 << 13 | 3 << 29)
54
55 /* ISP_CTRL */
56 #define CIF_ISP_CTRL_ISP_ENABLE BIT(0)
57 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT (0 << 1)
58 #define CIF_ISP_CTRL_ISP_MODE_ITU656 (1 << 1)
59 #define CIF_ISP_CTRL_ISP_MODE_ITU601 (2 << 1)
60 #define CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601 (3 << 1)
61 #define CIF_ISP_CTRL_ISP_MODE_DATA_MODE (4 << 1)
62 #define CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656 (5 << 1)
63 #define CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656 (6 << 1)
64 #define CIF_ISP_CTRL_ISP_INFORM_ENABLE BIT(4)
65 #define CIF_ISP_CTRL_ISP_GAMMA_IN_ENA BIT(6)
66 #define CIF_ISP_CTRL_ISP_AWB_ENA BIT(7)
67 #define CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT BIT(8)
68 #define CIF_ISP_CTRL_ISP_CFG_UPD BIT(9)
69 #define CIF_ISP_CTRL_ISP_GEN_CFG_UPD BIT(10)
70 #define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA BIT(11)
71 #define CIF_ISP_CTRL_ISP_FLASH_MODE_ENA BIT(12)
72 #define CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA BIT(13)
73 #define CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA BIT(14)
74
75 /* ISP_ACQ_PROP */
76 #define CIF_ISP_ACQ_PROP_POS_EDGE BIT(0)
77 #define CIF_ISP_ACQ_PROP_HSYNC_LOW BIT(1)
78 #define CIF_ISP_ACQ_PROP_VSYNC_LOW BIT(2)
79 #define CIF_ISP_ACQ_PROP_BAYER_PAT_RGGB (0 << 3)
80 #define CIF_ISP_ACQ_PROP_BAYER_PAT_GRBG (1 << 3)
81 #define CIF_ISP_ACQ_PROP_BAYER_PAT_GBRG (2 << 3)
82 #define CIF_ISP_ACQ_PROP_BAYER_PAT_BGGR (3 << 3)
83 #define CIF_ISP_ACQ_PROP_BAYER_PAT(pat) ((pat) << 3)
84 #define CIF_ISP_ACQ_PROP_YCBYCR (0 << 7)
85 #define CIF_ISP_ACQ_PROP_YCRYCB (1 << 7)
86 #define CIF_ISP_ACQ_PROP_CBYCRY (2 << 7)
87 #define CIF_ISP_ACQ_PROP_CRYCBY (3 << 7)
88 #define CIF_ISP_ACQ_PROP_FIELD_SEL_ALL (0 << 9)
89 #define CIF_ISP_ACQ_PROP_FIELD_SEL_EVEN (1 << 9)
90 #define CIF_ISP_ACQ_PROP_FIELD_SEL_ODD (2 << 9)
91 #define CIF_ISP_ACQ_PROP_IN_SEL_12B (0 << 12)
92 #define CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO (1 << 12)
93 #define CIF_ISP_ACQ_PROP_IN_SEL_10B_MSB (2 << 12)
94 #define CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO (3 << 12)
95 #define CIF_ISP_ACQ_PROP_IN_SEL_8B_MSB (4 << 12)
96 #define CIF_ISP_ACQ_PROP_DMA_RGB BIT(15)
97 #define CIF_ISP_ACQ_PROP_DMA_YUV BIT(16)
98
99 /* VI_DPCL */
100 #define CIF_VI_DPCL_DMA_JPEG (0 << 0)
101 #define CIF_VI_DPCL_MP_MUX_MRSZ_MI (1 << 0)
102 #define CIF_VI_DPCL_MP_MUX_MRSZ_JPEG (2 << 0)
103 #define CIF_VI_DPCL_CHAN_MODE_MP (1 << 2)
104 #define CIF_VI_DPCL_CHAN_MODE_SP (2 << 2)
105 #define CIF_VI_DPCL_CHAN_MODE_MPSP (3 << 2)
106 #define CIF_VI_DPCL_DMA_SW_SPMUX (0 << 4)
107 #define CIF_VI_DPCL_DMA_SW_SI (1 << 4)
108 #define CIF_VI_DPCL_DMA_SW_IE (2 << 4)
109 #define CIF_VI_DPCL_DMA_SW_JPEG (3 << 4)
110 #define CIF_VI_DPCL_DMA_SW_ISP (4 << 4)
111 #define CIF_VI_DPCL_IF_SEL_PARALLEL (0 << 8)
112 #define CIF_VI_DPCL_IF_SEL_SMIA (1 << 8)
113 #define CIF_VI_DPCL_IF_SEL_MIPI (2 << 8)
114 #define CIF_VI_DPCL_DMA_IE_MUX_DMA BIT(10)
115 #define CIF_VI_DPCL_DMA_SP_MUX_DMA BIT(11)
116
117 /* ISP_IMSC - ISP_MIS - ISP_RIS - ISP_ICR - ISP_ISR */
118 #define CIF_ISP_OFF BIT(0)
119 #define CIF_ISP_FRAME BIT(1)
120 #define CIF_ISP_DATA_LOSS BIT(2)
121 #define CIF_ISP_PIC_SIZE_ERROR BIT(3)
122 #define CIF_ISP_AWB_DONE BIT(4)
123 #define CIF_ISP_FRAME_IN BIT(5)
124 #define CIF_ISP_V_START BIT(6)
125 #define CIF_ISP_H_START BIT(7)
126 #define CIF_ISP_FLASH_ON BIT(8)
127 #define CIF_ISP_FLASH_OFF BIT(9)
128 #define CIF_ISP_SHUTTER_ON BIT(10)
129 #define CIF_ISP_SHUTTER_OFF BIT(11)
130 #define CIF_ISP_AFM_SUM_OF BIT(12)
131 #define CIF_ISP_AFM_LUM_OF BIT(13)
132 #define CIF_ISP_AFM_FIN BIT(14)
133 #define CIF_ISP_HIST_MEASURE_RDY BIT(15)
134 #define CIF_ISP_FLASH_CAP BIT(17)
135 #define CIF_ISP_EXP_END BIT(18)
136 #define CIF_ISP_VSM_END BIT(19)
137
138 /* ISP_ERR */
139 #define CIF_ISP_ERR_INFORM_SIZE BIT(0)
140 #define CIF_ISP_ERR_IS_SIZE BIT(1)
141 #define CIF_ISP_ERR_OUTFORM_SIZE BIT(2)
142
143 /* MI_CTRL */
144 #define CIF_MI_CTRL_MP_ENABLE (1 << 0)
145 #define CIF_MI_CTRL_SP_ENABLE (2 << 0)
146 #define CIF_MI_CTRL_JPEG_ENABLE (4 << 0)
147 #define CIF_MI_CTRL_RAW_ENABLE (8 << 0)
148 #define CIF_MI_CTRL_HFLIP BIT(4)
149 #define CIF_MI_CTRL_VFLIP BIT(5)
150 #define CIF_MI_CTRL_ROT BIT(6)
151 #define CIF_MI_BYTE_SWAP BIT(7)
152 #define CIF_MI_SP_Y_FULL_YUV2RGB BIT(8)
153 #define CIF_MI_SP_CBCR_FULL_YUV2RGB BIT(9)
154 #define CIF_MI_SP_422NONCOSITEED BIT(10)
155 #define CIF_MI_MP_PINGPONG_ENABLE BIT(11)
156 #define CIF_MI_SP_PINGPONG_ENABLE BIT(12)
157 #define CIF_MI_MP_AUTOUPDATE_ENABLE BIT(13)
158 #define CIF_MI_SP_AUTOUPDATE_ENABLE BIT(14)
159 #define CIF_MI_LAST_PIXEL_SIG_ENABLE BIT(15)
160 #define CIF_MI_CTRL_BURST_LEN_LUM_4 (0 << 16)
161 #define CIF_MI_CTRL_BURST_LEN_LUM_8 (1 << 16)
162 #define CIF_MI_CTRL_BURST_LEN_LUM_16 (2 << 16)
163 #define CIF_MI_CTRL_BURST_LEN_CHROM_4 (0 << 18)
164 #define CIF_MI_CTRL_BURST_LEN_CHROM_8 (1 << 18)
165 #define CIF_MI_CTRL_BURST_LEN_CHROM_16 (2 << 18)
166 #define CIF_MI_CTRL_INIT_BASE_EN BIT(20)
167 #define CIF_MI_CTRL_INIT_OFFSET_EN BIT(21)
168 #define MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8 (0 << 22)
169 #define MI_CTRL_MP_WRITE_YUV_SPLA (1 << 22)
170 #define MI_CTRL_MP_WRITE_YUVINT (2 << 22)
171 #define MI_CTRL_MP_WRITE_RAW12 (2 << 22)
172 #define MI_CTRL_SP_WRITE_PLA (0 << 24)
173 #define MI_CTRL_SP_WRITE_SPLA (1 << 24)
174 #define MI_CTRL_SP_WRITE_INT (2 << 24)
175 #define MI_CTRL_SP_INPUT_YUV400 (0 << 26)
176 #define MI_CTRL_SP_INPUT_YUV420 (1 << 26)
177 #define MI_CTRL_SP_INPUT_YUV422 (2 << 26)
178 #define MI_CTRL_SP_INPUT_YUV444 (3 << 26)
179 #define MI_CTRL_SP_OUTPUT_YUV400 (0 << 28)
180 #define MI_CTRL_SP_OUTPUT_YUV420 (1 << 28)
181 #define MI_CTRL_SP_OUTPUT_YUV422 (2 << 28)
182 #define MI_CTRL_SP_OUTPUT_YUV444 (3 << 28)
183 #define MI_CTRL_SP_OUTPUT_RGB565 (4 << 28)
184 #define MI_CTRL_SP_OUTPUT_RGB666 (5 << 28)
185 #define MI_CTRL_SP_OUTPUT_ARGB888 (6 << 28)
186 #define MI_CTRL_SP_OUTPUT_RGB888 (7 << 28)
187
188 #define MI_CTRL_MP_FMT_MASK GENMASK(23, 22)
189 #define MI_CTRL_SP_FMT_MASK GENMASK(30, 24)
190
191 /* MI_INIT */
192 #define CIF_MI_INIT_SKIP BIT(2)
193 #define CIF_MI_INIT_SOFT_UPD BIT(4)
194
195 /* MI_CTRL_SHD */
196 #define CIF_MI_CTRL_SHD_MP_IN_ENABLED BIT(0)
197 #define CIF_MI_CTRL_SHD_SP_IN_ENABLED BIT(1)
198 #define CIF_MI_CTRL_SHD_JPEG_IN_ENABLED BIT(2)
199 #define CIF_MI_CTRL_SHD_RAW_IN_ENABLED BIT(3)
200 #define CIF_MI_CTRL_SHD_MP_OUT_ENABLED BIT(16)
201 #define CIF_MI_CTRL_SHD_SP_OUT_ENABLED BIT(17)
202 #define CIF_MI_CTRL_SHD_JPEG_OUT_ENABLED BIT(18)
203 #define CIF_MI_CTRL_SHD_RAW_OUT_ENABLED BIT(19)
204
205 /* MI_CTRL2 */
206 #define CIF_MI_CTRL2_MIPI_RAW0_PINGPONG_EN BIT(2)
207 #define CIF_MI_CTRL2_MIPI_RAW0_AUTO_UPDATE BIT(1)
208 #define CIF_MI_CTRL2_MIPI_RAW0_ENABLE BIT(0)
209
210 /* RSZ_CTRL */
211 #define CIF_RSZ_CTRL_SCALE_HY_ENABLE BIT(0)
212 #define CIF_RSZ_CTRL_SCALE_HC_ENABLE BIT(1)
213 #define CIF_RSZ_CTRL_SCALE_VY_ENABLE BIT(2)
214 #define CIF_RSZ_CTRL_SCALE_VC_ENABLE BIT(3)
215 #define CIF_RSZ_CTRL_SCALE_HY_UP BIT(4)
216 #define CIF_RSZ_CTRL_SCALE_HC_UP BIT(5)
217 #define CIF_RSZ_CTRL_SCALE_VY_UP BIT(6)
218 #define CIF_RSZ_CTRL_SCALE_VC_UP BIT(7)
219 #define CIF_RSZ_CTRL_CFG_UPD BIT(8)
220 #define CIF_RSZ_CTRL_CFG_UPD_AUTO BIT(9)
221 #define CIF_RSZ_SCALER_FACTOR BIT(16)
222
223 /* MI_IMSC - MI_MIS - MI_RIS - MI_ICR - MI_ISR */
224 #define CIF_MI_FRAME(stream) ({ \
225 typeof(stream) __stream = (stream); \
226 !__stream->config ? 0 : \
227 __stream->config->frame_end_id; \
228 })
229 #define CIF_MI_MP_FRAME BIT(0)
230 #define CIF_MI_SP_FRAME BIT(1)
231 #define CIF_MI_MBLK_LINE BIT(2)
232 #define CIF_MI_FILL_MP_Y BIT(3)
233 #define CIF_MI_WRAP_MP_Y BIT(4)
234 #define CIF_MI_WRAP_MP_CB BIT(5)
235 #define CIF_MI_WRAP_MP_CR BIT(6)
236 #define CIF_MI_WRAP_SP_Y BIT(7)
237 #define CIF_MI_WRAP_SP_CB BIT(8)
238 #define CIF_MI_WRAP_SP_CR BIT(9)
239 #define CIF_MI_DMA_READY BIT(11)
240
241 /* MI_STATUS */
242 #define CIF_MI_STATUS_MP_Y_FIFO_FULL BIT(0)
243 #define CIF_MI_STATUS_SP_Y_FIFO_FULL BIT(4)
244
245 /* MI_DMA_CTRL */
246 #define CIF_MI_DMA_CTRL_BURST_LEN_LUM_4 (0 << 0)
247 #define CIF_MI_DMA_CTRL_BURST_LEN_LUM_8 BIT(0)
248 #define CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 BIT(1)
249 #define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_4 (0 << 2)
250 #define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_8 BIT(2)
251 #define CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16 BIT(3)
252 #define CIF_MI_DMA_CTRL_READ_FMT_PLANAR (0 << 4)
253 #define CIF_MI_DMA_CTRL_READ_FMT_SPLANAR (1 << 4)
254 #define CIF_MI_DMA_CTRL_READ_FMT_PACKED (2 << 4)
255 #define CIF_MI_DMA_CTRL_FMT_YUV400 (0 << 6)
256 #define CIF_MI_DMA_CTRL_FMT_YUV420 (1 << 6)
257 #define CIF_MI_DMA_CTRL_FMT_YUV422 (2 << 6)
258 #define CIF_MI_DMA_CTRL_FMT_YUV444 (3 << 6)
259 #define CIF_MI_DMA_CTRL_BYTE_SWAP BIT(8)
260 #define CIF_MI_DMA_CTRL_CONTINUOUS_ENA BIT(9)
261 #define CIF_MI_DMA_CTRL_RGB_BAYER_NO (0 << 12)
262 #define CIF_MI_DMA_CTRL_RGB_BAYER_8BIT (1 << 12)
263 #define CIF_MI_DMA_CTRL_RGB_BAYER_16BIT (2 << 12)
264 /* MI_DMA_START */
265 #define CIF_MI_DMA_START_ENABLE BIT(0)
266 /* MI_XTD_FORMAT_CTRL */
267 #define CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP BIT(0)
268 #define CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP BIT(1)
269 #define CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP BIT(2)
270
271 /* CCL */
272 #define CIF_CCL_CIF_CLK_DIS BIT(2)
273 /* VI_ISP_CLK_CTRL */
274 #define CIF_CLK_CTRL_ISP_RAW BIT(0)
275 #define CIF_CLK_CTRL_ISP_RGB BIT(1)
276 #define CIF_CLK_CTRL_ISP_YUV BIT(2)
277 #define CIF_CLK_CTRL_ISP_3A BIT(3)
278 #define CIF_CLK_CTRL_MIPI_RAW BIT(4)
279 #define CIF_CLK_CTRL_ISP_IE BIT(5)
280 #define CIF_CLK_CTRL_RSZ_RAM BIT(6)
281 #define CIF_CLK_CTRL_JPEG_RAM BIT(7)
282 #define CIF_CLK_CTRL_ACLK_ISP BIT(8)
283 #define CIF_CLK_CTRL_MI_IDC BIT(9)
284 #define CIF_CLK_CTRL_MI_MP BIT(10)
285 #define CIF_CLK_CTRL_MI_JPEG BIT(11)
286 #define CIF_CLK_CTRL_MI_DP BIT(12)
287 #define CIF_CLK_CTRL_MI_Y12 BIT(13)
288 #define CIF_CLK_CTRL_MI_SP BIT(14)
289 #define CIF_CLK_CTRL_MI_RAW0 BIT(15)
290 #define CIF_CLK_CTRL_MI_RAW1 BIT(16)
291 #define CIF_CLK_CTRL_MI_READ BIT(17)
292 #define CIF_CLK_CTRL_MI_RAWRD BIT(18)
293 #define CIF_CLK_CTRL_CP BIT(19)
294 #define CIF_CLK_CTRL_IE BIT(20)
295 #define CIF_CLK_CTRL_SI BIT(21)
296 #define CIF_CLK_CTRL_RSZM BIT(22)
297 #define CIF_CLK_CTRL_DPMUX BIT(23)
298 #define CIF_CLK_CTRL_JPEG BIT(24)
299 #define CIF_CLK_CTRL_RSZS BIT(25)
300 #define CIF_CLK_CTRL_MIPI BIT(26)
301 #define CIF_CLK_CTRL_MARVINMI BIT(27)
302 /* ICCL */
303 #define CIF_ICCL_ISP_CLK BIT(0)
304 #define CIF_ICCL_CP_CLK BIT(1)
305 #define CIF_ICCL_RES_2 BIT(2)
306 #define CIF_ICCL_MRSZ_CLK BIT(3)
307 #define CIF_ICCL_SRSZ_CLK BIT(4)
308 #define CIF_ICCL_JPEG_CLK BIT(5)
309 #define CIF_ICCL_MI_CLK BIT(6)
310 #define CIF_ICCL_RES_7 BIT(7)
311 #define CIF_ICCL_IE_CLK BIT(8)
312 #define CIF_ICCL_SIMP_CLK BIT(9)
313 #define CIF_ICCL_SMIA_CLK BIT(10)
314 #define CIF_ICCL_MIPI_CLK BIT(11)
315 #define CIF_ICCL_DCROP_CLK BIT(12)
316 /* IRCL */
317 #define CIF_IRCL_ISP_SW_RST BIT(0)
318 #define CIF_IRCL_CP_SW_RST BIT(1)
319 #define CIF_IRCL_YCS_SW_RST BIT(2)
320 #define CIF_IRCL_MRSZ_SW_RST BIT(3)
321 #define CIF_IRCL_SRSZ_SW_RST BIT(4)
322 #define CIF_IRCL_JPEG_SW_RST BIT(5)
323 #define CIF_IRCL_MI_SW_RST BIT(6)
324 #define CIF_IRCL_CIF_SW_RST BIT(7)
325 #define CIF_IRCL_IE_SW_RST BIT(8)
326 #define CIF_IRCL_SI_SW_RST BIT(9)
327 #define CIF_IRCL_MIPI_SW_RST BIT(11)
328
329 /* C_PROC_CTR */
330 #define CIF_C_PROC_CTR_ENABLE BIT(0)
331 #define CIF_C_PROC_YOUT_FULL BIT(1)
332 #define CIF_C_PROC_YIN_FULL BIT(2)
333 #define CIF_C_PROC_COUT_FULL BIT(3)
334 #define CIF_C_PROC_CTRL_RESERVED 0xFFFFFFFE
335 #define CIF_C_PROC_CONTRAST_RESERVED 0xFFFFFF00
336 #define CIF_C_PROC_BRIGHTNESS_RESERVED 0xFFFFFF00
337 #define CIF_C_PROC_HUE_RESERVED 0xFFFFFF00
338 #define CIF_C_PROC_SATURATION_RESERVED 0xFFFFFF00
339 #define CIF_C_PROC_MACC_RESERVED 0xE000E000
340 #define CIF_C_PROC_TONE_RESERVED 0xF000
341 /* DUAL_CROP_CTRL */
342 #define CIF_DUAL_CROP_MP_MODE_BYPASS (0 << 0)
343 #define CIF_DUAL_CROP_MP_MODE_YUV (1 << 0)
344 #define CIF_DUAL_CROP_MP_MODE_RAW (2 << 0)
345 #define CIF_DUAL_CROP_SP_MODE_BYPASS (0 << 2)
346 #define CIF_DUAL_CROP_SP_MODE_YUV (1 << 2)
347 #define CIF_DUAL_CROP_SP_MODE_RAW (2 << 2)
348 #define CIF_DUAL_CROP_CFG_UPD_PERMANENT BIT(4)
349 #define CIF_DUAL_CROP_CFG_UPD BIT(5)
350 #define CIF_DUAL_CROP_GEN_CFG_UPD BIT(6)
351
352 /* IMG_EFF_CTRL */
353 #define CIF_IMG_EFF_CTRL_ENABLE BIT(0)
354 #define CIF_IMG_EFF_CTRL_MODE_BLACKWHITE (0 << 1)
355 #define CIF_IMG_EFF_CTRL_MODE_NEGATIVE (1 << 1)
356 #define CIF_IMG_EFF_CTRL_MODE_SEPIA (2 << 1)
357 #define CIF_IMG_EFF_CTRL_MODE_COLOR_SEL (3 << 1)
358 #define CIF_IMG_EFF_CTRL_MODE_EMBOSS (4 << 1)
359 #define CIF_IMG_EFF_CTRL_MODE_SKETCH (5 << 1)
360 #define CIF_IMG_EFF_CTRL_MODE_SHARPEN (6 << 1)
361 #define CIF_IMG_EFF_CTRL_MODE_RKSHARPEN (7 << 1)
362 #define CIF_IMG_EFF_CTRL_CFG_UPD BIT(4)
363 #define CIF_IMG_EFF_CTRL_YCBCR_FULL BIT(5)
364
365 #define CIF_IMG_EFF_CTRL_MODE_BLACKWHITE_SHIFT 0
366 #define CIF_IMG_EFF_CTRL_MODE_NEGATIVE_SHIFT 1
367 #define CIF_IMG_EFF_CTRL_MODE_SEPIA_SHIFT 2
368 #define CIF_IMG_EFF_CTRL_MODE_COLOR_SEL_SHIFT 3
369 #define CIF_IMG_EFF_CTRL_MODE_EMBOSS_SHIFT 4
370 #define CIF_IMG_EFF_CTRL_MODE_SKETCH_SHIFT 5
371 #define CIF_IMG_EFF_CTRL_MODE_SHARPEN_SHIFT 6
372 #define CIF_IMG_EFF_CTRL_MODE_MASK 0xE
373
374 /* IMG_EFF_COLOR_SEL */
375 #define CIF_IMG_EFF_COLOR_RGB 0
376 #define CIF_IMG_EFF_COLOR_B (1 << 0)
377 #define CIF_IMG_EFF_COLOR_G (2 << 0)
378 #define CIF_IMG_EFF_COLOR_GB (3 << 0)
379 #define CIF_IMG_EFF_COLOR_R (4 << 0)
380 #define CIF_IMG_EFF_COLOR_RB (5 << 0)
381 #define CIF_IMG_EFF_COLOR_RG (6 << 0)
382 #define CIF_IMG_EFF_COLOR_RGB2 (7 << 0)
383
384 /* MIPI_CTRL */
385 #define CIF_MIPI_CTRL_OUTPUT_ENA BIT(0)
386 #define CIF_MIPI_CTRL_FLUSH_FIFO BIT(1)
387 #define CIF_MIPI_CTRL_SHUTDOWNLANES(a) (((a) & 0xF) << 8)
388 #define CIF_MIPI_CTRL_NUM_LANES(a) (((a) & 0x3) << 12)
389 #define CIF_MIPI_CTRL_ERR_SOT_HS_SKIP BIT(16)
390 #define CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP BIT(17)
391 #define CIF_MIPI_CTRL_CLOCKLANE_ENA BIT(18)
392
393 /* MIPI_DATA_SEL */
394 #define CIF_MIPI_DATA_SEL_VC(a) (((a) & 0x3) << 6)
395 #define CIF_MIPI_DATA_SEL_DT(a) (((a) & 0x3F) << 0)
396 /* MIPI DATA_TYPE */
397 #define CIF_CSI2_DT_EBD 0x12
398 #define CIF_CSI2_DT_YUV420_8b 0x18
399 #define CIF_CSI2_DT_YUV420_10b 0x19
400 #define CIF_CSI2_DT_YUV422_8b 0x1E
401 #define CIF_CSI2_DT_YUV422_10b 0x1F
402 #define CIF_CSI2_DT_RGB565 0x22
403 #define CIF_CSI2_DT_RGB666 0x23
404 #define CIF_CSI2_DT_RGB888 0x24
405 #define CIF_CSI2_DT_RAW8 0x2A
406 #define CIF_CSI2_DT_RAW10 0x2B
407 #define CIF_CSI2_DT_RAW12 0x2C
408 #define CIF_CSI2_DT_SPD 0x2F
409
410 /* MIPI_IMSC, MIPI_RIS, MIPI_MIS, MIPI_ICR, MIPI_ISR */
411 #define CIF_MIPI_SYNC_FIFO_OVFLW(a) (((a) & 0xF) << 0)
412 #define CIF_MIPI_ERR_SOT(a) (((a) & 0xF) << 4)
413 #define CIF_MIPI_ERR_SOT_SYNC(a) (((a) & 0xF) << 8)
414 #define CIF_MIPI_ERR_EOT_SYNC(a) (((a) & 0xF) << 12)
415 #define CIF_MIPI_ERR_CTRL(a) (((a) & 0xF) << 16)
416 #define CIF_MIPI_ERR_PROTOCOL BIT(20)
417 #define CIF_MIPI_ERR_ECC1 BIT(21)
418 #define CIF_MIPI_ERR_ECC2 BIT(22)
419 #define CIF_MIPI_ERR_CS BIT(23)
420 #define CIF_MIPI_FRAME_END BIT(24)
421 #define CIF_MIPI_ADD_DATA_OVFLW BIT(25)
422 #define CIF_MIPI_ADD_DATA_WATER_MARK BIT(26)
423
424 #define CIF_MIPI_ERR_CSI (CIF_MIPI_ERR_PROTOCOL | \
425 CIF_MIPI_ERR_ECC1 | \
426 CIF_MIPI_ERR_ECC2 | \
427 CIF_MIPI_ERR_CS)
428
429 #define CIF_MIPI_ERR_DPHY (CIF_MIPI_ERR_SOT(0xF) | \
430 CIF_MIPI_ERR_SOT_SYNC(0xF) | \
431 CIF_MIPI_ERR_EOT_SYNC(0xF) | \
432 CIF_MIPI_ERR_CTRL(0xF))
433
434 /* SUPER_IMPOSE */
435 #define CIF_SUPER_IMP_CTRL_NORMAL_MODE BIT(0)
436 #define CIF_SUPER_IMP_CTRL_REF_IMG_MEM BIT(1)
437 #define CIF_SUPER_IMP_CTRL_TRANSP_DIS BIT(2)
438
439 /* ISP HISTOGRAM CALCULATION : ISP_HIST_PROP */
440 #define CIF_ISP_HIST_PROP_MODE_DIS_V10 (0 << 0)
441 #define CIF_ISP_HIST_PROP_MODE_RGB_V10 (1 << 0)
442 #define CIF_ISP_HIST_PROP_MODE_RED_V10 (2 << 0)
443 #define CIF_ISP_HIST_PROP_MODE_GREEN_V10 (3 << 0)
444 #define CIF_ISP_HIST_PROP_MODE_BLUE_V10 (4 << 0)
445 #define CIF_ISP_HIST_PROP_MODE_LUM_V10 (5 << 0)
446 #define CIF_ISP_HIST_PROP_MODE_MASK_V10 0x7
447 #define CIF_ISP_HIST_PREDIV_SET_V10(x) (((x) & 0x7F) << 3)
448 #define CIF_ISP_HIST_WEIGHT_SET_V10(v0, v1, v2, v3) \
449 (((v0) & 0x1F) | (((v1) & 0x1F) << 8) |\
450 (((v2) & 0x1F) << 16) | \
451 (((v3) & 0x1F) << 24))
452
453 #define CIF_ISP_HIST_WINDOW_OFFSET_RESERVED_V10 0xFFFFF000
454 #define CIF_ISP_HIST_WINDOW_SIZE_RESERVED_V10 0xFFFFF800
455 #define CIF_ISP_HIST_WEIGHT_RESERVED_V10 0xE0E0E0E0
456 #define CIF_ISP_MAX_HIST_PREDIVIDER_V10 0x0000007F
457 #define CIF_ISP_HIST_ROW_NUM_V10 5
458 #define CIF_ISP_HIST_COLUMN_NUM_V10 5
459
460 /* ISP HISTOGRAM CALCULATION : CIF_ISP_HIST */
461 #define CIF_ISP_HIST_CTRL_EN_SET_V12(x) (((x) & 0x01) << 0)
462 #define CIF_ISP_HIST_CTRL_EN_MASK_V12 CIF_ISP_HIST_CTRL_EN_SET_V12(0x01)
463 #define CIF_ISP_HIST_CTRL_STEPSIZE_SET_V12(x) (((x) & 0x7F) << 1)
464 #define CIF_ISP_HIST_CTRL_MODE_SET_V12(x) (((x) & 0x07) << 8)
465 #define CIF_ISP_HIST_CTRL_MODE_MASK_V12 CIF_ISP_HIST_CTRL_MODE_SET_V12(0x07)
466 #define CIF_ISP_HIST_CTRL_AUTOSTOP_SET_V12(x) (((x) & 0x01) << 11)
467 #define CIF_ISP_HIST_CTRL_WATERLINE_SET_V12(x) (((x) & 0xFFF) << 12)
468 #define CIF_ISP_HIST_CTRL_DATASEL_SET_V12(x) (((x) & 0x07) << 24)
469 #define CIF_ISP_HIST_CTRL_INTRSEL_SET_V12(x) (((x) & 0x01) << 27)
470 #define CIF_ISP_HIST_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 28)
471 #define CIF_ISP_HIST_CTRL_DBGEN_SET_V12(x) (((x) & 0x01) << 30)
472 #define CIF_ISP_HIST_ROW_NUM_V12 15
473 #define CIF_ISP_HIST_COLUMN_NUM_V12 15
474 #define CIF_ISP_HIST_WEIGHT_REG_SIZE_V12 \
475 (CIF_ISP_HIST_ROW_NUM_V12 * CIF_ISP_HIST_COLUMN_NUM_V12)
476
477 #define CIF_ISP_HIST_WEIGHT_SET_V12(v0, v1, v2, v3) \
478 (((v0) & 0x3F) | (((v1) & 0x3F) << 8) |\
479 (((v2) & 0x3F) << 16) |\
480 (((v3) & 0x3F) << 24))
481
482 #define CIF_ISP_HIST_OFFS_SET_V12(v0, v1) \
483 (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
484 #define CIF_ISP_HIST_SIZE_SET_V12(v0, v1) \
485 (((v0) & 0x7FF) | (((v1) & 0x7FF) << 16))
486
487 #define CIF_ISP_HIST_GET_BIN0_V12(x) \
488 ((x) & 0xFFFF)
489 #define CIF_ISP_HIST_GET_BIN1_V12(x) \
490 (((x) >> 16) & 0xFFFF)
491
492 /* AUTO FOCUS MEASUREMENT: ISP_AFM_CTRL */
493 #define ISP_AFM_CTRL_ENABLE BIT(0)
494
495 /* SHUTTER CONTROL */
496 #define CIF_ISP_SH_CTRL_SH_ENA BIT(0)
497 #define CIF_ISP_SH_CTRL_REP_EN BIT(1)
498 #define CIF_ISP_SH_CTRL_SRC_SH_TRIG BIT(2)
499 #define CIF_ISP_SH_CTRL_EDGE_POS BIT(3)
500 #define CIF_ISP_SH_CTRL_POL_LOW BIT(4)
501
502 /* FLASH MODULE */
503 /* ISP_FLASH_CMD */
504 #define CIF_FLASH_CMD_PRELIGHT_ON BIT(0)
505 #define CIF_FLASH_CMD_FLASH_ON BIT(1)
506 #define CIF_FLASH_CMD_PRE_FLASH_ON BIT(2)
507 /* ISP_FLASH_CONFIG */
508 #define CIF_FLASH_CONFIG_PRELIGHT_END BIT(0)
509 #define CIF_FLASH_CONFIG_VSYNC_POS BIT(1)
510 #define CIF_FLASH_CONFIG_PRELIGHT_LOW BIT(2)
511 #define CIF_FLASH_CONFIG_SRC_FL_TRIG BIT(3)
512 #define CIF_FLASH_CONFIG_DELAY(a) (((a) & 0xF) << 4)
513
514 /* Demosaic: ISP_DEMOSAIC */
515 #define CIF_ISP_DEMOSAIC_BYPASS BIT(10)
516 #define CIF_ISP_DEMOSAIC_TH(x) ((x) & 0xFF)
517
518 /* AWB */
519 /* ISP_AWB_PROP */
520 #define CIF_ISP_AWB_YMAX_CMP_EN BIT(2)
521 #define CIF_ISP_AWB_YMAX_READ(x) (((x) >> 2) & 1)
522 #define CIF_ISP_AWB_MODE_RGB_EN ((1 << 31) | (0x2 << 0))
523 #define CIF_ISP_AWB_MODE_YCBCR_EN ((0 << 31) | (0x2 << 0))
524 #define CIF_ISP_AWB_MODE_RGB BIT(31)
525 #define CIF_ISP_AWB_ENABLE (0x2 << 0)
526 #define CIF_ISP_AWB_MODE_MASK_NONE 0xFFFFFFFC
527 #define CIF_ISP_AWB_MODE_READ(x) ((x) & 3)
528 #define CIF_ISP_AWB_SET_FRAMES_V12(x) (((x) & 0x07) << 28)
529 #define CIF_ISP_AWB_SET_FRAMES_MASK_V12 CIF_ISP_AWB_SET_FRAMES_V12(0x07)
530 /* ISP_AWB_GAIN_RB, ISP_AWB_GAIN_G */
531 #define CIF_ISP_AWB_GAIN_R_SET(x) (((x) & 0x3FF) << 16)
532 #define CIF_ISP_AWB_GAIN_R_READ(x) (((x) >> 16) & 0x3FF)
533 #define CIF_ISP_AWB_GAIN_B_SET(x) ((x) & 0x3FF)
534 #define CIF_ISP_AWB_GAIN_B_READ(x) ((x) & 0x3FF)
535 /* ISP_AWB_REF */
536 #define CIF_ISP_AWB_REF_CR_SET(x) (((x) & 0xFF) << 8)
537 #define CIF_ISP_AWB_REF_CR_READ(x) (((x) >> 8) & 0xFF)
538 #define CIF_ISP_AWB_REF_CB_READ(x) ((x) & 0xFF)
539 /* ISP_AWB_THRESH */
540 #define CIF_ISP_AWB_MAX_CS_SET(x) (((x) & 0xFF) << 8)
541 #define CIF_ISP_AWB_MAX_CS_READ(x) (((x) >> 8) & 0xFF)
542 #define CIF_ISP_AWB_MIN_C_READ(x) ((x) & 0xFF)
543 #define CIF_ISP_AWB_MIN_Y_SET(x) (((x) & 0xFF) << 16)
544 #define CIF_ISP_AWB_MIN_Y_READ(x) (((x) >> 16) & 0xFF)
545 #define CIF_ISP_AWB_MAX_Y_SET(x) (((x) & 0xFF) << 24)
546 #define CIF_ISP_AWB_MAX_Y_READ(x) (((x) >> 24) & 0xFF)
547 /* ISP_AWB_MEAN */
548 #define CIF_ISP_AWB_GET_MEAN_CR_R(x) ((x) & 0xFF)
549 #define CIF_ISP_AWB_GET_MEAN_CB_B(x) (((x) >> 8) & 0xFF)
550 #define CIF_ISP_AWB_GET_MEAN_Y_G(x) (((x) >> 16) & 0xFF)
551 /* ISP_AWB_WHITE_CNT */
552 #define CIF_ISP_AWB_GET_PIXEL_CNT(x) ((x) & 0x3FFFFFF)
553
554 #define CIF_ISP_AWB_GAINS_MAX_VAL 0x000003FF
555 #define CIF_ISP_AWB_WINDOW_OFFSET_MAX 0x00000FFF
556 #define CIF_ISP_AWB_WINDOW_MAX_SIZE 0x00001FFF
557 #define CIF_ISP_AWB_CBCR_MAX_REF 0x000000FF
558 #define CIF_ISP_AWB_THRES_MAX_YC 0x000000FF
559
560 /* AE */
561 /* ISP_EXP_CTRL */
562 #define CIF_ISP_EXP_ENA BIT(0)
563 #define CIF_ISP_EXP_CTRL_AUTOSTOP BIT(1)
564 #define CIF_ISP_EXP_CTRL_WNDNUM_SET_V12(x) (((x) & 0x03) << 2)
565 /*
566 *'1' luminance calculation according to Y=(R+G+B) x 0.332 (85/256)
567 *'0' luminance calculation according to Y=16+0.25R+0.5G+0.1094B
568 */
569 #define CIF_ISP_EXP_CTRL_MEASMODE_1 BIT(31)
570
571 /* ISP_EXP_H_SIZE */
572 #define CIF_ISP_EXP_H_SIZE_SET_V10(x) ((x) & 0x7FF)
573 #define CIF_ISP_EXP_HEIGHT_MASK_V10 0x000007FF
574 /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
575 #define CIF_ISP_EXP_V_SIZE_SET_V10(x) ((x) & 0x7FE)
576
577 /* ISP_EXP_H_OFFSET */
578 #define CIF_ISP_EXP_H_OFFSET_SET_V10(x) ((x) & 0x1FFF)
579 #define CIF_ISP_EXP_MAX_HOFFS_V10 2424
580 /* ISP_EXP_V_OFFSET */
581 #define CIF_ISP_EXP_V_OFFSET_SET_V10(x) ((x) & 0x1FFF)
582 #define CIF_ISP_EXP_MAX_VOFFS_V10 1806
583
584 #define CIF_ISP_EXP_ROW_NUM_V10 5
585 #define CIF_ISP_EXP_COLUMN_NUM_V10 5
586 #define CIF_ISP_EXP_NUM_LUMA_REGS_V10 \
587 (CIF_ISP_EXP_ROW_NUM_V10 * CIF_ISP_EXP_COLUMN_NUM_V10)
588 #define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 516
589 #define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 35
590 #define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 390
591 #define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 28
592 #define CIF_ISP_EXP_MAX_HSIZE_V10 \
593 (CIF_ISP_EXP_BLOCK_MAX_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
594 #define CIF_ISP_EXP_MIN_HSIZE_V10 \
595 (CIF_ISP_EXP_BLOCK_MIN_HSIZE_V10 * CIF_ISP_EXP_COLUMN_NUM_V10 + 1)
596 #define CIF_ISP_EXP_MAX_VSIZE_V10 \
597 (CIF_ISP_EXP_BLOCK_MAX_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1)
598 #define CIF_ISP_EXP_MIN_VSIZE_V10 \
599 (CIF_ISP_EXP_BLOCK_MIN_VSIZE_V10 * CIF_ISP_EXP_ROW_NUM_V10 + 1)
600
601 /* ISP_EXP_H_SIZE */
602 #define CIF_ISP_EXP_H_SIZE_SET_V12(x) ((x) & 0x7FF)
603 #define CIF_ISP_EXP_HEIGHT_MASK_V12 0x000007FF
604 /* ISP_EXP_V_SIZE : vertical size must be a multiple of 2). */
605 #define CIF_ISP_EXP_V_SIZE_SET_V12(x) (((x) & 0x7FE) << 16)
606
607 /* ISP_EXP_H_OFFSET */
608 #define CIF_ISP_EXP_H_OFFSET_SET_V12(x) ((x) & 0x1FFF)
609 #define CIF_ISP_EXP_MAX_HOFFS_V12 0x1FFF
610 /* ISP_EXP_V_OFFSET */
611 #define CIF_ISP_EXP_V_OFFSET_SET_V12(x) (((x) & 0x1FFF) << 16)
612 #define CIF_ISP_EXP_MAX_VOFFS_V12 0x1FFF
613
614 #define CIF_ISP_EXP_ROW_NUM_V12 15
615 #define CIF_ISP_EXP_COLUMN_NUM_V12 15
616 #define CIF_ISP_EXP_NUM_LUMA_REGS_V12 \
617 (CIF_ISP_EXP_ROW_NUM_V12 * CIF_ISP_EXP_COLUMN_NUM_V12)
618 #define CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 0x7FF
619 #define CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 0xE
620 #define CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 0x7FE
621 #define CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 0xE
622 #define CIF_ISP_EXP_MAX_HSIZE_V12 \
623 (CIF_ISP_EXP_BLOCK_MAX_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
624 #define CIF_ISP_EXP_MIN_HSIZE_V12 \
625 (CIF_ISP_EXP_BLOCK_MIN_HSIZE_V12 * CIF_ISP_EXP_COLUMN_NUM_V12 + 1)
626 #define CIF_ISP_EXP_MAX_VSIZE_V12 \
627 (CIF_ISP_EXP_BLOCK_MAX_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1)
628 #define CIF_ISP_EXP_MIN_VSIZE_V12 \
629 (CIF_ISP_EXP_BLOCK_MIN_VSIZE_V12 * CIF_ISP_EXP_ROW_NUM_V12 + 1)
630
631 #define CIF_ISP_EXP_GET_MEAN_xy0_V12(x) ((x) & 0xFF)
632 #define CIF_ISP_EXP_GET_MEAN_xy1_V12(x) (((x) >> 8) & 0xFF)
633 #define CIF_ISP_EXP_GET_MEAN_xy2_V12(x) (((x) >> 16) & 0xFF)
634 #define CIF_ISP_EXP_GET_MEAN_xy3_V12(x) (((x) >> 24) & 0xFF)
635
636 /* LSC: ISP_LSC_CTRL */
637 #define CIF_ISP_LSC_CTRL_ENA BIT(0)
638 #define CIF_ISP_LSC_SECT_SIZE_RESERVED 0xFC00FC00
639 #define CIF_ISP_LSC_GRAD_RESERVED_V10 0xF000F000
640 #define CIF_ISP_LSC_SAMPLE_RESERVED_V10 0xF000F000
641 #define CIF_ISP_LSC_GRAD_RESERVED_V12 0xE000E000
642 #define CIF_ISP_LSC_SAMPLE_RESERVED_V12 0xE000E000
643 #define CIF_ISP_LSC_SECTORS_MAX 17
644 #define CIF_ISP_LSC_TABLE_DATA_V10(v0, v1) \
645 (((v0) & 0xFFF) | (((v1) & 0xFFF) << 12))
646 #define CIF_ISP_LSC_TABLE_DATA_V12(v0, v1) \
647 (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 13))
648 #define CIF_ISP_LSC_SECT_SIZE(v0, v1) \
649 (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
650 #define CIF_ISP_LSC_GRAD_SIZE(v0, v1) \
651 (((v0) & 0xFFF) | (((v1) & 0xFFF) << 16))
652
653 /* LSC: ISP_LSC_TABLE_SEL */
654 #define CIF_ISP_LSC_TABLE_0 0
655 #define CIF_ISP_LSC_TABLE_1 1
656
657 /* LSC: ISP_LSC_STATUS */
658 #define CIF_ISP_LSC_ACTIVE_TABLE BIT(1)
659 #define CIF_ISP_LSC_TABLE_ADDRESS_0 0
660 #define CIF_ISP_LSC_TABLE_ADDRESS_153 153
661
662 /* FLT */
663 /* ISP_FILT_MODE */
664 #define CIF_ISP_FLT_ENA BIT(0)
665
666 /*
667 * 0: green filter static mode (active filter factor = FILT_FAC_MID)
668 * 1: dynamic noise reduction/sharpen Default
669 */
670 #define CIF_ISP_FLT_MODE_DNR BIT(1)
671 #define CIF_ISP_FLT_MODE_MAX 1
672 #define CIF_ISP_FLT_CHROMA_V_MODE(x) (((x) & 0x3) << 4)
673 #define CIF_ISP_FLT_CHROMA_H_MODE(x) (((x) & 0x3) << 6)
674 #define CIF_ISP_FLT_CHROMA_MODE_MAX 3
675 #define CIF_ISP_FLT_GREEN_STAGE1(x) (((x) & 0xF) << 8)
676 #define CIF_ISP_FLT_GREEN_STAGE1_MAX 8
677 #define CIF_ISP_FLT_THREAD_RESERVED 0xFFFFFC00
678 #define CIF_ISP_FLT_FAC_RESERVED 0xFFFFFFC0
679 #define CIF_ISP_FLT_LUM_WEIGHT_RESERVED 0xFFF80000
680
681 #define CIF_ISP_CTK_COEFF_RESERVED 0xFFFFF800
682 #define CIF_ISP_XTALK_OFFSET_RESERVED 0xFFFFF000
683
684 #define CIF_ISP_FLT_LEVEL_OLD_LP BIT(16)
685
686 /* GOC */
687 #define CIF_ISP_GAMMA_OUT_MODE_EQU BIT(0)
688 #define CIF_ISP_GOC_MODE_MAX 1
689 #define CIF_ISP_GOC_RESERVED 0xFFFFF800
690 /* ISP_CTRL BIT 11*/
691 #define CIF_ISP_CTRL_ISP_GAMMA_OUT_ENA_READ(x) (((x) >> 11) & 1)
692
693 /* DPCC */
694 /* ISP_DPCC_MODE */
695 #define CIF_ISP_DPCC_ENA BIT(0)
696 #define CIF_ISP_DPCC_MODE_MAX 0x07
697 #define CIF_ISP_DPCC_OUTPUTMODE_MAX 0x0F
698 #define CIF_ISP_DPCC_SETUSE_MAX 0x0F
699 #define CIF_ISP_DPCC_METHODS_SET_RESERVED 0xFFFFE000
700 #define CIF_ISP_DPCC_LINE_THRESH_RESERVED 0xFFFF0000
701 #define CIF_ISP_DPCC_LINE_MAD_FAC_RESERVED 0xFFFFC0C0
702 #define CIF_ISP_DPCC_PG_FAC_RESERVED 0xFFFFC0C0
703 #define CIF_ISP_DPCC_RND_THRESH_RESERVED 0xFFFF0000
704 #define CIF_ISP_DPCC_RG_FAC_RESERVED 0xFFFFC0C0
705 #define CIF_ISP_DPCC_RO_LIMIT_RESERVED 0xFFFFF000
706 #define CIF_ISP_DPCC_RND_OFFS_RESERVED 0xFFFFF000
707
708 /* BLS */
709 /* ISP_BLS_CTRL */
710 #define CIF_ISP_BLS_ENA BIT(0)
711 #define CIF_ISP_BLS_MODE_MEASURED BIT(1)
712 #define CIF_ISP_BLS_MODE_FIXED 0
713 #define CIF_ISP_BLS_WINDOW_1 (1 << 2)
714 #define CIF_ISP_BLS_WINDOW_2 (2 << 2)
715
716 /* GAMMA-IN */
717 #define CIFISP_DEGAMMA_X_RESERVED \
718 ((1 << 31) | (1 << 27) | (1 << 23) | (1 << 19) |\
719 (1 << 15) | (1 << 11) | (1 << 7) | (1 << 3))
720 #define CIFISP_DEGAMMA_Y_RESERVED 0xFFFFF000
721
722 /* GAMMA-OUT */
723 #define CIF_ISP_GAMMA_REG_VALUE_V12(x, y) \
724 (((x) & 0xFFF) << 16 | ((y) & 0xFFF) << 0)
725
726 /* AFM */
727 #define CIF_ISP_AFM_ENA BIT(0)
728 #define CIF_ISP_AFM_THRES_RESERVED 0xFFFF0000
729 #define CIF_ISP_AFM_VAR_SHIFT_RESERVED 0xFFF8FFF8
730 #define CIF_ISP_AFM_WINDOW_X_RESERVED 0xE000
731 #define CIF_ISP_AFM_WINDOW_Y_RESERVED 0xF000
732 #define CIF_ISP_AFM_WINDOW_X_MIN 0x5
733 #define CIF_ISP_AFM_WINDOW_Y_MIN 0x2
734 #define CIF_ISP_AFM_WINDOW_X(x) (((x) & 0x1FFF) << 16)
735 #define CIF_ISP_AFM_WINDOW_Y(x) ((x) & 0x1FFF)
736 #define CIF_ISP_AFM_SET_SHIFT_a_V12(x, y) (((x) & 0x7) << 16 | ((y) & 0x7) << 0)
737 #define CIF_ISP_AFM_SET_SHIFT_b_V12(x, y) (((x) & 0x7) << 20 | ((y) & 0x7) << 4)
738 #define CIF_ISP_AFM_SET_SHIFT_c_V12(x, y) (((x) & 0x7) << 24 | ((y) & 0x7) << 8)
739 #define CIF_ISP_AFM_GET_LUM_SHIFT_a_V12(x) (((x) & 0x70000) >> 16)
740 #define CIF_ISP_AFM_GET_AFM_SHIFT_a_V12(x) ((x) & 0x7)
741
742 /* DPF */
743 #define CIF_ISP_DPF_MODE_EN BIT(0)
744 #define CIF_ISP_DPF_MODE_B_FLT_DIS BIT(1)
745 #define CIF_ISP_DPF_MODE_GB_FLT_DIS BIT(2)
746 #define CIF_ISP_DPF_MODE_GR_FLT_DIS BIT(3)
747 #define CIF_ISP_DPF_MODE_R_FLT_DIS BIT(4)
748 #define CIF_ISP_DPF_MODE_RB_FLTSIZE_9x9 BIT(5)
749 #define CIF_ISP_DPF_MODE_NLL_SEGMENTATION BIT(6)
750 #define CIF_ISP_DPF_MODE_AWB_GAIN_COMP BIT(7)
751 #define CIF_ISP_DPF_MODE_LSC_GAIN_COMP BIT(8)
752 #define CIF_ISP_DPF_MODE_USE_NF_GAIN BIT(9)
753 #define CIF_ISP_DPF_NF_GAIN_RESERVED 0xFFFFF000
754 #define CIF_ISP_DPF_SPATIAL_COEFF_MAX 0x1F
755 #define CIF_ISP_DPF_NLL_COEFF_N_MAX 0x3FF
756
757 /* CSI0 */
758 #define CIF_ISP_CSI0_IMASK_LINECNT BIT(12)
759 #define CIF_ISP_CSI0_IMASK_RAW1_OUT_V_END BIT(11)
760 #define CIF_ISP_CSI0_IMASK_RAW0_OUT_V_END BIT(10)
761 #define CIF_ISP_CSI0_IMASK_FRAME_END(a) (((a) & 0x3F) << 0)
762
763 #define CIF_ISP_CSI0_IMASK2_PHY_ERRSOTHS(a) (((a) & 0x0F) << 4)
764 #define CIF_ISP_CSI0_IMASK2_PHY_ERRCONTROL(a) (((a) & 0x0F) << 16)
765 #define CIF_ISP_CSI0_IMASK1_PHY_ERRSOTSYNC(a) (((a) & 0x0F) << 8)
766 #define CIF_ISP_CSI0_IMASK1_PHY_ERREOTSYNC(a) (((a) & 0x0F) << 4)
767
768 #define CIF_ISP_CSI0_DMATX0_VC(a) (((a) & 0xFF) << 8)
769 #define CIF_ISP_CSI0_DMATX0_SIMG_SWP BIT(2)
770 #define CIF_ISP_CSI0_DMATX0_SIMG_MODE BIT(1)
771 #define CIF_ISP_CSI0_DMATX0_EN BIT(0)
772
773 /* =================================================================== */
774 /* CIF Registers */
775 /* =================================================================== */
776 #define CIF_CTRL_BASE 0x00000000
777 #define CIF_CCL (CIF_CTRL_BASE + 0x00000000)
778 #define CIF_VI_ID (CIF_CTRL_BASE + 0x00000008)
779 #define CIF_VI_ISP_CLK_CTRL_V12 (CIF_CTRL_BASE + 0x0000000C)
780 #define CIF_ICCL (CIF_CTRL_BASE + 0x00000010)
781 #define CIF_IRCL (CIF_CTRL_BASE + 0x00000014)
782 #define CIF_VI_DPCL (CIF_CTRL_BASE + 0x00000018)
783
784 #define CIF_IMG_EFF_BASE 0x00000200
785 #define CIF_IMG_EFF_CTRL (CIF_IMG_EFF_BASE + 0x00000000)
786 #define CIF_IMG_EFF_COLOR_SEL (CIF_IMG_EFF_BASE + 0x00000004)
787 #define CIF_IMG_EFF_MAT_1 (CIF_IMG_EFF_BASE + 0x00000008)
788 #define CIF_IMG_EFF_MAT_2 (CIF_IMG_EFF_BASE + 0x0000000C)
789 #define CIF_IMG_EFF_MAT_3 (CIF_IMG_EFF_BASE + 0x00000010)
790 #define CIF_IMG_EFF_MAT_4 (CIF_IMG_EFF_BASE + 0x00000014)
791 #define CIF_IMG_EFF_MAT_5 (CIF_IMG_EFF_BASE + 0x00000018)
792 #define CIF_IMG_EFF_TINT (CIF_IMG_EFF_BASE + 0x0000001C)
793 #define CIF_IMG_EFF_CTRL_SHD (CIF_IMG_EFF_BASE + 0x00000020)
794 #define CIF_IMG_EFF_SHARPEN (CIF_IMG_EFF_BASE + 0x00000024)
795
796 #define CIF_RKSHARP_CTRL (CIF_IMG_EFF_BASE + 0x00000030)
797 #define CIF_RKSHARP_YAVG_THR (CIF_IMG_EFF_BASE + 0x00000034)
798 #define CIF_RKSHARP_DELTA_P0_P1 (CIF_IMG_EFF_BASE + 0x00000038)
799 #define CIF_RKSHARP_DELTA_P2_P3 (CIF_IMG_EFF_BASE + 0x0000003c)
800 #define CIF_RKSHARP_DELTA_P4 (CIF_IMG_EFF_BASE + 0x00000040)
801 #define CIF_RKSHARP_NPIXEL_P0_P1_P2_P3 (CIF_IMG_EFF_BASE + 0x00000044)
802 #define CIF_RKSHARP_NPIXEL_P4 (CIF_IMG_EFF_BASE + 0x00000048)
803 #define CIF_RKSHARP_GAUSS_FLAT_COE1 (CIF_IMG_EFF_BASE + 0x0000004c)
804 #define CIF_RKSHARP_GAUSS_FLAT_COE2 (CIF_IMG_EFF_BASE + 0x00000050)
805 #define CIF_RKSHARP_GAUSS_FLAT_COE3 (CIF_IMG_EFF_BASE + 0x00000054)
806 #define CIF_RKSHARP_GAUSS_NOISE_COE1 (CIF_IMG_EFF_BASE + 0x00000058)
807 #define CIF_RKSHARP_GAUSS_NOISE_COE2 (CIF_IMG_EFF_BASE + 0x0000005c)
808 #define CIF_RKSHARP_GAUSS_NOISE_COE3 (CIF_IMG_EFF_BASE + 0x00000060)
809 #define CIF_RKSHARP_GAUSS_OTHER_COE1 (CIF_IMG_EFF_BASE + 0x00000064)
810 #define CIF_RKSHARP_GAUSS_OTHER_COE2 (CIF_IMG_EFF_BASE + 0x00000068)
811 #define CIF_RKSHARP_GAUSS_OTHER_COE3 (CIF_IMG_EFF_BASE + 0x0000006c)
812 #define CIF_RKSHARP_LINE1_FILTER_COE1 (CIF_IMG_EFF_BASE + 0x00000070)
813 #define CIF_RKSHARP_LINE1_FILTER_COE2 (CIF_IMG_EFF_BASE + 0x00000074)
814 #define CIF_RKSHARP_LINE2_FILTER_COE1 (CIF_IMG_EFF_BASE + 0x00000078)
815 #define CIF_RKSHARP_LINE2_FILTER_COE2 (CIF_IMG_EFF_BASE + 0x0000007c)
816 #define CIF_RKSHARP_LINE2_FILTER_COE3 (CIF_IMG_EFF_BASE + 0x00000080)
817 #define CIF_RKSHARP_LINE3_FILTER_COE1 (CIF_IMG_EFF_BASE + 0x00000084)
818 #define CIF_RKSHARP_LINE3_FILTER_COE2 (CIF_IMG_EFF_BASE + 0x00000088)
819 #define CIF_RKSHARP_GRAD_SEQ_P0_P1 (CIF_IMG_EFF_BASE + 0x0000008c)
820 #define CIF_RKSHARP_GRAD_SEQ_P2_P3 (CIF_IMG_EFF_BASE + 0x00000090)
821 #define CIF_RKSHARP_SHARP_FACTOR_P0_P1_P2 (CIF_IMG_EFF_BASE + 0x00000094)
822 #define CIF_RKSHARP_SHARP_FACTOR_P3_P4 (CIF_IMG_EFF_BASE + 0x00000098)
823 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE11_COE14 (CIF_IMG_EFF_BASE + 0x0000009c)
824 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE15_COE23 (CIF_IMG_EFF_BASE + 0x000000a0)
825 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE24_COE32 (CIF_IMG_EFF_BASE + 0x000000a4)
826 #define CIF_RKSHARP_UV_GAUSS_FLAT_COE33_COE35 (CIF_IMG_EFF_BASE + 0x000000a8)
827 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE11_COE14 (CIF_IMG_EFF_BASE + 0x000000ac)
828 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE15_COE23 (CIF_IMG_EFF_BASE + 0x000000b0)
829 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE24_COE32 (CIF_IMG_EFF_BASE + 0x000000b4)
830 #define CIF_RKSHARP_UV_GAUSS_NOISE_COE33_COE35 (CIF_IMG_EFF_BASE + 0x000000b8)
831 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE11_COE14 (CIF_IMG_EFF_BASE + 0x000000bc)
832 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE15_COE23 (CIF_IMG_EFF_BASE + 0x000000c0)
833 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE24_COE32 (CIF_IMG_EFF_BASE + 0x000000c4)
834 #define CIF_RKSHARP_UV_GAUSS_OTHER_COE33_COE35 (CIF_IMG_EFF_BASE + 0x000000c8)
835
836 #define CIF_SUPER_IMP_BASE 0x00000300
837 #define CIF_SUPER_IMP_CTRL (CIF_SUPER_IMP_BASE + 0x00000000)
838 #define CIF_SUPER_IMP_OFFSET_X (CIF_SUPER_IMP_BASE + 0x00000004)
839 #define CIF_SUPER_IMP_OFFSET_Y (CIF_SUPER_IMP_BASE + 0x00000008)
840 #define CIF_SUPER_IMP_COLOR_Y (CIF_SUPER_IMP_BASE + 0x0000000C)
841 #define CIF_SUPER_IMP_COLOR_CB (CIF_SUPER_IMP_BASE + 0x00000010)
842 #define CIF_SUPER_IMP_COLOR_CR (CIF_SUPER_IMP_BASE + 0x00000014)
843
844 #define CIF_ISP_BASE 0x00000400
845 #define CIF_ISP_CTRL (CIF_ISP_BASE + 0x00000000)
846 #define CIF_ISP_ACQ_PROP (CIF_ISP_BASE + 0x00000004)
847 #define CIF_ISP_ACQ_H_OFFS (CIF_ISP_BASE + 0x00000008)
848 #define CIF_ISP_ACQ_V_OFFS (CIF_ISP_BASE + 0x0000000C)
849 #define CIF_ISP_ACQ_H_SIZE (CIF_ISP_BASE + 0x00000010)
850 #define CIF_ISP_ACQ_V_SIZE (CIF_ISP_BASE + 0x00000014)
851 #define CIF_ISP_ACQ_NR_FRAMES (CIF_ISP_BASE + 0x00000018)
852 #define CIF_ISP_GAMMA_DX_LO (CIF_ISP_BASE + 0x0000001C)
853 #define CIF_ISP_GAMMA_DX_HI (CIF_ISP_BASE + 0x00000020)
854 #define CIF_ISP_GAMMA_R_Y0 (CIF_ISP_BASE + 0x00000024)
855 #define CIF_ISP_GAMMA_R_Y1 (CIF_ISP_BASE + 0x00000028)
856 #define CIF_ISP_GAMMA_R_Y2 (CIF_ISP_BASE + 0x0000002C)
857 #define CIF_ISP_GAMMA_R_Y3 (CIF_ISP_BASE + 0x00000030)
858 #define CIF_ISP_GAMMA_R_Y4 (CIF_ISP_BASE + 0x00000034)
859 #define CIF_ISP_GAMMA_R_Y5 (CIF_ISP_BASE + 0x00000038)
860 #define CIF_ISP_GAMMA_R_Y6 (CIF_ISP_BASE + 0x0000003C)
861 #define CIF_ISP_GAMMA_R_Y7 (CIF_ISP_BASE + 0x00000040)
862 #define CIF_ISP_GAMMA_R_Y8 (CIF_ISP_BASE + 0x00000044)
863 #define CIF_ISP_GAMMA_R_Y9 (CIF_ISP_BASE + 0x00000048)
864 #define CIF_ISP_GAMMA_R_Y10 (CIF_ISP_BASE + 0x0000004C)
865 #define CIF_ISP_GAMMA_R_Y11 (CIF_ISP_BASE + 0x00000050)
866 #define CIF_ISP_GAMMA_R_Y12 (CIF_ISP_BASE + 0x00000054)
867 #define CIF_ISP_GAMMA_R_Y13 (CIF_ISP_BASE + 0x00000058)
868 #define CIF_ISP_GAMMA_R_Y14 (CIF_ISP_BASE + 0x0000005C)
869 #define CIF_ISP_GAMMA_R_Y15 (CIF_ISP_BASE + 0x00000060)
870 #define CIF_ISP_GAMMA_R_Y16 (CIF_ISP_BASE + 0x00000064)
871 #define CIF_ISP_GAMMA_G_Y0 (CIF_ISP_BASE + 0x00000068)
872 #define CIF_ISP_GAMMA_G_Y1 (CIF_ISP_BASE + 0x0000006C)
873 #define CIF_ISP_GAMMA_G_Y2 (CIF_ISP_BASE + 0x00000070)
874 #define CIF_ISP_GAMMA_G_Y3 (CIF_ISP_BASE + 0x00000074)
875 #define CIF_ISP_GAMMA_G_Y4 (CIF_ISP_BASE + 0x00000078)
876 #define CIF_ISP_GAMMA_G_Y5 (CIF_ISP_BASE + 0x0000007C)
877 #define CIF_ISP_GAMMA_G_Y6 (CIF_ISP_BASE + 0x00000080)
878 #define CIF_ISP_GAMMA_G_Y7 (CIF_ISP_BASE + 0x00000084)
879 #define CIF_ISP_GAMMA_G_Y8 (CIF_ISP_BASE + 0x00000088)
880 #define CIF_ISP_GAMMA_G_Y9 (CIF_ISP_BASE + 0x0000008C)
881 #define CIF_ISP_GAMMA_G_Y10 (CIF_ISP_BASE + 0x00000090)
882 #define CIF_ISP_GAMMA_G_Y11 (CIF_ISP_BASE + 0x00000094)
883 #define CIF_ISP_GAMMA_G_Y12 (CIF_ISP_BASE + 0x00000098)
884 #define CIF_ISP_GAMMA_G_Y13 (CIF_ISP_BASE + 0x0000009C)
885 #define CIF_ISP_GAMMA_G_Y14 (CIF_ISP_BASE + 0x000000A0)
886 #define CIF_ISP_GAMMA_G_Y15 (CIF_ISP_BASE + 0x000000A4)
887 #define CIF_ISP_GAMMA_G_Y16 (CIF_ISP_BASE + 0x000000A8)
888 #define CIF_ISP_GAMMA_B_Y0 (CIF_ISP_BASE + 0x000000AC)
889 #define CIF_ISP_GAMMA_B_Y1 (CIF_ISP_BASE + 0x000000B0)
890 #define CIF_ISP_GAMMA_B_Y2 (CIF_ISP_BASE + 0x000000B4)
891 #define CIF_ISP_GAMMA_B_Y3 (CIF_ISP_BASE + 0x000000B8)
892 #define CIF_ISP_GAMMA_B_Y4 (CIF_ISP_BASE + 0x000000BC)
893 #define CIF_ISP_GAMMA_B_Y5 (CIF_ISP_BASE + 0x000000C0)
894 #define CIF_ISP_GAMMA_B_Y6 (CIF_ISP_BASE + 0x000000C4)
895 #define CIF_ISP_GAMMA_B_Y7 (CIF_ISP_BASE + 0x000000C8)
896 #define CIF_ISP_GAMMA_B_Y8 (CIF_ISP_BASE + 0x000000CC)
897 #define CIF_ISP_GAMMA_B_Y9 (CIF_ISP_BASE + 0x000000D0)
898 #define CIF_ISP_GAMMA_B_Y10 (CIF_ISP_BASE + 0x000000D4)
899 #define CIF_ISP_GAMMA_B_Y11 (CIF_ISP_BASE + 0x000000D8)
900 #define CIF_ISP_GAMMA_B_Y12 (CIF_ISP_BASE + 0x000000DC)
901 #define CIF_ISP_GAMMA_B_Y13 (CIF_ISP_BASE + 0x000000E0)
902 #define CIF_ISP_GAMMA_B_Y14 (CIF_ISP_BASE + 0x000000E4)
903 #define CIF_ISP_GAMMA_B_Y15 (CIF_ISP_BASE + 0x000000E8)
904 #define CIF_ISP_GAMMA_B_Y16 (CIF_ISP_BASE + 0x000000EC)
905
906 #define CIF_ISP_AWB_PROP_V10 (CIF_ISP_BASE + 0x00000110)
907 #define CIF_ISP_AWB_WND_H_OFFS_V10 (CIF_ISP_BASE + 0x00000114)
908 #define CIF_ISP_AWB_WND_V_OFFS_V10 (CIF_ISP_BASE + 0x00000118)
909 #define CIF_ISP_AWB_WND_H_SIZE_V10 (CIF_ISP_BASE + 0x0000011C)
910 #define CIF_ISP_AWB_WND_V_SIZE_V10 (CIF_ISP_BASE + 0x00000120)
911 #define CIF_ISP_AWB_FRAMES_V10 (CIF_ISP_BASE + 0x00000124)
912 #define CIF_ISP_AWB_REF_V10 (CIF_ISP_BASE + 0x00000128)
913 #define CIF_ISP_AWB_THRESH_V10 (CIF_ISP_BASE + 0x0000012C)
914 #define CIF_ISP_AWB_GAIN_G_V10 (CIF_ISP_BASE + 0x00000138)
915 #define CIF_ISP_AWB_GAIN_RB_V10 (CIF_ISP_BASE + 0x0000013C)
916 #define CIF_ISP_AWB_WHITE_CNT_V10 (CIF_ISP_BASE + 0x00000140)
917 #define CIF_ISP_AWB_MEAN_V10 (CIF_ISP_BASE + 0x00000144)
918
919 #define CIF_ISP_AWB_PROP_V12 (CIF_ISP_BASE + 0x00000110)
920 #define CIF_ISP_AWB_SIZE_V12 (CIF_ISP_BASE + 0x00000114)
921 #define CIF_ISP_AWB_OFFS_V12 (CIF_ISP_BASE + 0x00000118)
922 #define CIF_ISP_AWB_REF_V12 (CIF_ISP_BASE + 0x0000011C)
923 #define CIF_ISP_AWB_THRESH_V12 (CIF_ISP_BASE + 0x00000120)
924 #define CIF_ISP_X_COOR12_V12 (CIF_ISP_BASE + 0x00000124)
925 #define CIF_ISP_X_COOR34_V12 (CIF_ISP_BASE + 0x00000128)
926 #define CIF_ISP_AWB_WHITE_CNT_V12 (CIF_ISP_BASE + 0x0000012C)
927 #define CIF_ISP_AWB_MEAN_V12 (CIF_ISP_BASE + 0x00000130)
928 #define CIF_ISP_DEGAIN_V12 (CIF_ISP_BASE + 0x00000134)
929 #define CIF_ISP_AWB_GAIN_G_V12 (CIF_ISP_BASE + 0x00000138)
930 #define CIF_ISP_AWB_GAIN_RB_V12 (CIF_ISP_BASE + 0x0000013C)
931 #define CIF_ISP_REGION_LINE_V12 (CIF_ISP_BASE + 0x00000140)
932 #define CIF_ISP_WP_CNT_REGION0_V12 (CIF_ISP_BASE + 0x00000160)
933 #define CIF_ISP_WP_CNT_REGION1_V12 (CIF_ISP_BASE + 0x00000164)
934 #define CIF_ISP_WP_CNT_REGION2_V12 (CIF_ISP_BASE + 0x00000168)
935 #define CIF_ISP_WP_CNT_REGION3_V12 (CIF_ISP_BASE + 0x0000016C)
936
937 #define CIF_ISP_CC_COEFF_0 (CIF_ISP_BASE + 0x00000170)
938 #define CIF_ISP_CC_COEFF_1 (CIF_ISP_BASE + 0x00000174)
939 #define CIF_ISP_CC_COEFF_2 (CIF_ISP_BASE + 0x00000178)
940 #define CIF_ISP_CC_COEFF_3 (CIF_ISP_BASE + 0x0000017C)
941 #define CIF_ISP_CC_COEFF_4 (CIF_ISP_BASE + 0x00000180)
942 #define CIF_ISP_CC_COEFF_5 (CIF_ISP_BASE + 0x00000184)
943 #define CIF_ISP_CC_COEFF_6 (CIF_ISP_BASE + 0x00000188)
944 #define CIF_ISP_CC_COEFF_7 (CIF_ISP_BASE + 0x0000018C)
945 #define CIF_ISP_CC_COEFF_8 (CIF_ISP_BASE + 0x00000190)
946 #define CIF_ISP_OUT_H_OFFS (CIF_ISP_BASE + 0x00000194)
947 #define CIF_ISP_OUT_V_OFFS (CIF_ISP_BASE + 0x00000198)
948 #define CIF_ISP_OUT_H_SIZE (CIF_ISP_BASE + 0x0000019C)
949 #define CIF_ISP_OUT_V_SIZE (CIF_ISP_BASE + 0x000001A0)
950 #define CIF_ISP_DEMOSAIC (CIF_ISP_BASE + 0x000001A4)
951 #define CIF_ISP_FLAGS_SHD (CIF_ISP_BASE + 0x000001A8)
952 #define CIF_ISP_OUT_H_OFFS_SHD (CIF_ISP_BASE + 0x000001AC)
953 #define CIF_ISP_OUT_V_OFFS_SHD (CIF_ISP_BASE + 0x000001B0)
954 #define CIF_ISP_OUT_H_SIZE_SHD (CIF_ISP_BASE + 0x000001B4)
955 #define CIF_ISP_OUT_V_SIZE_SHD (CIF_ISP_BASE + 0x000001B8)
956 #define CIF_ISP_IMSC (CIF_ISP_BASE + 0x000001BC)
957 #define CIF_ISP_RIS (CIF_ISP_BASE + 0x000001C0)
958 #define CIF_ISP_MIS (CIF_ISP_BASE + 0x000001C4)
959 #define CIF_ISP_ICR (CIF_ISP_BASE + 0x000001C8)
960 #define CIF_ISP_ISR (CIF_ISP_BASE + 0x000001CC)
961 #define CIF_ISP_CT_COEFF_0 (CIF_ISP_BASE + 0x000001D0)
962 #define CIF_ISP_CT_COEFF_1 (CIF_ISP_BASE + 0x000001D4)
963 #define CIF_ISP_CT_COEFF_2 (CIF_ISP_BASE + 0x000001D8)
964 #define CIF_ISP_CT_COEFF_3 (CIF_ISP_BASE + 0x000001DC)
965 #define CIF_ISP_CT_COEFF_4 (CIF_ISP_BASE + 0x000001E0)
966 #define CIF_ISP_CT_COEFF_5 (CIF_ISP_BASE + 0x000001E4)
967 #define CIF_ISP_CT_COEFF_6 (CIF_ISP_BASE + 0x000001E8)
968 #define CIF_ISP_CT_COEFF_7 (CIF_ISP_BASE + 0x000001EC)
969 #define CIF_ISP_CT_COEFF_8 (CIF_ISP_BASE + 0x000001F0)
970 #define CIF_ISP_GAMMA_OUT_MODE_V10 (CIF_ISP_BASE + 0x000001F4)
971 #define CIF_ISP_GAMMA_OUT_Y_0_V10 (CIF_ISP_BASE + 0x000001F8)
972 #define CIF_ISP_GAMMA_OUT_Y_1_V10 (CIF_ISP_BASE + 0x000001FC)
973 #define CIF_ISP_GAMMA_OUT_Y_2_V10 (CIF_ISP_BASE + 0x00000200)
974 #define CIF_ISP_GAMMA_OUT_Y_3_V10 (CIF_ISP_BASE + 0x00000204)
975 #define CIF_ISP_GAMMA_OUT_Y_4_V10 (CIF_ISP_BASE + 0x00000208)
976 #define CIF_ISP_GAMMA_OUT_Y_5_V10 (CIF_ISP_BASE + 0x0000020C)
977 #define CIF_ISP_GAMMA_OUT_Y_6_V10 (CIF_ISP_BASE + 0x00000210)
978 #define CIF_ISP_GAMMA_OUT_Y_7_V10 (CIF_ISP_BASE + 0x00000214)
979 #define CIF_ISP_GAMMA_OUT_Y_8_V10 (CIF_ISP_BASE + 0x00000218)
980 #define CIF_ISP_GAMMA_OUT_Y_9_V10 (CIF_ISP_BASE + 0x0000021C)
981 #define CIF_ISP_GAMMA_OUT_Y_10_V10 (CIF_ISP_BASE + 0x00000220)
982 #define CIF_ISP_GAMMA_OUT_Y_11_V10 (CIF_ISP_BASE + 0x00000224)
983 #define CIF_ISP_GAMMA_OUT_Y_12_V10 (CIF_ISP_BASE + 0x00000228)
984 #define CIF_ISP_GAMMA_OUT_Y_13_V10 (CIF_ISP_BASE + 0x0000022C)
985 #define CIF_ISP_GAMMA_OUT_Y_14_V10 (CIF_ISP_BASE + 0x00000230)
986 #define CIF_ISP_GAMMA_OUT_Y_15_V10 (CIF_ISP_BASE + 0x00000234)
987 #define CIF_ISP_GAMMA_OUT_Y_16_V10 (CIF_ISP_BASE + 0x00000238)
988 #define CIF_ISP_ERR (CIF_ISP_BASE + 0x0000023C)
989 #define CIF_ISP_ERR_CLR (CIF_ISP_BASE + 0x00000240)
990 #define CIF_ISP_FRAME_COUNT (CIF_ISP_BASE + 0x00000244)
991 #define CIF_ISP_CT_OFFSET_R (CIF_ISP_BASE + 0x00000248)
992 #define CIF_ISP_CT_OFFSET_G (CIF_ISP_BASE + 0x0000024C)
993 #define CIF_ISP_CT_OFFSET_B (CIF_ISP_BASE + 0x00000250)
994 #define CIF_ISP_GAMMA_OUT_MODE_V12 (CIF_ISP_BASE + 0x00000300)
995 #define CIF_ISP_GAMMA_OUT_Y_0_V12 (CIF_ISP_BASE + 0x00000304)
996
997 #define CIF_ISP_FLASH_BASE 0x00000660
998 #define CIF_ISP_FLASH_CMD (CIF_ISP_FLASH_BASE + 0x00000000)
999 #define CIF_ISP_FLASH_CONFIG (CIF_ISP_FLASH_BASE + 0x00000004)
1000 #define CIF_ISP_FLASH_PREDIV (CIF_ISP_FLASH_BASE + 0x00000008)
1001 #define CIF_ISP_FLASH_DELAY (CIF_ISP_FLASH_BASE + 0x0000000C)
1002 #define CIF_ISP_FLASH_TIME (CIF_ISP_FLASH_BASE + 0x00000010)
1003 #define CIF_ISP_FLASH_MAXP (CIF_ISP_FLASH_BASE + 0x00000014)
1004
1005 #define CIF_ISP_SH_BASE 0x00000680
1006 #define CIF_ISP_SH_CTRL (CIF_ISP_SH_BASE + 0x00000000)
1007 #define CIF_ISP_SH_PREDIV (CIF_ISP_SH_BASE + 0x00000004)
1008 #define CIF_ISP_SH_DELAY (CIF_ISP_SH_BASE + 0x00000008)
1009 #define CIF_ISP_SH_TIME (CIF_ISP_SH_BASE + 0x0000000C)
1010
1011 #define CIF_C_PROC_BASE 0x00000800
1012 #define CIF_C_PROC_CTRL (CIF_C_PROC_BASE + 0x00000000)
1013 #define CIF_C_PROC_CONTRAST (CIF_C_PROC_BASE + 0x00000004)
1014 #define CIF_C_PROC_BRIGHTNESS (CIF_C_PROC_BASE + 0x00000008)
1015 #define CIF_C_PROC_SATURATION (CIF_C_PROC_BASE + 0x0000000C)
1016 #define CIF_C_PROC_HUE (CIF_C_PROC_BASE + 0x00000010)
1017
1018 #define CIF_DUAL_CROP_BASE 0x00000880
1019 #define CIF_DUAL_CROP_CTRL (CIF_DUAL_CROP_BASE + 0x00000000)
1020 #define CIF_DUAL_CROP_M_H_OFFS (CIF_DUAL_CROP_BASE + 0x00000004)
1021 #define CIF_DUAL_CROP_M_V_OFFS (CIF_DUAL_CROP_BASE + 0x00000008)
1022 #define CIF_DUAL_CROP_M_H_SIZE (CIF_DUAL_CROP_BASE + 0x0000000C)
1023 #define CIF_DUAL_CROP_M_V_SIZE (CIF_DUAL_CROP_BASE + 0x00000010)
1024 #define CIF_DUAL_CROP_S_H_OFFS (CIF_DUAL_CROP_BASE + 0x00000014)
1025 #define CIF_DUAL_CROP_S_V_OFFS (CIF_DUAL_CROP_BASE + 0x00000018)
1026 #define CIF_DUAL_CROP_S_H_SIZE (CIF_DUAL_CROP_BASE + 0x0000001C)
1027 #define CIF_DUAL_CROP_S_V_SIZE (CIF_DUAL_CROP_BASE + 0x00000020)
1028 #define CIF_DUAL_CROP_M_H_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000024)
1029 #define CIF_DUAL_CROP_M_V_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000028)
1030 #define CIF_DUAL_CROP_M_H_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x0000002C)
1031 #define CIF_DUAL_CROP_M_V_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x00000030)
1032 #define CIF_DUAL_CROP_S_H_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000034)
1033 #define CIF_DUAL_CROP_S_V_OFFS_SHD (CIF_DUAL_CROP_BASE + 0x00000038)
1034 #define CIF_DUAL_CROP_S_H_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x0000003C)
1035 #define CIF_DUAL_CROP_S_V_SIZE_SHD (CIF_DUAL_CROP_BASE + 0x00000040)
1036
1037 #define CIF_MRSZ_BASE 0x00000C00
1038 #define CIF_MRSZ_CTRL (CIF_MRSZ_BASE + 0x00000000)
1039 #define CIF_MRSZ_SCALE_HY (CIF_MRSZ_BASE + 0x00000004)
1040 #define CIF_MRSZ_SCALE_HCB (CIF_MRSZ_BASE + 0x00000008)
1041 #define CIF_MRSZ_SCALE_HCR (CIF_MRSZ_BASE + 0x0000000C)
1042 #define CIF_MRSZ_SCALE_VY (CIF_MRSZ_BASE + 0x00000010)
1043 #define CIF_MRSZ_SCALE_VC (CIF_MRSZ_BASE + 0x00000014)
1044 #define CIF_MRSZ_PHASE_HY (CIF_MRSZ_BASE + 0x00000018)
1045 #define CIF_MRSZ_PHASE_HC (CIF_MRSZ_BASE + 0x0000001C)
1046 #define CIF_MRSZ_PHASE_VY (CIF_MRSZ_BASE + 0x00000020)
1047 #define CIF_MRSZ_PHASE_VC (CIF_MRSZ_BASE + 0x00000024)
1048 #define CIF_MRSZ_SCALE_LUT_ADDR (CIF_MRSZ_BASE + 0x00000028)
1049 #define CIF_MRSZ_SCALE_LUT (CIF_MRSZ_BASE + 0x0000002C)
1050 #define CIF_MRSZ_CTRL_SHD (CIF_MRSZ_BASE + 0x00000030)
1051 #define CIF_MRSZ_SCALE_HY_SHD (CIF_MRSZ_BASE + 0x00000034)
1052 #define CIF_MRSZ_SCALE_HCB_SHD (CIF_MRSZ_BASE + 0x00000038)
1053 #define CIF_MRSZ_SCALE_HCR_SHD (CIF_MRSZ_BASE + 0x0000003C)
1054 #define CIF_MRSZ_SCALE_VY_SHD (CIF_MRSZ_BASE + 0x00000040)
1055 #define CIF_MRSZ_SCALE_VC_SHD (CIF_MRSZ_BASE + 0x00000044)
1056 #define CIF_MRSZ_PHASE_HY_SHD (CIF_MRSZ_BASE + 0x00000048)
1057 #define CIF_MRSZ_PHASE_HC_SHD (CIF_MRSZ_BASE + 0x0000004C)
1058 #define CIF_MRSZ_PHASE_VY_SHD (CIF_MRSZ_BASE + 0x00000050)
1059 #define CIF_MRSZ_PHASE_VC_SHD (CIF_MRSZ_BASE + 0x00000054)
1060
1061 #define CIF_SRSZ_BASE 0x00001000
1062 #define CIF_SRSZ_CTRL (CIF_SRSZ_BASE + 0x00000000)
1063 #define CIF_SRSZ_SCALE_HY (CIF_SRSZ_BASE + 0x00000004)
1064 #define CIF_SRSZ_SCALE_HCB (CIF_SRSZ_BASE + 0x00000008)
1065 #define CIF_SRSZ_SCALE_HCR (CIF_SRSZ_BASE + 0x0000000C)
1066 #define CIF_SRSZ_SCALE_VY (CIF_SRSZ_BASE + 0x00000010)
1067 #define CIF_SRSZ_SCALE_VC (CIF_SRSZ_BASE + 0x00000014)
1068 #define CIF_SRSZ_PHASE_HY (CIF_SRSZ_BASE + 0x00000018)
1069 #define CIF_SRSZ_PHASE_HC (CIF_SRSZ_BASE + 0x0000001C)
1070 #define CIF_SRSZ_PHASE_VY (CIF_SRSZ_BASE + 0x00000020)
1071 #define CIF_SRSZ_PHASE_VC (CIF_SRSZ_BASE + 0x00000024)
1072 #define CIF_SRSZ_SCALE_LUT_ADDR (CIF_SRSZ_BASE + 0x00000028)
1073 #define CIF_SRSZ_SCALE_LUT (CIF_SRSZ_BASE + 0x0000002C)
1074 #define CIF_SRSZ_CTRL_SHD (CIF_SRSZ_BASE + 0x00000030)
1075 #define CIF_SRSZ_SCALE_HY_SHD (CIF_SRSZ_BASE + 0x00000034)
1076 #define CIF_SRSZ_SCALE_HCB_SHD (CIF_SRSZ_BASE + 0x00000038)
1077 #define CIF_SRSZ_SCALE_HCR_SHD (CIF_SRSZ_BASE + 0x0000003C)
1078 #define CIF_SRSZ_SCALE_VY_SHD (CIF_SRSZ_BASE + 0x00000040)
1079 #define CIF_SRSZ_SCALE_VC_SHD (CIF_SRSZ_BASE + 0x00000044)
1080 #define CIF_SRSZ_PHASE_HY_SHD (CIF_SRSZ_BASE + 0x00000048)
1081 #define CIF_SRSZ_PHASE_HC_SHD (CIF_SRSZ_BASE + 0x0000004C)
1082 #define CIF_SRSZ_PHASE_VY_SHD (CIF_SRSZ_BASE + 0x00000050)
1083 #define CIF_SRSZ_PHASE_VC_SHD (CIF_SRSZ_BASE + 0x00000054)
1084
1085 #define CIF_MI_BASE 0x00001400
1086 #define CIF_MI_CTRL (CIF_MI_BASE + 0x00000000)
1087 #define CIF_MI_INIT (CIF_MI_BASE + 0x00000004)
1088 #define CIF_MI_MP_Y_BASE_AD_INIT (CIF_MI_BASE + 0x00000008)
1089 #define CIF_MI_MP_Y_SIZE_INIT (CIF_MI_BASE + 0x0000000C)
1090 #define CIF_MI_MP_Y_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000010)
1091 #define CIF_MI_MP_Y_OFFS_CNT_START (CIF_MI_BASE + 0x00000014)
1092 #define CIF_MI_MP_Y_IRQ_OFFS_INIT (CIF_MI_BASE + 0x00000018)
1093 #define CIF_MI_MP_CB_BASE_AD_INIT (CIF_MI_BASE + 0x0000001C)
1094 #define CIF_MI_MP_CB_SIZE_INIT (CIF_MI_BASE + 0x00000020)
1095 #define CIF_MI_MP_CB_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000024)
1096 #define CIF_MI_MP_CB_OFFS_CNT_START (CIF_MI_BASE + 0x00000028)
1097 #define CIF_MI_MP_CR_BASE_AD_INIT (CIF_MI_BASE + 0x0000002C)
1098 #define CIF_MI_MP_CR_SIZE_INIT (CIF_MI_BASE + 0x00000030)
1099 #define CIF_MI_MP_CR_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000034)
1100 #define CIF_MI_MP_CR_OFFS_CNT_START (CIF_MI_BASE + 0x00000038)
1101 #define CIF_MI_SP_Y_BASE_AD_INIT (CIF_MI_BASE + 0x0000003C)
1102 #define CIF_MI_SP_Y_SIZE_INIT (CIF_MI_BASE + 0x00000040)
1103 #define CIF_MI_SP_Y_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000044)
1104 #define CIF_MI_SP_Y_OFFS_CNT_START (CIF_MI_BASE + 0x00000048)
1105 #define CIF_MI_SP_Y_LLENGTH (CIF_MI_BASE + 0x0000004C)
1106 #define CIF_MI_SP_CB_BASE_AD_INIT (CIF_MI_BASE + 0x00000050)
1107 #define CIF_MI_SP_CB_SIZE_INIT (CIF_MI_BASE + 0x00000054)
1108 #define CIF_MI_SP_CB_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000058)
1109 #define CIF_MI_SP_CB_OFFS_CNT_START (CIF_MI_BASE + 0x0000005C)
1110 #define CIF_MI_SP_CR_BASE_AD_INIT (CIF_MI_BASE + 0x00000060)
1111 #define CIF_MI_SP_CR_SIZE_INIT (CIF_MI_BASE + 0x00000064)
1112 #define CIF_MI_SP_CR_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000068)
1113 #define CIF_MI_SP_CR_OFFS_CNT_START (CIF_MI_BASE + 0x0000006C)
1114 #define CIF_MI_BYTE_CNT (CIF_MI_BASE + 0x00000070)
1115 #define CIF_MI_CTRL_SHD (CIF_MI_BASE + 0x00000074)
1116 #define CIF_MI_MP_Y_BASE_AD_SHD (CIF_MI_BASE + 0x00000078)
1117 #define CIF_MI_MP_Y_SIZE_SHD (CIF_MI_BASE + 0x0000007C)
1118 #define CIF_MI_MP_Y_OFFS_CNT_SHD (CIF_MI_BASE + 0x00000080)
1119 #define CIF_MI_MP_Y_IRQ_OFFS_SHD (CIF_MI_BASE + 0x00000084)
1120 #define CIF_MI_MP_CB_BASE_AD_SHD (CIF_MI_BASE + 0x00000088)
1121 #define CIF_MI_MP_CB_SIZE_SHD (CIF_MI_BASE + 0x0000008C)
1122 #define CIF_MI_MP_CB_OFFS_CNT_SHD (CIF_MI_BASE + 0x00000090)
1123 #define CIF_MI_MP_CR_BASE_AD_SHD (CIF_MI_BASE + 0x00000094)
1124 #define CIF_MI_MP_CR_SIZE_SHD (CIF_MI_BASE + 0x00000098)
1125 #define CIF_MI_MP_CR_OFFS_CNT_SHD (CIF_MI_BASE + 0x0000009C)
1126 #define CIF_MI_SP_Y_BASE_AD_SHD (CIF_MI_BASE + 0x000000A0)
1127 #define CIF_MI_SP_Y_SIZE_SHD (CIF_MI_BASE + 0x000000A4)
1128 #define CIF_MI_SP_Y_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000A8)
1129 #define CIF_MI_SP_CB_BASE_AD_SHD (CIF_MI_BASE + 0x000000B0)
1130 #define CIF_MI_SP_CB_SIZE_SHD (CIF_MI_BASE + 0x000000B4)
1131 #define CIF_MI_SP_CB_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000B8)
1132 #define CIF_MI_SP_CR_BASE_AD_SHD (CIF_MI_BASE + 0x000000BC)
1133 #define CIF_MI_SP_CR_SIZE_SHD (CIF_MI_BASE + 0x000000C0)
1134 #define CIF_MI_SP_CR_OFFS_CNT_SHD (CIF_MI_BASE + 0x000000C4)
1135 #define CIF_MI_DMA_Y_PIC_START_AD (CIF_MI_BASE + 0x000000C8)
1136 #define CIF_MI_DMA_Y_PIC_WIDTH (CIF_MI_BASE + 0x000000CC)
1137 #define CIF_MI_DMA_Y_LLENGTH (CIF_MI_BASE + 0x000000D0)
1138 #define CIF_MI_DMA_Y_PIC_SIZE (CIF_MI_BASE + 0x000000D4)
1139 #define CIF_MI_DMA_CB_PIC_START_AD (CIF_MI_BASE + 0x000000D8)
1140 #define CIF_MI_DMA_CR_PIC_START_AD (CIF_MI_BASE + 0x000000E8)
1141 #define CIF_MI_IMSC (CIF_MI_BASE + 0x000000F8)
1142 #define CIF_MI_RIS (CIF_MI_BASE + 0x000000FC)
1143 #define CIF_MI_MIS (CIF_MI_BASE + 0x00000100)
1144 #define CIF_MI_ICR (CIF_MI_BASE + 0x00000104)
1145 #define CIF_MI_ISR (CIF_MI_BASE + 0x00000108)
1146 #define CIF_MI_STATUS (CIF_MI_BASE + 0x0000010C)
1147 #define CIF_MI_STATUS_CLR (CIF_MI_BASE + 0x00000110)
1148 #define CIF_MI_SP_Y_PIC_WIDTH (CIF_MI_BASE + 0x00000114)
1149 #define CIF_MI_SP_Y_PIC_HEIGHT (CIF_MI_BASE + 0x00000118)
1150 #define CIF_MI_SP_Y_PIC_SIZE (CIF_MI_BASE + 0x0000011C)
1151 #define CIF_MI_DMA_CTRL (CIF_MI_BASE + 0x00000120)
1152 #define CIF_MI_DMA_START (CIF_MI_BASE + 0x00000124)
1153 #define CIF_MI_DMA_STATUS (CIF_MI_BASE + 0x00000128)
1154 #define CIF_MI_PIXEL_COUNT (CIF_MI_BASE + 0x0000012C)
1155 #define CIF_MI_MP_Y_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000130)
1156 #define CIF_MI_MP_CB_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000134)
1157 #define CIF_MI_MP_CR_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000138)
1158 #define CIF_MI_SP_Y_BASE_AD_INIT2 (CIF_MI_BASE + 0x0000013C)
1159 #define CIF_MI_SP_CB_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000140)
1160 #define CIF_MI_SP_CR_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000144)
1161 #define CIF_MI_XTD_FORMAT_CTRL (CIF_MI_BASE + 0x00000148)
1162 #define CIF_MI_CTRL2 (CIF_MI_BASE + 0x00000150)
1163 #define CIF_MI_RAW0_BASE_AD_INIT (CIF_MI_BASE + 0x00000160)
1164 #define CIF_MI_RAW0_BASE_AD_INIT2 (CIF_MI_BASE + 0x00000164)
1165 #define CIF_MI_RAW0_IRQ_OFFS_INIT (CIF_MI_BASE + 0x00000168)
1166 #define CIF_MI_RAW0_SIZE_INIT (CIF_MI_BASE + 0x0000016c)
1167 #define CIF_MI_RAW0_OFFS_CNT_INIT (CIF_MI_BASE + 0x00000170)
1168 #define CIF_MI_RAW0_LENGTH (CIF_MI_BASE + 0x00000174)
1169 #define CIF_MI_RAW0_OFFS_CNT_START_SHD (CIF_MI_BASE + 0x00000178)
1170 #define CIF_MI_RAW0_BASE_AS_SHD (CIF_MI_BASE + 0x00000180)
1171 #define CIF_MI_RAW0_IRQ_OFFS_INI_SHD (CIF_MI_BASE + 0x00000184)
1172 #define CIF_MI_RAW0_SIZE_INIT_SHD (CIF_MI_BASE + 0x00000188)
1173 #define CIF_MI_RAW0_OFFS_CNT_INIT_SHD (CIF_MI_BASE + 0x0000018c)
1174
1175 #define CIF_SMIA_BASE 0x00001A00
1176 #define CIF_SMIA_CTRL (CIF_SMIA_BASE + 0x00000000)
1177 #define CIF_SMIA_STATUS (CIF_SMIA_BASE + 0x00000004)
1178 #define CIF_SMIA_IMSC (CIF_SMIA_BASE + 0x00000008)
1179 #define CIF_SMIA_RIS (CIF_SMIA_BASE + 0x0000000C)
1180 #define CIF_SMIA_MIS (CIF_SMIA_BASE + 0x00000010)
1181 #define CIF_SMIA_ICR (CIF_SMIA_BASE + 0x00000014)
1182 #define CIF_SMIA_ISR (CIF_SMIA_BASE + 0x00000018)
1183 #define CIF_SMIA_DATA_FORMAT_SEL (CIF_SMIA_BASE + 0x0000001C)
1184 #define CIF_SMIA_SOF_EMB_DATA_LINES (CIF_SMIA_BASE + 0x00000020)
1185 #define CIF_SMIA_EMB_HSTART (CIF_SMIA_BASE + 0x00000024)
1186 #define CIF_SMIA_EMB_HSIZE (CIF_SMIA_BASE + 0x00000028)
1187 #define CIF_SMIA_EMB_VSTART (CIF_SMIA_BASE + 0x0000002c)
1188 #define CIF_SMIA_NUM_LINES (CIF_SMIA_BASE + 0x00000030)
1189 #define CIF_SMIA_EMB_DATA_FIFO (CIF_SMIA_BASE + 0x00000034)
1190 #define CIF_SMIA_EMB_DATA_WATERMARK (CIF_SMIA_BASE + 0x00000038)
1191
1192 #define CIF_MIPI_BASE 0x00001C00
1193 #define CIF_MIPI_CTRL (CIF_MIPI_BASE + 0x00000000)
1194 #define CIF_MIPI_STATUS (CIF_MIPI_BASE + 0x00000004)
1195 #define CIF_MIPI_IMSC (CIF_MIPI_BASE + 0x00000008)
1196 #define CIF_MIPI_RIS (CIF_MIPI_BASE + 0x0000000C)
1197 #define CIF_MIPI_MIS (CIF_MIPI_BASE + 0x00000010)
1198 #define CIF_MIPI_ICR (CIF_MIPI_BASE + 0x00000014)
1199 #define CIF_MIPI_ISR (CIF_MIPI_BASE + 0x00000018)
1200 #define CIF_MIPI_CUR_DATA_ID (CIF_MIPI_BASE + 0x0000001C)
1201 #define CIF_MIPI_IMG_DATA_SEL (CIF_MIPI_BASE + 0x00000020)
1202 #define CIF_MIPI_ADD_DATA_SEL_1 (CIF_MIPI_BASE + 0x00000024)
1203 #define CIF_MIPI_ADD_DATA_SEL_2 (CIF_MIPI_BASE + 0x00000028)
1204 #define CIF_MIPI_ADD_DATA_SEL_3 (CIF_MIPI_BASE + 0x0000002C)
1205 #define CIF_MIPI_ADD_DATA_SEL_4 (CIF_MIPI_BASE + 0x00000030)
1206 #define CIF_MIPI_ADD_DATA_FIFO (CIF_MIPI_BASE + 0x00000034)
1207 #define CIF_MIPI_FIFO_FILL_LEVEL (CIF_MIPI_BASE + 0x00000038)
1208 #define CIF_MIPI_COMPRESSED_MODE (CIF_MIPI_BASE + 0x0000003C)
1209 #define CIF_MIPI_FRAME (CIF_MIPI_BASE + 0x00000040)
1210 #define CIF_MIPI_GEN_SHORT_DT (CIF_MIPI_BASE + 0x00000044)
1211 #define CIF_MIPI_GEN_SHORT_8_9 (CIF_MIPI_BASE + 0x00000048)
1212 #define CIF_MIPI_GEN_SHORT_A_B (CIF_MIPI_BASE + 0x0000004C)
1213 #define CIF_MIPI_GEN_SHORT_C_D (CIF_MIPI_BASE + 0x00000050)
1214 #define CIF_MIPI_GEN_SHORT_E_F (CIF_MIPI_BASE + 0x00000054)
1215
1216 #define CIF_ISP_AFM_BASE 0x00002000
1217 #define CIF_ISP_AFM_CTRL (CIF_ISP_AFM_BASE + 0x00000000)
1218 #define CIF_ISP_AFM_LT_A (CIF_ISP_AFM_BASE + 0x00000004)
1219 #define CIF_ISP_AFM_RB_A (CIF_ISP_AFM_BASE + 0x00000008)
1220 #define CIF_ISP_AFM_LT_B (CIF_ISP_AFM_BASE + 0x0000000C)
1221 #define CIF_ISP_AFM_RB_B (CIF_ISP_AFM_BASE + 0x00000010)
1222 #define CIF_ISP_AFM_LT_C (CIF_ISP_AFM_BASE + 0x00000014)
1223 #define CIF_ISP_AFM_RB_C (CIF_ISP_AFM_BASE + 0x00000018)
1224 #define CIF_ISP_AFM_THRES (CIF_ISP_AFM_BASE + 0x0000001C)
1225 #define CIF_ISP_AFM_VAR_SHIFT (CIF_ISP_AFM_BASE + 0x00000020)
1226 #define CIF_ISP_AFM_SUM_A (CIF_ISP_AFM_BASE + 0x00000024)
1227 #define CIF_ISP_AFM_SUM_B (CIF_ISP_AFM_BASE + 0x00000028)
1228 #define CIF_ISP_AFM_SUM_C (CIF_ISP_AFM_BASE + 0x0000002C)
1229 #define CIF_ISP_AFM_LUM_A (CIF_ISP_AFM_BASE + 0x00000030)
1230 #define CIF_ISP_AFM_LUM_B (CIF_ISP_AFM_BASE + 0x00000034)
1231 #define CIF_ISP_AFM_LUM_C (CIF_ISP_AFM_BASE + 0x00000038)
1232
1233 #define CIF_ISP_LSC_BASE 0x00002200
1234 #define CIF_ISP_LSC_CTRL (CIF_ISP_LSC_BASE + 0x00000000)
1235 #define CIF_ISP_LSC_R_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000004)
1236 #define CIF_ISP_LSC_GR_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000008)
1237 #define CIF_ISP_LSC_B_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x0000000C)
1238 #define CIF_ISP_LSC_GB_TABLE_ADDR (CIF_ISP_LSC_BASE + 0x00000010)
1239 #define CIF_ISP_LSC_R_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000014)
1240 #define CIF_ISP_LSC_GR_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000018)
1241 #define CIF_ISP_LSC_B_TABLE_DATA (CIF_ISP_LSC_BASE + 0x0000001C)
1242 #define CIF_ISP_LSC_GB_TABLE_DATA (CIF_ISP_LSC_BASE + 0x00000020)
1243 #define CIF_ISP_LSC_XGRAD_01 (CIF_ISP_LSC_BASE + 0x00000024)
1244 #define CIF_ISP_LSC_XGRAD_23 (CIF_ISP_LSC_BASE + 0x00000028)
1245 #define CIF_ISP_LSC_XGRAD_45 (CIF_ISP_LSC_BASE + 0x0000002C)
1246 #define CIF_ISP_LSC_XGRAD_67 (CIF_ISP_LSC_BASE + 0x00000030)
1247 #define CIF_ISP_LSC_YGRAD_01 (CIF_ISP_LSC_BASE + 0x00000034)
1248 #define CIF_ISP_LSC_YGRAD_23 (CIF_ISP_LSC_BASE + 0x00000038)
1249 #define CIF_ISP_LSC_YGRAD_45 (CIF_ISP_LSC_BASE + 0x0000003C)
1250 #define CIF_ISP_LSC_YGRAD_67 (CIF_ISP_LSC_BASE + 0x00000040)
1251 #define CIF_ISP_LSC_XSIZE_01 (CIF_ISP_LSC_BASE + 0x00000044)
1252 #define CIF_ISP_LSC_XSIZE_23 (CIF_ISP_LSC_BASE + 0x00000048)
1253 #define CIF_ISP_LSC_XSIZE_45 (CIF_ISP_LSC_BASE + 0x0000004C)
1254 #define CIF_ISP_LSC_XSIZE_67 (CIF_ISP_LSC_BASE + 0x00000050)
1255 #define CIF_ISP_LSC_YSIZE_01 (CIF_ISP_LSC_BASE + 0x00000054)
1256 #define CIF_ISP_LSC_YSIZE_23 (CIF_ISP_LSC_BASE + 0x00000058)
1257 #define CIF_ISP_LSC_YSIZE_45 (CIF_ISP_LSC_BASE + 0x0000005C)
1258 #define CIF_ISP_LSC_YSIZE_67 (CIF_ISP_LSC_BASE + 0x00000060)
1259 #define CIF_ISP_LSC_TABLE_SEL (CIF_ISP_LSC_BASE + 0x00000064)
1260 #define CIF_ISP_LSC_STATUS (CIF_ISP_LSC_BASE + 0x00000068)
1261
1262 #define CIF_ISP_IS_BASE 0x00002300
1263 #define CIF_ISP_IS_CTRL (CIF_ISP_IS_BASE + 0x00000000)
1264 #define CIF_ISP_IS_RECENTER (CIF_ISP_IS_BASE + 0x00000004)
1265 #define CIF_ISP_IS_H_OFFS (CIF_ISP_IS_BASE + 0x00000008)
1266 #define CIF_ISP_IS_V_OFFS (CIF_ISP_IS_BASE + 0x0000000C)
1267 #define CIF_ISP_IS_H_SIZE (CIF_ISP_IS_BASE + 0x00000010)
1268 #define CIF_ISP_IS_V_SIZE (CIF_ISP_IS_BASE + 0x00000014)
1269 #define CIF_ISP_IS_MAX_DX (CIF_ISP_IS_BASE + 0x00000018)
1270 #define CIF_ISP_IS_MAX_DY (CIF_ISP_IS_BASE + 0x0000001C)
1271 #define CIF_ISP_IS_DISPLACE (CIF_ISP_IS_BASE + 0x00000020)
1272 #define CIF_ISP_IS_H_OFFS_SHD (CIF_ISP_IS_BASE + 0x00000024)
1273 #define CIF_ISP_IS_V_OFFS_SHD (CIF_ISP_IS_BASE + 0x00000028)
1274 #define CIF_ISP_IS_H_SIZE_SHD (CIF_ISP_IS_BASE + 0x0000002C)
1275 #define CIF_ISP_IS_V_SIZE_SHD (CIF_ISP_IS_BASE + 0x00000030)
1276
1277 #define CIF_ISP_HIST_BASE_V10 0x00002400
1278 #define CIF_ISP_HIST_PROP_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000000)
1279 #define CIF_ISP_HIST_H_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000004)
1280 #define CIF_ISP_HIST_V_OFFS_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000008)
1281 #define CIF_ISP_HIST_H_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000000C)
1282 #define CIF_ISP_HIST_V_SIZE_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000010)
1283 #define CIF_ISP_HIST_BIN_0_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000014)
1284 #define CIF_ISP_HIST_BIN_1_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000018)
1285 #define CIF_ISP_HIST_BIN_2_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000001C)
1286 #define CIF_ISP_HIST_BIN_3_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000020)
1287 #define CIF_ISP_HIST_BIN_4_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000024)
1288 #define CIF_ISP_HIST_BIN_5_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000028)
1289 #define CIF_ISP_HIST_BIN_6_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000002C)
1290 #define CIF_ISP_HIST_BIN_7_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000030)
1291 #define CIF_ISP_HIST_BIN_8_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000034)
1292 #define CIF_ISP_HIST_BIN_9_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000038)
1293 #define CIF_ISP_HIST_BIN_10_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000003C)
1294 #define CIF_ISP_HIST_BIN_11_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000040)
1295 #define CIF_ISP_HIST_BIN_12_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000044)
1296 #define CIF_ISP_HIST_BIN_13_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000048)
1297 #define CIF_ISP_HIST_BIN_14_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000004C)
1298 #define CIF_ISP_HIST_BIN_15_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000050)
1299 #define CIF_ISP_HIST_WEIGHT_00TO30_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000054)
1300 #define CIF_ISP_HIST_WEIGHT_40TO21_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000058)
1301 #define CIF_ISP_HIST_WEIGHT_31TO12_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000005C)
1302 #define CIF_ISP_HIST_WEIGHT_22TO03_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000060)
1303 #define CIF_ISP_HIST_WEIGHT_13TO43_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000064)
1304 #define CIF_ISP_HIST_WEIGHT_04TO34_V10 (CIF_ISP_HIST_BASE_V10 + 0x00000068)
1305 #define CIF_ISP_HIST_WEIGHT_44_V10 (CIF_ISP_HIST_BASE_V10 + 0x0000006C)
1306
1307 #define CIF_ISP_FILT_BASE 0x00002500
1308 #define CIF_ISP_FILT_MODE (CIF_ISP_FILT_BASE + 0x00000000)
1309 #define CIF_ISP_FILT_THRESH_BL0 (CIF_ISP_FILT_BASE + 0x00000028)
1310 #define CIF_ISP_FILT_THRESH_BL1 (CIF_ISP_FILT_BASE + 0x0000002c)
1311 #define CIF_ISP_FILT_THRESH_SH0 (CIF_ISP_FILT_BASE + 0x00000030)
1312 #define CIF_ISP_FILT_THRESH_SH1 (CIF_ISP_FILT_BASE + 0x00000034)
1313 #define CIF_ISP_FILT_LUM_WEIGHT (CIF_ISP_FILT_BASE + 0x00000038)
1314 #define CIF_ISP_FILT_FAC_SH1 (CIF_ISP_FILT_BASE + 0x0000003c)
1315 #define CIF_ISP_FILT_FAC_SH0 (CIF_ISP_FILT_BASE + 0x00000040)
1316 #define CIF_ISP_FILT_FAC_MID (CIF_ISP_FILT_BASE + 0x00000044)
1317 #define CIF_ISP_FILT_FAC_BL0 (CIF_ISP_FILT_BASE + 0x00000048)
1318 #define CIF_ISP_FILT_FAC_BL1 (CIF_ISP_FILT_BASE + 0x0000004C)
1319 #define CIF_ISP_FILT_ISP_CAC_CTRL (CIF_ISP_FILT_BASE + 0x00000080)
1320 #define CIF_ISP_FILT_CAC_COUNT_START (CIF_ISP_FILT_BASE + 0x00000084)
1321 #define CIF_ISP_FILT_CAC_A (CIF_ISP_FILT_BASE + 0x00000088)
1322 #define CIF_ISP_FILT_CAC_B (CIF_ISP_FILT_BASE + 0x0000008c)
1323 #define CIF_ISP_FILT_CAC_C (CIF_ISP_FILT_BASE + 0x00000090)
1324 #define CIF_ISP_FILT_CAC_X_NORM (CIF_ISP_FILT_BASE + 0x00000094)
1325 #define CIF_ISP_FILT_CAC_Y_NORM (CIF_ISP_FILT_BASE + 0x00000098)
1326 #define CIF_ISP_FILT_LU_DIVID (CIF_ISP_FILT_BASE + 0x000000a0)
1327 #define CIF_ISP_FILT_THGRAD_DIVID0123 (CIF_ISP_FILT_BASE + 0x000000a4)
1328 #define CIF_ISP_FILT_THGRAD_DIVID4 (CIF_ISP_FILT_BASE + 0x000000a8)
1329 #define CIF_ISP_FILT_THDIFF_DIVID0123 (CIF_ISP_FILT_BASE + 0x000000ac)
1330 #define CIF_ISP_FILT_THDIFF_DIVID4 (CIF_ISP_FILT_BASE + 0x000000b0)
1331 #define CIF_ISP_FILT_THCSC_DIVID0123 (CIF_ISP_FILT_BASE + 0x000000b4)
1332 #define CIF_ISP_FILT_THCSC_DIVID4 (CIF_ISP_FILT_BASE + 0x000000b8)
1333 #define CIF_ISP_FILT_THVAR_DIVID01 (CIF_ISP_FILT_BASE + 0x000000bc)
1334 #define CIF_ISP_FILT_THVAR_DIVID23 (CIF_ISP_FILT_BASE + 0x000000c0)
1335 #define CIF_ISP_FILT_THVAR_DIVID4 (CIF_ISP_FILT_BASE + 0x000000c4)
1336 #define CIF_ISP_FILT_TH_GRAD (CIF_ISP_FILT_BASE + 0x000000c8)
1337 #define CIF_ISP_FILT_TH_DIFF (CIF_ISP_FILT_BASE + 0x000000cc)
1338 #define CIF_ISP_FILT_TH_CSC (CIF_ISP_FILT_BASE + 0x000000d0)
1339 #define CIF_ISP_FILT_TH_VAR (CIF_ISP_FILT_BASE + 0x000000d4)
1340 #define CIF_ISP_FILT_LELEL_SEL (CIF_ISP_FILT_BASE + 0x000000d8)
1341 #define CIF_ISP_FILT_R_FCT (CIF_ISP_FILT_BASE + 0x000000dc)
1342 #define CIF_ISP_FILT_B_FCT (CIF_ISP_FILT_BASE + 0x000000e0)
1343
1344 #define CIF_ISP_CAC_BASE 0x00002580
1345 #define CIF_ISP_CAC_CTRL (CIF_ISP_CAC_BASE + 0x00000000)
1346 #define CIF_ISP_CAC_COUNT_START (CIF_ISP_CAC_BASE + 0x00000004)
1347 #define CIF_ISP_CAC_A (CIF_ISP_CAC_BASE + 0x00000008)
1348 #define CIF_ISP_CAC_B (CIF_ISP_CAC_BASE + 0x0000000C)
1349 #define CIF_ISP_CAC_C (CIF_ISP_CAC_BASE + 0x00000010)
1350 #define CIF_ISP_X_NORM (CIF_ISP_CAC_BASE + 0x00000014)
1351 #define CIF_ISP_Y_NORM (CIF_ISP_CAC_BASE + 0x00000018)
1352
1353 #define CIF_ISP_EXP_BASE 0x00002600
1354 #define CIF_ISP_EXP_CTRL (CIF_ISP_EXP_BASE + 0x00000000)
1355 #define CIF_ISP_EXP_H_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000004)
1356 #define CIF_ISP_EXP_V_OFFSET_V10 (CIF_ISP_EXP_BASE + 0x00000008)
1357 #define CIF_ISP_EXP_H_SIZE_V10 (CIF_ISP_EXP_BASE + 0x0000000C)
1358 #define CIF_ISP_EXP_V_SIZE_V10 (CIF_ISP_EXP_BASE + 0x00000010)
1359 #define CIF_ISP_EXP_SIZE_V12 (CIF_ISP_EXP_BASE + 0x00000004)
1360 #define CIF_ISP_EXP_OFFS_V12 (CIF_ISP_EXP_BASE + 0x00000008)
1361 #define CIF_ISP_EXP_MEAN_V12 (CIF_ISP_EXP_BASE + 0x0000000c)
1362 #define CIF_ISP_EXP_MEAN_00_V10 (CIF_ISP_EXP_BASE + 0x00000014)
1363 #define CIF_ISP_EXP_MEAN_10_V10 (CIF_ISP_EXP_BASE + 0x00000018)
1364 #define CIF_ISP_EXP_MEAN_20_V10 (CIF_ISP_EXP_BASE + 0x0000001c)
1365 #define CIF_ISP_EXP_MEAN_30_V10 (CIF_ISP_EXP_BASE + 0x00000020)
1366 #define CIF_ISP_EXP_MEAN_40_V10 (CIF_ISP_EXP_BASE + 0x00000024)
1367 #define CIF_ISP_EXP_MEAN_01_V10 (CIF_ISP_EXP_BASE + 0x00000028)
1368 #define CIF_ISP_EXP_MEAN_11_V10 (CIF_ISP_EXP_BASE + 0x0000002c)
1369 #define CIF_ISP_EXP_MEAN_21_V10 (CIF_ISP_EXP_BASE + 0x00000030)
1370 #define CIF_ISP_EXP_MEAN_31_V10 (CIF_ISP_EXP_BASE + 0x00000034)
1371 #define CIF_ISP_EXP_MEAN_41_V10 (CIF_ISP_EXP_BASE + 0x00000038)
1372 #define CIF_ISP_EXP_MEAN_02_V10 (CIF_ISP_EXP_BASE + 0x0000003c)
1373 #define CIF_ISP_EXP_MEAN_12_V10 (CIF_ISP_EXP_BASE + 0x00000040)
1374 #define CIF_ISP_EXP_MEAN_22_V10 (CIF_ISP_EXP_BASE + 0x00000044)
1375 #define CIF_ISP_EXP_MEAN_32_V10 (CIF_ISP_EXP_BASE + 0x00000048)
1376 #define CIF_ISP_EXP_MEAN_42_V10 (CIF_ISP_EXP_BASE + 0x0000004c)
1377 #define CIF_ISP_EXP_MEAN_03_V10 (CIF_ISP_EXP_BASE + 0x00000050)
1378 #define CIF_ISP_EXP_MEAN_13_V10 (CIF_ISP_EXP_BASE + 0x00000054)
1379 #define CIF_ISP_EXP_MEAN_23_V10 (CIF_ISP_EXP_BASE + 0x00000058)
1380 #define CIF_ISP_EXP_MEAN_33_V10 (CIF_ISP_EXP_BASE + 0x0000005c)
1381 #define CIF_ISP_EXP_MEAN_43_V10 (CIF_ISP_EXP_BASE + 0x00000060)
1382 #define CIF_ISP_EXP_MEAN_04_V10 (CIF_ISP_EXP_BASE + 0x00000064)
1383 #define CIF_ISP_EXP_MEAN_14_V10 (CIF_ISP_EXP_BASE + 0x00000068)
1384 #define CIF_ISP_EXP_MEAN_24_V10 (CIF_ISP_EXP_BASE + 0x0000006c)
1385 #define CIF_ISP_EXP_MEAN_34_V10 (CIF_ISP_EXP_BASE + 0x00000070)
1386 #define CIF_ISP_EXP_MEAN_44_V10 (CIF_ISP_EXP_BASE + 0x00000074)
1387
1388 #define CIF_ISP_BLS_BASE 0x00002700
1389 #define CIF_ISP_BLS_CTRL (CIF_ISP_BLS_BASE + 0x00000000)
1390 #define CIF_ISP_BLS_SAMPLES (CIF_ISP_BLS_BASE + 0x00000004)
1391 #define CIF_ISP_BLS_H1_START (CIF_ISP_BLS_BASE + 0x00000008)
1392 #define CIF_ISP_BLS_H1_STOP (CIF_ISP_BLS_BASE + 0x0000000c)
1393 #define CIF_ISP_BLS_V1_START (CIF_ISP_BLS_BASE + 0x00000010)
1394 #define CIF_ISP_BLS_V1_STOP (CIF_ISP_BLS_BASE + 0x00000014)
1395 #define CIF_ISP_BLS_H2_START (CIF_ISP_BLS_BASE + 0x00000018)
1396 #define CIF_ISP_BLS_H2_STOP (CIF_ISP_BLS_BASE + 0x0000001c)
1397 #define CIF_ISP_BLS_V2_START (CIF_ISP_BLS_BASE + 0x00000020)
1398 #define CIF_ISP_BLS_V2_STOP (CIF_ISP_BLS_BASE + 0x00000024)
1399 #define CIF_ISP_BLS_A_FIXED (CIF_ISP_BLS_BASE + 0x00000028)
1400 #define CIF_ISP_BLS_B_FIXED (CIF_ISP_BLS_BASE + 0x0000002c)
1401 #define CIF_ISP_BLS_C_FIXED (CIF_ISP_BLS_BASE + 0x00000030)
1402 #define CIF_ISP_BLS_D_FIXED (CIF_ISP_BLS_BASE + 0x00000034)
1403 #define CIF_ISP_BLS_A_MEASURED (CIF_ISP_BLS_BASE + 0x00000038)
1404 #define CIF_ISP_BLS_B_MEASURED (CIF_ISP_BLS_BASE + 0x0000003c)
1405 #define CIF_ISP_BLS_C_MEASURED (CIF_ISP_BLS_BASE + 0x00000040)
1406 #define CIF_ISP_BLS_D_MEASURED (CIF_ISP_BLS_BASE + 0x00000044)
1407
1408 #define CIF_ISP_DPF_BASE 0x00002800
1409 #define CIF_ISP_DPF_MODE (CIF_ISP_DPF_BASE + 0x00000000)
1410 #define CIF_ISP_DPF_STRENGTH_R (CIF_ISP_DPF_BASE + 0x00000004)
1411 #define CIF_ISP_DPF_STRENGTH_G (CIF_ISP_DPF_BASE + 0x00000008)
1412 #define CIF_ISP_DPF_STRENGTH_B (CIF_ISP_DPF_BASE + 0x0000000C)
1413 #define CIF_ISP_DPF_S_WEIGHT_G_1_4 (CIF_ISP_DPF_BASE + 0x00000010)
1414 #define CIF_ISP_DPF_S_WEIGHT_G_5_6 (CIF_ISP_DPF_BASE + 0x00000014)
1415 #define CIF_ISP_DPF_S_WEIGHT_RB_1_4 (CIF_ISP_DPF_BASE + 0x00000018)
1416 #define CIF_ISP_DPF_S_WEIGHT_RB_5_6 (CIF_ISP_DPF_BASE + 0x0000001C)
1417 #define CIF_ISP_DPF_NULL_COEFF_0 (CIF_ISP_DPF_BASE + 0x00000020)
1418 #define CIF_ISP_DPF_NULL_COEFF_1 (CIF_ISP_DPF_BASE + 0x00000024)
1419 #define CIF_ISP_DPF_NULL_COEFF_2 (CIF_ISP_DPF_BASE + 0x00000028)
1420 #define CIF_ISP_DPF_NULL_COEFF_3 (CIF_ISP_DPF_BASE + 0x0000002C)
1421 #define CIF_ISP_DPF_NULL_COEFF_4 (CIF_ISP_DPF_BASE + 0x00000030)
1422 #define CIF_ISP_DPF_NULL_COEFF_5 (CIF_ISP_DPF_BASE + 0x00000034)
1423 #define CIF_ISP_DPF_NULL_COEFF_6 (CIF_ISP_DPF_BASE + 0x00000038)
1424 #define CIF_ISP_DPF_NULL_COEFF_7 (CIF_ISP_DPF_BASE + 0x0000003C)
1425 #define CIF_ISP_DPF_NULL_COEFF_8 (CIF_ISP_DPF_BASE + 0x00000040)
1426 #define CIF_ISP_DPF_NULL_COEFF_9 (CIF_ISP_DPF_BASE + 0x00000044)
1427 #define CIF_ISP_DPF_NULL_COEFF_10 (CIF_ISP_DPF_BASE + 0x00000048)
1428 #define CIF_ISP_DPF_NULL_COEFF_11 (CIF_ISP_DPF_BASE + 0x0000004C)
1429 #define CIF_ISP_DPF_NULL_COEFF_12 (CIF_ISP_DPF_BASE + 0x00000050)
1430 #define CIF_ISP_DPF_NULL_COEFF_13 (CIF_ISP_DPF_BASE + 0x00000054)
1431 #define CIF_ISP_DPF_NULL_COEFF_14 (CIF_ISP_DPF_BASE + 0x00000058)
1432 #define CIF_ISP_DPF_NULL_COEFF_15 (CIF_ISP_DPF_BASE + 0x0000005C)
1433 #define CIF_ISP_DPF_NULL_COEFF_16 (CIF_ISP_DPF_BASE + 0x00000060)
1434 #define CIF_ISP_DPF_NF_GAIN_R (CIF_ISP_DPF_BASE + 0x00000064)
1435 #define CIF_ISP_DPF_NF_GAIN_GR (CIF_ISP_DPF_BASE + 0x00000068)
1436 #define CIF_ISP_DPF_NF_GAIN_GB (CIF_ISP_DPF_BASE + 0x0000006C)
1437 #define CIF_ISP_DPF_NF_GAIN_B (CIF_ISP_DPF_BASE + 0x00000070)
1438
1439 #define CIF_ISP_DPCC_BASE 0x00002900
1440 #define CIF_ISP_DPCC_MODE (CIF_ISP_DPCC_BASE + 0x00000000)
1441 #define CIF_ISP_DPCC_OUTPUT_MODE (CIF_ISP_DPCC_BASE + 0x00000004)
1442 #define CIF_ISP_DPCC_SET_USE (CIF_ISP_DPCC_BASE + 0x00000008)
1443 #define CIF_ISP_DPCC_METHODS_SET_1 (CIF_ISP_DPCC_BASE + 0x0000000C)
1444 #define CIF_ISP_DPCC_METHODS_SET_2 (CIF_ISP_DPCC_BASE + 0x00000010)
1445 #define CIF_ISP_DPCC_METHODS_SET_3 (CIF_ISP_DPCC_BASE + 0x00000014)
1446 #define CIF_ISP_DPCC_LINE_THRESH_1 (CIF_ISP_DPCC_BASE + 0x00000018)
1447 #define CIF_ISP_DPCC_LINE_MAD_FAC_1 (CIF_ISP_DPCC_BASE + 0x0000001C)
1448 #define CIF_ISP_DPCC_PG_FAC_1 (CIF_ISP_DPCC_BASE + 0x00000020)
1449 #define CIF_ISP_DPCC_RND_THRESH_1 (CIF_ISP_DPCC_BASE + 0x00000024)
1450 #define CIF_ISP_DPCC_RG_FAC_1 (CIF_ISP_DPCC_BASE + 0x00000028)
1451 #define CIF_ISP_DPCC_LINE_THRESH_2 (CIF_ISP_DPCC_BASE + 0x0000002C)
1452 #define CIF_ISP_DPCC_LINE_MAD_FAC_2 (CIF_ISP_DPCC_BASE + 0x00000030)
1453 #define CIF_ISP_DPCC_PG_FAC_2 (CIF_ISP_DPCC_BASE + 0x00000034)
1454 #define CIF_ISP_DPCC_RND_THRESH_2 (CIF_ISP_DPCC_BASE + 0x00000038)
1455 #define CIF_ISP_DPCC_RG_FAC_2 (CIF_ISP_DPCC_BASE + 0x0000003C)
1456 #define CIF_ISP_DPCC_LINE_THRESH_3 (CIF_ISP_DPCC_BASE + 0x00000040)
1457 #define CIF_ISP_DPCC_LINE_MAD_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000044)
1458 #define CIF_ISP_DPCC_PG_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000048)
1459 #define CIF_ISP_DPCC_RND_THRESH_3 (CIF_ISP_DPCC_BASE + 0x0000004C)
1460 #define CIF_ISP_DPCC_RG_FAC_3 (CIF_ISP_DPCC_BASE + 0x00000050)
1461 #define CIF_ISP_DPCC_RO_LIMITS (CIF_ISP_DPCC_BASE + 0x00000054)
1462 #define CIF_ISP_DPCC_RND_OFFS (CIF_ISP_DPCC_BASE + 0x00000058)
1463 #define CIF_ISP_DPCC_BPT_CTRL (CIF_ISP_DPCC_BASE + 0x0000005C)
1464 #define CIF_ISP_DPCC_BPT_NUMBER (CIF_ISP_DPCC_BASE + 0x00000060)
1465 #define CIF_ISP_DPCC_BPT_ADDR (CIF_ISP_DPCC_BASE + 0x00000064)
1466 #define CIF_ISP_DPCC_BPT_DATA (CIF_ISP_DPCC_BASE + 0x00000068)
1467
1468 #define CIF_ISP_WDR_BASE 0x00002A00
1469 #define CIF_ISP_WDR_CTRL (CIF_ISP_WDR_BASE + 0x00000000)
1470 #define CIF_ISP_WDR_TONECURVE_1 (CIF_ISP_WDR_BASE + 0x00000004)
1471 #define CIF_ISP_WDR_TONECURVE_2 (CIF_ISP_WDR_BASE + 0x00000008)
1472 #define CIF_ISP_WDR_TONECURVE_3 (CIF_ISP_WDR_BASE + 0x0000000C)
1473 #define CIF_ISP_WDR_TONECURVE_4 (CIF_ISP_WDR_BASE + 0x00000010)
1474 #define CIF_ISP_WDR_TONECURVE_YM_0 (CIF_ISP_WDR_BASE + 0x00000014)
1475 #define CIF_ISP_WDR_TONECURVE_YM_1 (CIF_ISP_WDR_BASE + 0x00000018)
1476 #define CIF_ISP_WDR_TONECURVE_YM_2 (CIF_ISP_WDR_BASE + 0x0000001C)
1477 #define CIF_ISP_WDR_TONECURVE_YM_3 (CIF_ISP_WDR_BASE + 0x00000020)
1478 #define CIF_ISP_WDR_TONECURVE_YM_4 (CIF_ISP_WDR_BASE + 0x00000024)
1479 #define CIF_ISP_WDR_TONECURVE_YM_5 (CIF_ISP_WDR_BASE + 0x00000028)
1480 #define CIF_ISP_WDR_TONECURVE_YM_6 (CIF_ISP_WDR_BASE + 0x0000002C)
1481 #define CIF_ISP_WDR_TONECURVE_YM_7 (CIF_ISP_WDR_BASE + 0x00000030)
1482 #define CIF_ISP_WDR_TONECURVE_YM_8 (CIF_ISP_WDR_BASE + 0x00000034)
1483 #define CIF_ISP_WDR_TONECURVE_YM_9 (CIF_ISP_WDR_BASE + 0x00000038)
1484 #define CIF_ISP_WDR_TONECURVE_YM_10 (CIF_ISP_WDR_BASE + 0x0000003C)
1485 #define CIF_ISP_WDR_TONECURVE_YM_11 (CIF_ISP_WDR_BASE + 0x00000040)
1486 #define CIF_ISP_WDR_TONECURVE_YM_12 (CIF_ISP_WDR_BASE + 0x00000044)
1487 #define CIF_ISP_WDR_TONECURVE_YM_13 (CIF_ISP_WDR_BASE + 0x00000048)
1488 #define CIF_ISP_WDR_TONECURVE_YM_14 (CIF_ISP_WDR_BASE + 0x0000004C)
1489 #define CIF_ISP_WDR_TONECURVE_YM_15 (CIF_ISP_WDR_BASE + 0x00000050)
1490 #define CIF_ISP_WDR_TONECURVE_YM_16 (CIF_ISP_WDR_BASE + 0x00000054)
1491 #define CIF_ISP_WDR_TONECURVE_YM_17 (CIF_ISP_WDR_BASE + 0x00000058)
1492 #define CIF_ISP_WDR_TONECURVE_YM_18 (CIF_ISP_WDR_BASE + 0x0000005C)
1493 #define CIF_ISP_WDR_TONECURVE_YM_19 (CIF_ISP_WDR_BASE + 0x00000060)
1494 #define CIF_ISP_WDR_TONECURVE_YM_20 (CIF_ISP_WDR_BASE + 0x00000064)
1495 #define CIF_ISP_WDR_TONECURVE_YM_21 (CIF_ISP_WDR_BASE + 0x00000068)
1496 #define CIF_ISP_WDR_TONECURVE_YM_22 (CIF_ISP_WDR_BASE + 0x0000006C)
1497 #define CIF_ISP_WDR_TONECURVE_YM_23 (CIF_ISP_WDR_BASE + 0x00000070)
1498 #define CIF_ISP_WDR_TONECURVE_YM_24 (CIF_ISP_WDR_BASE + 0x00000074)
1499 #define CIF_ISP_WDR_TONECURVE_YM_25 (CIF_ISP_WDR_BASE + 0x00000078)
1500 #define CIF_ISP_WDR_TONECURVE_YM_26 (CIF_ISP_WDR_BASE + 0x0000007C)
1501 #define CIF_ISP_WDR_TONECURVE_YM_27 (CIF_ISP_WDR_BASE + 0x00000080)
1502 #define CIF_ISP_WDR_TONECURVE_YM_28 (CIF_ISP_WDR_BASE + 0x00000084)
1503 #define CIF_ISP_WDR_TONECURVE_YM_29 (CIF_ISP_WDR_BASE + 0x00000088)
1504 #define CIF_ISP_WDR_TONECURVE_YM_30 (CIF_ISP_WDR_BASE + 0x0000008C)
1505 #define CIF_ISP_WDR_TONECURVE_YM_31 (CIF_ISP_WDR_BASE + 0x00000090)
1506 #define CIF_ISP_WDR_TONECURVE_YM_32 (CIF_ISP_WDR_BASE + 0x00000094)
1507 #define CIF_ISP_WDR_OFFSET (CIF_ISP_WDR_BASE + 0x00000098)
1508 #define CIF_ISP_WDR_DELTAMIN (CIF_ISP_WDR_BASE + 0x0000009C)
1509 #define CIF_ISP_WDR_TONECURVE_1_SHD (CIF_ISP_WDR_BASE + 0x000000A0)
1510 #define CIF_ISP_WDR_TONECURVE_2_SHD (CIF_ISP_WDR_BASE + 0x000000A4)
1511 #define CIF_ISP_WDR_TONECURVE_3_SHD (CIF_ISP_WDR_BASE + 0x000000A8)
1512 #define CIF_ISP_WDR_TONECURVE_4_SHD (CIF_ISP_WDR_BASE + 0x000000AC)
1513 #define CIF_ISP_WDR_TONECURVE_YM_0_SHD (CIF_ISP_WDR_BASE + 0x000000B0)
1514 #define CIF_ISP_WDR_TONECURVE_YM_1_SHD (CIF_ISP_WDR_BASE + 0x000000B4)
1515 #define CIF_ISP_WDR_TONECURVE_YM_2_SHD (CIF_ISP_WDR_BASE + 0x000000B8)
1516 #define CIF_ISP_WDR_TONECURVE_YM_3_SHD (CIF_ISP_WDR_BASE + 0x000000BC)
1517 #define CIF_ISP_WDR_TONECURVE_YM_4_SHD (CIF_ISP_WDR_BASE + 0x000000C0)
1518 #define CIF_ISP_WDR_TONECURVE_YM_5_SHD (CIF_ISP_WDR_BASE + 0x000000C4)
1519 #define CIF_ISP_WDR_TONECURVE_YM_6_SHD (CIF_ISP_WDR_BASE + 0x000000C8)
1520 #define CIF_ISP_WDR_TONECURVE_YM_7_SHD (CIF_ISP_WDR_BASE + 0x000000CC)
1521 #define CIF_ISP_WDR_TONECURVE_YM_8_SHD (CIF_ISP_WDR_BASE + 0x000000D0)
1522 #define CIF_ISP_WDR_TONECURVE_YM_9_SHD (CIF_ISP_WDR_BASE + 0x000000D4)
1523 #define CIF_ISP_WDR_TONECURVE_YM_10_SHD (CIF_ISP_WDR_BASE + 0x000000D8)
1524 #define CIF_ISP_WDR_TONECURVE_YM_11_SHD (CIF_ISP_WDR_BASE + 0x000000DC)
1525 #define CIF_ISP_WDR_TONECURVE_YM_12_SHD (CIF_ISP_WDR_BASE + 0x000000E0)
1526 #define CIF_ISP_WDR_TONECURVE_YM_13_SHD (CIF_ISP_WDR_BASE + 0x000000E4)
1527 #define CIF_ISP_WDR_TONECURVE_YM_14_SHD (CIF_ISP_WDR_BASE + 0x000000E8)
1528 #define CIF_ISP_WDR_TONECURVE_YM_15_SHD (CIF_ISP_WDR_BASE + 0x000000EC)
1529 #define CIF_ISP_WDR_TONECURVE_YM_16_SHD (CIF_ISP_WDR_BASE + 0x000000F0)
1530 #define CIF_ISP_WDR_TONECURVE_YM_17_SHD (CIF_ISP_WDR_BASE + 0x000000F4)
1531 #define CIF_ISP_WDR_TONECURVE_YM_18_SHD (CIF_ISP_WDR_BASE + 0x000000F8)
1532 #define CIF_ISP_WDR_TONECURVE_YM_19_SHD (CIF_ISP_WDR_BASE + 0x000000FC)
1533 #define CIF_ISP_WDR_TONECURVE_YM_20_SHD (CIF_ISP_WDR_BASE + 0x00000100)
1534 #define CIF_ISP_WDR_TONECURVE_YM_21_SHD (CIF_ISP_WDR_BASE + 0x00000104)
1535 #define CIF_ISP_WDR_TONECURVE_YM_22_SHD (CIF_ISP_WDR_BASE + 0x00000108)
1536 #define CIF_ISP_WDR_TONECURVE_YM_23_SHD (CIF_ISP_WDR_BASE + 0x0000010C)
1537 #define CIF_ISP_WDR_TONECURVE_YM_24_SHD (CIF_ISP_WDR_BASE + 0x00000110)
1538 #define CIF_ISP_WDR_TONECURVE_YM_25_SHD (CIF_ISP_WDR_BASE + 0x00000114)
1539 #define CIF_ISP_WDR_TONECURVE_YM_26_SHD (CIF_ISP_WDR_BASE + 0x00000118)
1540 #define CIF_ISP_WDR_TONECURVE_YM_27_SHD (CIF_ISP_WDR_BASE + 0x0000011C)
1541 #define CIF_ISP_WDR_TONECURVE_YM_28_SHD (CIF_ISP_WDR_BASE + 0x00000120)
1542 #define CIF_ISP_WDR_TONECURVE_YM_29_SHD (CIF_ISP_WDR_BASE + 0x00000124)
1543 #define CIF_ISP_WDR_TONECURVE_YM_30_SHD (CIF_ISP_WDR_BASE + 0x00000128)
1544 #define CIF_ISP_WDR_TONECURVE_YM_31_SHD (CIF_ISP_WDR_BASE + 0x0000012C)
1545 #define CIF_ISP_WDR_TONECURVE_YM_32_SHD (CIF_ISP_WDR_BASE + 0x00000130)
1546
1547 #define CIF_ISP_RKWDR_CTRL0 (CIF_ISP_WDR_BASE + 0x00000150)
1548 #define CIF_ISP_RKWDR_CTRL1 (CIF_ISP_WDR_BASE + 0x00000154)
1549 #define CIF_ISP_RKWDR_BLKOFF0 (CIF_ISP_WDR_BASE + 0x00000158)
1550 #define CIF_ISP_RKWDR_AVGCLIP (CIF_ISP_WDR_BASE + 0x0000015c)
1551 #define CIF_ISP_RKWDR_COE_0 (CIF_ISP_WDR_BASE + 0x00000160)
1552 #define CIF_ISP_RKWDR_COE_1 (CIF_ISP_WDR_BASE + 0x00000164)
1553 #define CIF_ISP_RKWDR_COE_2 (CIF_ISP_WDR_BASE + 0x00000168)
1554 #define CIF_ISP_RKWDR_COE_OFF (CIF_ISP_WDR_BASE + 0x0000016c)
1555 #define CIF_ISP_RKWDR_OVERL (CIF_ISP_WDR_BASE + 0x00000170)
1556 #define CIF_ISP_RKWDR_BLKOFF1 (CIF_ISP_WDR_BASE + 0x00000174)
1557 #define CIF_ISP_RKWDR_BLKMEAN8_ROW0_0TO3 (CIF_ISP_WDR_BASE + 0x00000180)
1558 #define CIF_ISP_RKWDR_BLKMEAN8_ROW0_4TO7 (CIF_ISP_WDR_BASE + 0x00000184)
1559 #define CIF_ISP_RKWDR_BLKMEAN8_ROW1_0TO3 (CIF_ISP_WDR_BASE + 0x00000188)
1560 #define CIF_ISP_RKWDR_BLKMEAN8_ROW1_4TO7 (CIF_ISP_WDR_BASE + 0x0000018c)
1561 #define CIF_ISP_RKWDR_BLKMEAN8_ROW2_0TO3 (CIF_ISP_WDR_BASE + 0x00000190)
1562 #define CIF_ISP_RKWDR_BLKMEAN8_ROW2_4TO7 (CIF_ISP_WDR_BASE + 0x00000194)
1563 #define CIF_ISP_RKWDR_BLKMEAN8_ROW3_0TO3 (CIF_ISP_WDR_BASE + 0x00000198)
1564 #define CIF_ISP_RKWDR_BLKMEAN8_ROW3_4TO7 (CIF_ISP_WDR_BASE + 0x0000019c)
1565 #define CIF_ISP_RKWDR_BLKMEAN8_ROW4_0TO3 (CIF_ISP_WDR_BASE + 0x000001a0)
1566 #define CIF_ISP_RKWDR_BLKMEAN8_ROW4_4TO7 (CIF_ISP_WDR_BASE + 0x000001a4)
1567 #define CIF_ISP_RKWDR_BLKMEAN8_ROW5_0TO3 (CIF_ISP_WDR_BASE + 0x000001a8)
1568 #define CIF_ISP_RKWDR_BLKMEAN8_ROW5_4TO7 (CIF_ISP_WDR_BASE + 0x000001ac)
1569 #define CIF_ISP_RKWDR_BLKMEAN8_ROW6_0TO3 (CIF_ISP_WDR_BASE + 0x000001b0)
1570 #define CIF_ISP_RKWDR_BLKMEAN8_ROW6_4TO7 (CIF_ISP_WDR_BASE + 0x000001b4)
1571 #define CIF_ISP_RKWDR_BLKMEAN8_ROW7_0TO3 (CIF_ISP_WDR_BASE + 0x000001b8)
1572 #define CIF_ISP_RKWDR_BLKMEAN8_ROW7_4TO7 (CIF_ISP_WDR_BASE + 0x000001bc)
1573 #define CIF_ISP_RKWDR_BLKMEAN8_ROW8_0TO3 (CIF_ISP_WDR_BASE + 0x000001c0)
1574 #define CIF_ISP_RKWDR_BLKMEAN8_ROW8_4TO7 (CIF_ISP_WDR_BASE + 0x000001c4)
1575 #define CIF_ISP_RKWDR_BLKMEAN8_ROW9_0TO3 (CIF_ISP_WDR_BASE + 0x000001c8)
1576 #define CIF_ISP_RKWDR_BLKMEAN8_ROW9_4TO7 (CIF_ISP_WDR_BASE + 0x000001cc)
1577
1578 #define CIF_ISP_HIST_BASE_V12 0x00002C00
1579 #define CIF_ISP_HIST_CTRL_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000000)
1580 #define CIF_ISP_HIST_SIZE_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000004)
1581 #define CIF_ISP_HIST_OFFS_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000008)
1582 #define CIF_ISP_HIST_DBG1_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000000C)
1583 #define CIF_ISP_HIST_DBG2_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000001C)
1584 #define CIF_ISP_HIST_DBG3_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000002C)
1585 #define CIF_ISP_HIST_WEIGHT_V12 (CIF_ISP_HIST_BASE_V12 + 0x0000003C)
1586 #define CIF_ISP_HIST_BIN_V12 (CIF_ISP_HIST_BASE_V12 + 0x00000120)
1587
1588 #define CIF_ISP_VSM_BASE 0x00002F00
1589 #define CIF_ISP_VSM_MODE (CIF_ISP_VSM_BASE + 0x00000000)
1590 #define CIF_ISP_VSM_H_OFFS (CIF_ISP_VSM_BASE + 0x00000004)
1591 #define CIF_ISP_VSM_V_OFFS (CIF_ISP_VSM_BASE + 0x00000008)
1592 #define CIF_ISP_VSM_H_SIZE (CIF_ISP_VSM_BASE + 0x0000000C)
1593 #define CIF_ISP_VSM_V_SIZE (CIF_ISP_VSM_BASE + 0x00000010)
1594 #define CIF_ISP_VSM_H_SEGMENTS (CIF_ISP_VSM_BASE + 0x00000014)
1595 #define CIF_ISP_VSM_V_SEGMENTS (CIF_ISP_VSM_BASE + 0x00000018)
1596 #define CIF_ISP_VSM_DELTA_H (CIF_ISP_VSM_BASE + 0x0000001C)
1597 #define CIF_ISP_VSM_DELTA_V (CIF_ISP_VSM_BASE + 0x00000020)
1598
1599 #define CIF_ISP_CSI0_BASE 0x00007000
1600 #define CIF_ISP_CSI0_CTRL0 (CIF_ISP_CSI0_BASE + 0x00000000)
1601 #define CIF_ISP_CSI0_CTRL1 (CIF_ISP_CSI0_BASE + 0x00000004)
1602 #define CIF_ISP_CSI0_CTRL2 (CIF_ISP_CSI0_BASE + 0x00000008)
1603 #define CIF_ISP_CSI0_CSI2_RESETN (CIF_ISP_CSI0_BASE + 0x00000010)
1604 #define CIF_ISP_CSI0_PHY_STATE_RO (CIF_ISP_CSI0_BASE + 0x00000014)
1605 #define CIF_ISP_CSI0_DATA_IDS_1 (CIF_ISP_CSI0_BASE + 0x00000018)
1606 #define CIF_ISP_CSI0_DATA_IDS_2 (CIF_ISP_CSI0_BASE + 0x0000001c)
1607 #define CIF_ISP_CSI0_ERR1 (CIF_ISP_CSI0_BASE + 0x00000020)
1608 #define CIF_ISP_CSI0_ERR2 (CIF_ISP_CSI0_BASE + 0x00000024)
1609 #define CIF_ISP_CSI0_ERR3 (CIF_ISP_CSI0_BASE + 0x00000028)
1610 #define CIF_ISP_CSI0_MASK1 (CIF_ISP_CSI0_BASE + 0x0000002c)
1611 #define CIF_ISP_CSI0_MASK2 (CIF_ISP_CSI0_BASE + 0x00000030)
1612 #define CIF_ISP_CSI0_MASK3 (CIF_ISP_CSI0_BASE + 0x00000034)
1613 #define CIF_ISP_CSI0_SET_HEARDER (CIF_ISP_CSI0_BASE + 0x00000038)
1614 #define CIF_ISP_CSI0_CUR_HEADER_RO (CIF_ISP_CSI0_BASE + 0x0000003c)
1615 #define CIF_ISP_CSI0_DMATX0_CTRL (CIF_ISP_CSI0_BASE + 0x00000040)
1616 #define CIF_ISP_CSI0_DMATX0_LINECNT_RO (CIF_ISP_CSI0_BASE + 0x00000044)
1617 #define CIF_ISP_CSI0_DMATX0_PIC_SIZE (CIF_ISP_CSI0_BASE + 0x00000048)
1618 #define CIF_ISP_CSI0_DMATX0_PIC_OFF (CIF_ISP_CSI0_BASE + 0x0000004c)
1619 #define CIF_ISP_CSI0_FRAME_NUM_RO (CIF_ISP_CSI0_BASE + 0x00000070)
1620 #define CIF_ISP_CSI0_ISP_LINECNT_RO (CIF_ISP_CSI0_BASE + 0x00000074)
1621 #define CIF_ISP_CSI0_TX_IBUF_STATUS_RO (CIF_ISP_CSI0_BASE + 0x00000078)
1622 #define CIF_ISP_CSI0_VERSION (CIF_ISP_CSI0_BASE + 0x0000007c)
1623
1624 void rkisp_disable_dcrop(struct rkisp_stream *stream, bool async);
1625 void rkisp_config_dcrop(struct rkisp_stream *stream, struct v4l2_rect *rect, bool async);
1626
1627 void rkisp_dump_rsz_regs(struct rkisp_stream *stream);
1628 void rkisp_disable_rsz(struct rkisp_stream *stream, bool async);
1629 void rkisp_config_rsz(struct rkisp_stream *stream, struct v4l2_rect *in_y,
1630 struct v4l2_rect *in_c, struct v4l2_rect *out_y,
1631 struct v4l2_rect *out_c, bool async);
1632
config_mi_ctrl(struct rkisp_stream * stream,u32 burst)1633 static inline void config_mi_ctrl(struct rkisp_stream *stream, u32 burst)
1634 {
1635 void __iomem *base = stream->ispdev->base_addr;
1636 void __iomem *addr = base + CIF_MI_CTRL;
1637 u32 reg;
1638
1639 reg = readl(addr) & ~GENMASK(19, 16);
1640 writel(reg | burst, addr);
1641 reg = readl(addr);
1642 writel(reg | CIF_MI_CTRL_INIT_BASE_EN, addr);
1643 reg = readl(addr);
1644 writel(reg | CIF_MI_CTRL_INIT_OFFSET_EN, addr);
1645 }
1646
mp_is_stream_stopped(struct rkisp_stream * stream)1647 static inline bool mp_is_stream_stopped(struct rkisp_stream *stream)
1648 {
1649 u32 en = CIF_MI_CTRL_SHD_MP_OUT_ENABLED | CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
1650 u32 reg = CIF_MI_CTRL_SHD;
1651 bool is_direct = true;
1652
1653 if (!stream->ispdev->hw_dev->is_single) {
1654 is_direct = false;
1655 reg = CIF_MI_CTRL;
1656 en = CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE;
1657 }
1658
1659 return !(rkisp_read(stream->ispdev, reg, is_direct) & en);
1660 }
1661
sp_is_stream_stopped(struct rkisp_stream * stream)1662 static inline bool sp_is_stream_stopped(struct rkisp_stream *stream)
1663 {
1664 u32 reg = CIF_MI_CTRL_SHD, en = CIF_MI_CTRL_SHD_SP_OUT_ENABLED;
1665 bool is_direct = true;
1666
1667 if (!stream->ispdev->hw_dev->is_single) {
1668 is_direct = false;
1669 reg = CIF_MI_CTRL;
1670 en = CIF_MI_CTRL_SP_ENABLE;
1671 }
1672
1673 return !(rkisp_read(stream->ispdev, reg, is_direct) & en);
1674 }
1675
isp_set_bits(void __iomem * addr,u32 bit_mask,u32 val)1676 static inline void isp_set_bits(void __iomem *addr, u32 bit_mask, u32 val)
1677 {
1678 u32 tmp = readl(addr) & ~bit_mask;
1679
1680 writel(tmp | val, addr);
1681 }
1682
isp_clear_bits(void __iomem * addr,u32 bit_mask)1683 static inline void isp_clear_bits(void __iomem *addr, u32 bit_mask)
1684 {
1685 u32 val = readl(addr);
1686
1687 writel(val & ~bit_mask, addr);
1688 }
1689
mi_set_y_size(struct rkisp_stream * stream,int val)1690 static inline void mi_set_y_size(struct rkisp_stream *stream, int val)
1691 {
1692 void __iomem *base = stream->ispdev->base_addr;
1693
1694 writel(val, base + stream->config->mi.y_size_init);
1695 }
1696
mi_set_cb_size(struct rkisp_stream * stream,int val)1697 static inline void mi_set_cb_size(struct rkisp_stream *stream, int val)
1698 {
1699 void __iomem *base = stream->ispdev->base_addr;
1700
1701 writel(val, base + stream->config->mi.cb_size_init);
1702 }
1703
mi_set_cr_size(struct rkisp_stream * stream,int val)1704 static inline void mi_set_cr_size(struct rkisp_stream *stream, int val)
1705 {
1706 void __iomem *base = stream->ispdev->base_addr;
1707
1708 writel(val, base + stream->config->mi.cr_size_init);
1709 }
1710
mi_set_y_addr(struct rkisp_stream * stream,int val)1711 static inline void mi_set_y_addr(struct rkisp_stream *stream, int val)
1712 {
1713 void __iomem *base = stream->ispdev->base_addr;
1714
1715 writel(val, base + stream->config->mi.y_base_ad_init);
1716 }
1717
mi_set_cb_addr(struct rkisp_stream * stream,int val)1718 static inline void mi_set_cb_addr(struct rkisp_stream *stream, int val)
1719 {
1720 void __iomem *base = stream->ispdev->base_addr;
1721
1722 writel(val, base + stream->config->mi.cb_base_ad_init);
1723 }
1724
mi_set_cr_addr(struct rkisp_stream * stream,int val)1725 static inline void mi_set_cr_addr(struct rkisp_stream *stream, int val)
1726 {
1727 void __iomem *base = stream->ispdev->base_addr;
1728
1729 writel(val, base + stream->config->mi.cr_base_ad_init);
1730 }
1731
mi_set_y_offset(struct rkisp_stream * stream,int val)1732 static inline void mi_set_y_offset(struct rkisp_stream *stream, int val)
1733 {
1734 void __iomem *base = stream->ispdev->base_addr;
1735
1736 writel(val, base + stream->config->mi.y_offs_cnt_init);
1737 }
1738
mi_set_cb_offset(struct rkisp_stream * stream,int val)1739 static inline void mi_set_cb_offset(struct rkisp_stream *stream, int val)
1740 {
1741 void __iomem *base = stream->ispdev->base_addr;
1742
1743 writel(val, base + stream->config->mi.cb_offs_cnt_init);
1744 }
1745
mi_set_cr_offset(struct rkisp_stream * stream,int val)1746 static inline void mi_set_cr_offset(struct rkisp_stream *stream, int val)
1747 {
1748 void __iomem *base = stream->ispdev->base_addr;
1749
1750 writel(val, base + stream->config->mi.cr_offs_cnt_init);
1751 }
1752
mi_frame_end_int_enable(struct rkisp_stream * stream)1753 static inline void mi_frame_end_int_enable(struct rkisp_stream *stream)
1754 {
1755 struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1756 void __iomem *base = !hw->is_unite ?
1757 hw->base_addr : hw->base_next_addr;
1758 void __iomem *addr = base + CIF_MI_IMSC;
1759
1760 writel(CIF_MI_FRAME(stream) | readl(addr), addr);
1761 }
1762
mi_frame_end_int_disable(struct rkisp_stream * stream)1763 static inline void mi_frame_end_int_disable(struct rkisp_stream *stream)
1764 {
1765 struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1766 void __iomem *base = !hw->is_unite ?
1767 hw->base_addr : hw->base_next_addr;
1768 void __iomem *addr = base + CIF_MI_IMSC;
1769
1770 writel(~CIF_MI_FRAME(stream) & readl(addr), addr);
1771 }
1772
mi_frame_end_int_clear(struct rkisp_stream * stream)1773 static inline void mi_frame_end_int_clear(struct rkisp_stream *stream)
1774 {
1775 struct rkisp_hw_dev *hw = stream->ispdev->hw_dev;
1776 void __iomem *base = !hw->is_unite ?
1777 hw->base_addr : hw->base_next_addr;
1778 void __iomem *addr = base + CIF_MI_ICR;
1779
1780 writel(CIF_MI_FRAME(stream), addr);
1781 }
1782
stream_data_path(struct rkisp_stream * stream)1783 static inline void stream_data_path(struct rkisp_stream *stream)
1784 {
1785 struct rkisp_device *dev = stream->ispdev;
1786 bool is_unite = dev->hw_dev->is_unite;
1787 u32 dpcl = 0;
1788
1789 if (stream->id == RKISP_STREAM_MP)
1790 dpcl |= CIF_VI_DPCL_CHAN_MODE_MP | CIF_VI_DPCL_MP_MUX_MRSZ_MI;
1791 else if (stream->id == RKISP_STREAM_SP)
1792 dpcl |= CIF_VI_DPCL_CHAN_MODE_SP;
1793
1794 if (dpcl)
1795 rkisp_unite_set_bits(dev, CIF_VI_DPCL, 0, dpcl, true, is_unite);
1796 }
1797
mp_set_uv_swap(void __iomem * base)1798 static inline void mp_set_uv_swap(void __iomem *base)
1799 {
1800 void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
1801 u32 reg = readl(addr) & ~BIT(0);
1802
1803 writel(reg | CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP, addr);
1804 }
1805
sp_set_uv_swap(void __iomem * base)1806 static inline void sp_set_uv_swap(void __iomem *base)
1807 {
1808 void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
1809 u32 reg = readl(addr) & ~BIT(1);
1810
1811 writel(reg | CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP, addr);
1812 }
1813
sp_set_y_width(void __iomem * base,u32 val)1814 static inline void sp_set_y_width(void __iomem *base, u32 val)
1815 {
1816 writel(val, base + CIF_MI_SP_Y_PIC_WIDTH);
1817 }
1818
sp_set_y_height(void __iomem * base,u32 val)1819 static inline void sp_set_y_height(void __iomem *base, u32 val)
1820 {
1821 writel(val, base + CIF_MI_SP_Y_PIC_HEIGHT);
1822 }
1823
sp_set_y_line_length(void __iomem * base,u32 val)1824 static inline void sp_set_y_line_length(void __iomem *base, u32 val)
1825 {
1826 writel(val, base + CIF_MI_SP_Y_LLENGTH);
1827 }
1828
mp_mi_ctrl_set_format(void __iomem * base,u32 val)1829 static inline void mp_mi_ctrl_set_format(void __iomem *base, u32 val)
1830 {
1831 void __iomem *addr = base + CIF_MI_CTRL;
1832 u32 reg = readl(addr) & ~MI_CTRL_MP_FMT_MASK;
1833
1834 writel(reg | val, addr);
1835 }
1836
sp_mi_ctrl_set_format(void __iomem * base,u32 val)1837 static inline void sp_mi_ctrl_set_format(void __iomem *base, u32 val)
1838 {
1839 void __iomem *addr = base + CIF_MI_CTRL;
1840 u32 reg = readl(addr) & ~MI_CTRL_SP_FMT_MASK;
1841
1842 writel(reg | val, addr);
1843 }
1844
mi_ctrl_mpyuv_enable(void __iomem * base)1845 static inline void mi_ctrl_mpyuv_enable(void __iomem *base)
1846 {
1847 void __iomem *addr = base + CIF_MI_CTRL;
1848
1849 writel(CIF_MI_CTRL_MP_ENABLE | readl(addr), addr);
1850 }
1851
mi_ctrl_mpyuv_disable(void __iomem * base)1852 static inline void mi_ctrl_mpyuv_disable(void __iomem *base)
1853 {
1854 void __iomem *addr = base + CIF_MI_CTRL;
1855
1856 writel(~CIF_MI_CTRL_MP_ENABLE & readl(addr), addr);
1857 }
1858
mi_ctrl_mp_disable(void __iomem * base)1859 static inline void mi_ctrl_mp_disable(void __iomem *base)
1860 {
1861 void __iomem *addr = base + CIF_MI_CTRL;
1862
1863 writel(~(CIF_MI_CTRL_MP_ENABLE | CIF_MI_CTRL_RAW_ENABLE) & readl(addr),
1864 addr);
1865 }
1866
mi_ctrl_spyuv_enable(void __iomem * base)1867 static inline void mi_ctrl_spyuv_enable(void __iomem *base)
1868 {
1869 void __iomem *addr = base + CIF_MI_CTRL;
1870
1871 writel(CIF_MI_CTRL_SP_ENABLE | readl(addr), addr);
1872 }
1873
mi_ctrl_spyuv_disable(void __iomem * base)1874 static inline void mi_ctrl_spyuv_disable(void __iomem *base)
1875 {
1876 void __iomem *addr = base + CIF_MI_CTRL;
1877
1878 writel(~CIF_MI_CTRL_SP_ENABLE & readl(addr), addr);
1879 }
1880
mi_ctrl_sp_disable(void __iomem * base)1881 static inline void mi_ctrl_sp_disable(void __iomem *base)
1882 {
1883 mi_ctrl_spyuv_disable(base);
1884 }
1885
mi_ctrl_mpraw_enable(void __iomem * base)1886 static inline void mi_ctrl_mpraw_enable(void __iomem *base)
1887 {
1888 void __iomem *addr = base + CIF_MI_CTRL;
1889
1890 writel(CIF_MI_CTRL_RAW_ENABLE | readl(addr), addr);
1891 }
1892
mi_ctrl_mpraw_disable(void __iomem * base)1893 static inline void mi_ctrl_mpraw_disable(void __iomem *base)
1894 {
1895 void __iomem *addr = base + CIF_MI_CTRL;
1896
1897 writel(~CIF_MI_CTRL_RAW_ENABLE & readl(addr), addr);
1898 }
1899
mp_mi_ctrl_autoupdate_en(void __iomem * base)1900 static inline void mp_mi_ctrl_autoupdate_en(void __iomem *base)
1901 {
1902 void __iomem *addr = base + CIF_MI_CTRL;
1903
1904 writel(readl(addr) | CIF_MI_MP_AUTOUPDATE_ENABLE, addr);
1905 }
1906
sp_mi_ctrl_autoupdate_en(void __iomem * base)1907 static inline void sp_mi_ctrl_autoupdate_en(void __iomem *base)
1908 {
1909 void __iomem *addr = base + CIF_MI_CTRL;
1910
1911 writel(readl(addr) | CIF_MI_SP_AUTOUPDATE_ENABLE, addr);
1912 }
1913
force_cfg_update(struct rkisp_device * dev)1914 static inline void force_cfg_update(struct rkisp_device *dev)
1915 {
1916 u32 val = CIF_MI_CTRL_INIT_OFFSET_EN | CIF_MI_CTRL_INIT_BASE_EN;
1917 bool is_unite = dev->hw_dev->is_unite;
1918
1919 if (dev->isp_ver == ISP_V21) {
1920 val |= rkisp_read_reg_cache(dev, CIF_MI_CTRL);
1921 rkisp_write(dev, CIF_MI_CTRL, val, true);
1922 }
1923 dev->hw_dev->is_mi_update = true;
1924 rkisp_unite_set_bits(dev, CIF_MI_CTRL, 0, val, false, is_unite);
1925 val = CIF_MI_INIT_SOFT_UPD;
1926 rkisp_unite_write(dev, CIF_MI_INIT, val, true, is_unite);
1927 }
1928
dmatx0_ctrl(void __iomem * base,u32 val)1929 static inline void dmatx0_ctrl(void __iomem *base, u32 val)
1930 {
1931 writel(val, base + CIF_ISP_CSI0_DMATX0_CTRL);
1932 }
1933
dmatx0_enable(void __iomem * base)1934 static inline void dmatx0_enable(void __iomem *base)
1935 {
1936 void __iomem *addr = base + CIF_ISP_CSI0_DMATX0_CTRL;
1937
1938 writel(CIF_ISP_CSI0_DMATX0_EN | readl(addr), addr);
1939 }
1940
dmatx0_disable(void __iomem * base)1941 static inline void dmatx0_disable(void __iomem *base)
1942 {
1943 void __iomem *addr = base + CIF_ISP_CSI0_DMATX0_CTRL;
1944
1945 writel(~CIF_ISP_CSI0_DMATX0_EN & readl(addr), addr);
1946 }
1947
dmatx0_set_pic_size(void __iomem * base,u32 width,u32 height)1948 static inline void dmatx0_set_pic_size(void __iomem *base,
1949 u32 width, u32 height)
1950 {
1951 writel(height << 16 | width,
1952 base + CIF_ISP_CSI0_DMATX0_PIC_SIZE);
1953 }
1954
dmatx0_set_pic_off(void __iomem * base,u32 val)1955 static inline void dmatx0_set_pic_off(void __iomem *base, u32 val)
1956 {
1957 writel(val, base + CIF_ISP_CSI0_DMATX0_PIC_OFF);
1958 }
1959
mi_raw0_set_size(void __iomem * base,u32 val)1960 static inline void mi_raw0_set_size(void __iomem *base, u32 val)
1961 {
1962 writel(val, base + CIF_MI_RAW0_SIZE_INIT);
1963 }
1964
mi_raw0_set_offs(void __iomem * base,u32 val)1965 static inline void mi_raw0_set_offs(void __iomem *base, u32 val)
1966 {
1967 writel(val, base + CIF_MI_RAW0_OFFS_CNT_INIT);
1968 }
1969
mi_raw0_set_length(void __iomem * base,u32 val)1970 static inline void mi_raw0_set_length(void __iomem *base, u32 val)
1971 {
1972 writel(val, base + CIF_MI_RAW0_LENGTH);
1973 }
1974
mi_raw0_set_irq_offs(void __iomem * base,u32 val)1975 static inline void mi_raw0_set_irq_offs(void __iomem *base, u32 val)
1976 {
1977 writel(val, base + CIF_MI_RAW0_IRQ_OFFS_INIT);
1978 }
1979
mi_raw0_set_addr(void __iomem * base,u32 val)1980 static inline void mi_raw0_set_addr(void __iomem *base, u32 val)
1981 {
1982 writel(val, base + CIF_MI_RAW0_BASE_AD_INIT);
1983 }
1984
mi_mipi_raw0_enable(void __iomem * base)1985 static inline void mi_mipi_raw0_enable(void __iomem *base)
1986 {
1987 void __iomem *addr = base + CIF_MI_CTRL2;
1988
1989 writel(CIF_MI_CTRL2_MIPI_RAW0_ENABLE | readl(addr), addr);
1990 }
1991
mi_mipi_raw0_disable(void __iomem * base)1992 static inline void mi_mipi_raw0_disable(void __iomem *base)
1993 {
1994 void __iomem *addr = base + CIF_MI_CTRL2;
1995
1996 writel(~CIF_MI_CTRL2_MIPI_RAW0_ENABLE & readl(addr), addr);
1997 }
1998
mi_ctrl2(void __iomem * base,u32 val)1999 static inline void mi_ctrl2(void __iomem *base, u32 val)
2000 {
2001 writel(val, base + CIF_MI_CTRL2);
2002 }
2003
mi_dmarx_ready_enable(struct rkisp_stream * stream)2004 static inline void mi_dmarx_ready_enable(struct rkisp_stream *stream)
2005 {
2006 void __iomem *base = stream->ispdev->base_addr;
2007 void __iomem *addr = base + CIF_MI_IMSC;
2008
2009 writel(CIF_MI_DMA_READY | readl(addr), addr);
2010 }
2011
mi_dmarx_ready_disable(struct rkisp_stream * stream)2012 static inline void mi_dmarx_ready_disable(struct rkisp_stream *stream)
2013 {
2014 void __iomem *base = stream->ispdev->base_addr;
2015 void __iomem *addr = base + CIF_MI_IMSC;
2016
2017 writel(~CIF_MI_DMA_READY & readl(addr), addr);
2018 }
2019
dmarx_set_uv_swap(void __iomem * base)2020 static inline void dmarx_set_uv_swap(void __iomem *base)
2021 {
2022 void __iomem *addr = base + CIF_MI_XTD_FORMAT_CTRL;
2023 u32 reg = readl(addr) & ~BIT(2);
2024
2025 writel(reg | CIF_MI_XTD_FMT_CTRL_DMA_CB_CR_SWAP, addr);
2026 }
2027
dmarx_set_y_width(void __iomem * base,u32 val)2028 static inline void dmarx_set_y_width(void __iomem *base, u32 val)
2029 {
2030 writel(val, base + CIF_MI_DMA_Y_PIC_WIDTH);
2031 }
2032
dmarx_set_y_line_length(void __iomem * base,u32 val)2033 static inline void dmarx_set_y_line_length(void __iomem *base, u32 val)
2034 {
2035 writel(val, base + CIF_MI_DMA_Y_LLENGTH);
2036 }
2037
dmarx_ctrl(void __iomem * base,u32 val)2038 static inline void dmarx_ctrl(void __iomem *base, u32 val)
2039 {
2040 void __iomem *addr = base + CIF_MI_DMA_CTRL;
2041
2042 writel(val | readl(addr), addr);
2043 }
2044
mi_dmarx_start(void __iomem * base)2045 static inline void mi_dmarx_start(void __iomem *base)
2046 {
2047 void __iomem *addr = base + CIF_MI_DMA_START;
2048
2049 writel(CIF_MI_DMA_START_ENABLE, addr);
2050 }
2051
2052 #endif /* _RKISP_REGS_H */
2053