1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Fujitsu MB862xx Graphics Controller Registers/Bits 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _MB862XX_REG_H 7*4882a593Smuzhiyun #define _MB862XX_REG_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MB862XX_MMIO_BASE 0x01fc0000 10*4882a593Smuzhiyun #define MB862XX_MMIO_HIGH_BASE 0x03fc0000 11*4882a593Smuzhiyun #define MB862XX_I2C_BASE 0x0000c000 12*4882a593Smuzhiyun #define MB862XX_DISP_BASE 0x00010000 13*4882a593Smuzhiyun #define MB862XX_CAP_BASE 0x00018000 14*4882a593Smuzhiyun #define MB862XX_DRAW_BASE 0x00030000 15*4882a593Smuzhiyun #define MB862XX_GEO_BASE 0x00038000 16*4882a593Smuzhiyun #define MB862XX_PIO_BASE 0x00038000 17*4882a593Smuzhiyun #define MB862XX_MMIO_SIZE 0x40000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Host interface/pio registers */ 20*4882a593Smuzhiyun #define GC_IST 0x00000020 21*4882a593Smuzhiyun #define GC_IMASK 0x00000024 22*4882a593Smuzhiyun #define GC_SRST 0x0000002c 23*4882a593Smuzhiyun #define GC_CCF 0x00000038 24*4882a593Smuzhiyun #define GC_RSW 0x0000005c 25*4882a593Smuzhiyun #define GC_CID 0x000000f0 26*4882a593Smuzhiyun #define GC_REVISION 0x00000084 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define GC_CCF_CGE_100 0x00000000 29*4882a593Smuzhiyun #define GC_CCF_CGE_133 0x00040000 30*4882a593Smuzhiyun #define GC_CCF_CGE_166 0x00080000 31*4882a593Smuzhiyun #define GC_CCF_COT_100 0x00000000 32*4882a593Smuzhiyun #define GC_CCF_COT_133 0x00010000 33*4882a593Smuzhiyun #define GC_CID_CNAME_MSK 0x0000ff00 34*4882a593Smuzhiyun #define GC_CID_VERSION_MSK 0x000000ff 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* define enabled interrupts hereby */ 37*4882a593Smuzhiyun #define GC_INT_EN 0x00000000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Memory interface mode register */ 40*4882a593Smuzhiyun #define GC_MMR 0x0000fffc 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Display Controller registers */ 43*4882a593Smuzhiyun #define GC_DCM0 0x00000000 44*4882a593Smuzhiyun #define GC_HTP 0x00000004 45*4882a593Smuzhiyun #define GC_HDB_HDP 0x00000008 46*4882a593Smuzhiyun #define GC_VSW_HSW_HSP 0x0000000c 47*4882a593Smuzhiyun #define GC_VTR 0x00000010 48*4882a593Smuzhiyun #define GC_VDP_VSP 0x00000014 49*4882a593Smuzhiyun #define GC_WY_WX 0x00000018 50*4882a593Smuzhiyun #define GC_WH_WW 0x0000001c 51*4882a593Smuzhiyun #define GC_L0M 0x00000020 52*4882a593Smuzhiyun #define GC_L0OA0 0x00000024 53*4882a593Smuzhiyun #define GC_L0DA0 0x00000028 54*4882a593Smuzhiyun #define GC_L0DY_L0DX 0x0000002c 55*4882a593Smuzhiyun #define GC_L1M 0x00000030 56*4882a593Smuzhiyun #define GC_L1DA 0x00000034 57*4882a593Smuzhiyun #define GC_DCM1 0x00000100 58*4882a593Smuzhiyun #define GC_L0EM 0x00000110 59*4882a593Smuzhiyun #define GC_L0WY_L0WX 0x00000114 60*4882a593Smuzhiyun #define GC_L0WH_L0WW 0x00000118 61*4882a593Smuzhiyun #define GC_L1EM 0x00000120 62*4882a593Smuzhiyun #define GC_L1WY_L1WX 0x00000124 63*4882a593Smuzhiyun #define GC_L1WH_L1WW 0x00000128 64*4882a593Smuzhiyun #define GC_DLS 0x00000180 65*4882a593Smuzhiyun #define GC_DCM2 0x00000104 66*4882a593Smuzhiyun #define GC_DCM3 0x00000108 67*4882a593Smuzhiyun #define GC_CPM_CUTC 0x000000a0 68*4882a593Smuzhiyun #define GC_CUOA0 0x000000a4 69*4882a593Smuzhiyun #define GC_CUY0_CUX0 0x000000a8 70*4882a593Smuzhiyun #define GC_CUOA1 0x000000ac 71*4882a593Smuzhiyun #define GC_CUY1_CUX1 0x000000b0 72*4882a593Smuzhiyun #define GC_L0PAL0 0x00000400 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define GC_CPM_CEN0 0x00100000 75*4882a593Smuzhiyun #define GC_CPM_CEN1 0x00200000 76*4882a593Smuzhiyun #define GC_DCM1_DEN 0x80000000 77*4882a593Smuzhiyun #define GC_DCM1_L1E 0x00020000 78*4882a593Smuzhiyun #define GC_L1M_16 0x80000000 79*4882a593Smuzhiyun #define GC_L1M_YC 0x40000000 80*4882a593Smuzhiyun #define GC_L1M_CS 0x20000000 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define GC_DCM01_ESY 0x00000004 83*4882a593Smuzhiyun #define GC_DCM01_SC 0x00003f00 84*4882a593Smuzhiyun #define GC_DCM01_RESV 0x00004000 85*4882a593Smuzhiyun #define GC_DCM01_CKS 0x00008000 86*4882a593Smuzhiyun #define GC_DCM01_L0E 0x00010000 87*4882a593Smuzhiyun #define GC_DCM01_DEN 0x80000000 88*4882a593Smuzhiyun #define GC_L0M_L0C_8 0x00000000 89*4882a593Smuzhiyun #define GC_L0M_L0C_16 0x80000000 90*4882a593Smuzhiyun #define GC_L0EM_L0EC_24 0x40000000 91*4882a593Smuzhiyun #define GC_L0M_L0W_UNIT 64 92*4882a593Smuzhiyun #define GC_L1EM_DM 0x02000000 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define GC_DISP_REFCLK_400 400 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* I2C */ 97*4882a593Smuzhiyun #define GC_I2C_BSR 0x00000000 /* BSR */ 98*4882a593Smuzhiyun #define GC_I2C_BCR 0x00000004 /* BCR */ 99*4882a593Smuzhiyun #define GC_I2C_CCR 0x00000008 /* CCR */ 100*4882a593Smuzhiyun #define GC_I2C_ADR 0x0000000C /* ADR */ 101*4882a593Smuzhiyun #define GC_I2C_DAR 0x00000010 /* DAR */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define I2C_DISABLE 0x00000000 104*4882a593Smuzhiyun #define I2C_STOP 0x00000000 105*4882a593Smuzhiyun #define I2C_START 0x00000010 106*4882a593Smuzhiyun #define I2C_REPEATED_START 0x00000030 107*4882a593Smuzhiyun #define I2C_CLOCK_AND_ENABLE 0x0000003f 108*4882a593Smuzhiyun #define I2C_READY 0x01 109*4882a593Smuzhiyun #define I2C_INT 0x01 110*4882a593Smuzhiyun #define I2C_INTE 0x02 111*4882a593Smuzhiyun #define I2C_ACK 0x08 112*4882a593Smuzhiyun #define I2C_BER 0x80 113*4882a593Smuzhiyun #define I2C_BEIE 0x40 114*4882a593Smuzhiyun #define I2C_TRX 0x80 115*4882a593Smuzhiyun #define I2C_LRB 0x10 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* Capture registers and bits */ 118*4882a593Smuzhiyun #define GC_CAP_VCM 0x00000000 119*4882a593Smuzhiyun #define GC_CAP_CSC 0x00000004 120*4882a593Smuzhiyun #define GC_CAP_VCS 0x00000008 121*4882a593Smuzhiyun #define GC_CAP_CBM 0x00000010 122*4882a593Smuzhiyun #define GC_CAP_CBOA 0x00000014 123*4882a593Smuzhiyun #define GC_CAP_CBLA 0x00000018 124*4882a593Smuzhiyun #define GC_CAP_IMG_START 0x0000001C 125*4882a593Smuzhiyun #define GC_CAP_IMG_END 0x00000020 126*4882a593Smuzhiyun #define GC_CAP_CMSS 0x00000048 127*4882a593Smuzhiyun #define GC_CAP_CMDS 0x0000004C 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define GC_VCM_VIE 0x80000000 130*4882a593Smuzhiyun #define GC_VCM_CM 0x03000000 131*4882a593Smuzhiyun #define GC_VCM_VS_PAL 0x00000002 132*4882a593Smuzhiyun #define GC_CBM_OO 0x80000000 133*4882a593Smuzhiyun #define GC_CBM_HRV 0x00000010 134*4882a593Smuzhiyun #define GC_CBM_CBST 0x00000001 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Carmine specific */ 137*4882a593Smuzhiyun #define MB86297_DRAW_BASE 0x00020000 138*4882a593Smuzhiyun #define MB86297_DISP0_BASE 0x00100000 139*4882a593Smuzhiyun #define MB86297_DISP1_BASE 0x00140000 140*4882a593Smuzhiyun #define MB86297_WRBACK_BASE 0x00180000 141*4882a593Smuzhiyun #define MB86297_CAP0_BASE 0x00200000 142*4882a593Smuzhiyun #define MB86297_CAP1_BASE 0x00280000 143*4882a593Smuzhiyun #define MB86297_DRAMCTRL_BASE 0x00300000 144*4882a593Smuzhiyun #define MB86297_CTRL_BASE 0x00400000 145*4882a593Smuzhiyun #define MB86297_I2C_BASE 0x00500000 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define GC_CTRL_STATUS 0x00000000 148*4882a593Smuzhiyun #define GC_CTRL_INT_MASK 0x00000004 149*4882a593Smuzhiyun #define GC_CTRL_CLK_ENABLE 0x0000000c 150*4882a593Smuzhiyun #define GC_CTRL_SOFT_RST 0x00000010 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define GC_CTRL_CLK_EN_DRAM 0x00000001 153*4882a593Smuzhiyun #define GC_CTRL_CLK_EN_2D3D 0x00000002 154*4882a593Smuzhiyun #define GC_CTRL_CLK_EN_DISP0 0x00000020 155*4882a593Smuzhiyun #define GC_CTRL_CLK_EN_DISP1 0x00000040 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define GC_2D3D_REV 0x000004b4 158*4882a593Smuzhiyun #define GC_RE_REVISION 0x24240200 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* define enabled interrupts hereby */ 161*4882a593Smuzhiyun #define GC_CARMINE_INT_EN 0x00000004 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* DRAM controller */ 164*4882a593Smuzhiyun #define GC_DCTL_MODE_ADD 0x00000000 165*4882a593Smuzhiyun #define GC_DCTL_SETTIME1_EMODE 0x00000004 166*4882a593Smuzhiyun #define GC_DCTL_REFRESH_SETTIME2 0x00000008 167*4882a593Smuzhiyun #define GC_DCTL_RSV0_STATES 0x0000000C 168*4882a593Smuzhiyun #define GC_DCTL_RSV2_RSV1 0x00000010 169*4882a593Smuzhiyun #define GC_DCTL_DDRIF2_DDRIF1 0x00000014 170*4882a593Smuzhiyun #define GC_DCTL_IOCONT1_IOCONT0 0x00000024 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define GC_DCTL_STATES_MSK 0x0000000f 173*4882a593Smuzhiyun #define GC_DCTL_INIT_WAIT_CNT 3000 174*4882a593Smuzhiyun #define GC_DCTL_INIT_WAIT_INTERVAL 1 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* DRAM ctrl values for Carmine PCI Eval. board */ 177*4882a593Smuzhiyun #define GC_EVB_DCTL_MODE_ADD 0x012105c3 178*4882a593Smuzhiyun #define GC_EVB_DCTL_MODE_ADD_AFT_RST 0x002105c3 179*4882a593Smuzhiyun #define GC_EVB_DCTL_SETTIME1_EMODE 0x47498000 180*4882a593Smuzhiyun #define GC_EVB_DCTL_REFRESH_SETTIME2 0x00422a22 181*4882a593Smuzhiyun #define GC_EVB_DCTL_RSV0_STATES 0x00200003 182*4882a593Smuzhiyun #define GC_EVB_DCTL_RSV0_STATES_AFT_RST 0x00200002 183*4882a593Smuzhiyun #define GC_EVB_DCTL_RSV2_RSV1 0x0000000f 184*4882a593Smuzhiyun #define GC_EVB_DCTL_DDRIF2_DDRIF1 0x00556646 185*4882a593Smuzhiyun #define GC_EVB_DCTL_IOCONT1_IOCONT0 0x05550555 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define GC_DISP_REFCLK_533 533 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #endif 190