| /rk3399_ARM-atf/include/lib/ |
| H A D | mmio.h | 34 uint16_t set) in mmio_clrsetbits_16()
64 static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) in mmio_setbits_32()
71 uint32_t set) in mmio_clrsetbits_32()
76 static inline void mmio_setbits_64(uintptr_t addr, uint64_t set) in mmio_setbits_64()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/include/ |
| H A D | rk3399_mcu.h | 20 #define mmio_setbits_32(addr, set) \ argument
22 #define mmio_clrsetbits_32(addr, clear, set) \ argument
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm.c | 96 static void spm_ap_mdsrc_req(int set) in spm_ap_mdsrc_req()
127 static void spm_ap_gpueb_pll_control(int set) in spm_ap_gpueb_pll_control()
255 int mt_spm_hwctrl(uint32_t type, int set, void *priv) in mt_spm_hwctrl()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm.c | 98 static void spm_ap_mdsrc_req(int set) in spm_ap_mdsrc_req()
130 static void spm_ap_gpueb_pll_control(int set) in spm_ap_gpueb_pll_control()
267 int mt_spm_hwctrl(uint32_t type, int set, void *priv) in mt_spm_hwctrl()
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| /rk3399_ARM-atf/include/drivers/nxp/dcfg/ |
| H A D | scfg.h | 51 #define scfg_clrsetbits32(a, clear, set) \ argument
58 #define scfg_clrsetbits32(a, clear, set) \ argument
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| /rk3399_ARM-atf/drivers/imx/usdhc/ |
| H A D | imx_usdhc.h | 138 #define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (… argument
140 #define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set)) argument
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| /rk3399_ARM-atf/plat/socionext/synquacer/drivers/scpi/ |
| H A D | sq_scpi.h | 21 uint32_t set : 1; member
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 49 } set[NR_PMIC_WRAP_PHASE]; member
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_pmic_wrap.c | 54 } set[NR_PMIC_WRAP_PHASE]; member
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 49 } set[NR_PMIC_WRAP_PHASE]; member
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| /rk3399_ARM-atf/plat/mediatek/common/lpm_v2/ |
| H A D | mt_lp_rm.c | 153 int mt_lp_rm_do_hwctrl(unsigned int type, int set, void *priv) in mt_lp_rm_do_hwctrl()
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| /rk3399_ARM-atf/include/drivers/arm/css/ |
| H A D | css_scpi.h | 21 uint32_t set : 1; member
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| /rk3399_ARM-atf/plat/brcm/common/ |
| H A D | brcm_scpi.h | 21 uint32_t set : 1; member
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/ |
| H A D | spm_pmic_wrap.c | 52 } set[NR_PMIC_WRAP_PHASE]; member
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_pmic_wrap.c | 36 } set[NR_PMIC_WRAP_PHASE]; member
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| /rk3399_ARM-atf/drivers/brcm/ |
| H A D | iproc_gpio.c | 55 static void gpio_set_bit(uintptr_t base, unsigned int reg, int gpio, bool set) in gpio_set_bit()
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| /rk3399_ARM-atf/plat/brcm/board/stingray/driver/ |
| H A D | swreg.c | 45 #define UPDATE_POS_EDGE(data, set) ((data) | ((set) << 1)) argument
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_iossm_mailbox.c | 23 const bool set, in wait_for_bit()
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| /rk3399_ARM-atf/drivers/brcm/i2c/ |
| H A D | i2c.c | 116 uint32_t set) in iproc_i2c_reg_clearset()
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| /rk3399_ARM-atf/drivers/st/fmc/ |
| H A D | stm32_fmc2_nand.c | 331 static void stm32_fmc2_set_buswidth_16(bool set) in stm32_fmc2_set_buswidth_16()
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/gpio/ |
| H A D | mtgpio.h | 121 uint32_t set; member
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| /rk3399_ARM-atf/include/plat/marvell/odyssey/csr/ |
| H A D | ody-csrs-cst_shrd_funnel.h | 215 uint32_t set : 4; member
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| H A D | ody-csrs-gpio.h | 1324 uint64_t set : 64; member
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