Searched defs:pll_ctrl (Results 1 – 9 of 9) sorted by relevance
177 typedef struct pll_ctrl { struct178 u8 odr; /* 0x00 Output divider */179 u8 rsvd1;180 u8 cr; /* 0x02 Control */181 u8 rsvd2;182 u8 mdr; /* 0x04 Modulation Divider */183 u8 rsvd3;184 u8 fdr; /* 0x06 Feedback Divider */185 u8 rsvd4;
90 typedef struct pll_ctrl { struct91 u16 syncr; /* 0x00 synthesizer control register */92 u16 synsr; /* 0x02 synthesizer status register */
375 typedef struct pll_ctrl { struct376 u8 podr; /* 0x00 Output Divider Register */377 u8 res1[3];378 u8 pcr; /* 0x04 Control Register */379 u8 res2[3];380 u8 pmdr; /* 0x08 Modulation Divider Register */381 u8 res3[3];382 u8 pfdr; /* 0x0C Feedback Divider Register */383 u8 res4[3];
207 typedef struct pll_ctrl { struct208 u32 syncr; /* 0x00 synthesizer control register */209 u32 synsr; /* 0x04 synthesizer status register */
297 typedef struct pll_ctrl { struct298 u32 pcr; /* 0x00 Ctrl */299 u32 pdr; /* 0x04 Divider */300 u32 psr; /* 0x08 Status */
341 typedef struct pll_ctrl { struct342 u32 syncr;343 u32 synsr;
63 void __iomem *pll_ctrl; in usb_power_config() local
927 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra]; in rockchip_hdptx_phy_set_rate() local976 const struct tx_pll_ctrl *pll_ctrl = &tx_pll_ctrl_extra[bw_extra]; in rockchip_hdptx_phy_set_rate() local
179 u32 pll_ctrl; /* 0x208 */ member