| /rk3399_ARM-atf/drivers/delay_timer/ |
| H A D | generic_delay_timer.c | 51 void generic_delay_timer_init_args(uint32_t mult, uint32_t div) in generic_delay_timer_init_args()
73 unsigned int div = plat_get_syscnt_freq2(); in generic_delay_timer_init() local
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| /rk3399_ARM-atf/drivers/nxp/timer/ |
| H A D | nxp_timer.c | 60 static void delay_timer_init_args(uint32_t mult, uint32_t div) in delay_timer_init_args()
81 unsigned int div; in delay_timer_init() local
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| /rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/ |
| H A D | rk3568_clk.c | 32 #define CLKDIV_5BITS_SHF0(div) BITS_WITH_WMASK(div, 0x1f, 0) argument
33 #define CLKDIV_5BITS_SHF8(div) BITS_WITH_WMASK(div, 0x1f, 8) argument
35 #define CLKDIV_4BITS_SHF0(div) BITS_WITH_WMASK(div, 0xf, 0) argument
36 #define CLKDIV_2BITS_SHF4(div) BITS_WITH_WMASK(div, 0x3, 4) argument
281 struct pvtpll_table *div; in rk3568_apll_set_rate() local
382 int div = 0, ret = 0; in clk_cpu_set_rate() local
474 int div; in clk_scmi_gpu_get_rate() local
488 int div; in clk_gpu_set_rate() local
539 int div; in clk_scmi_npu_get_rate() local
553 int div; in clk_npu_set_rate() local
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/ |
| H A D | rk3588_clk.c | 60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) argument
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) argument
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) argument
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) argument
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) argument
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) argument
305 int div; in clk_cpul_set_rate() local
421 int src, div; in clk_scmi_cpul_get_rate() local
474 int div; in clk_cpub01_set_rate() local
591 int value, src, div; in clk_scmi_cpub01_get_rate() local
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3576/scmi/ |
| H A D | rk3576_clk.c | 60 #define CLKDIV_6BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3fU, shift) argument
61 #define CLKDIV_5BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1fU, shift) argument
62 #define CLKDIV_4BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0xfU, shift) argument
63 #define CLKDIV_3BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x7U, shift) argument
64 #define CLKDIV_2BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x3U, shift) argument
65 #define CLKDIV_1BITS_SHF(div, shift) BITS_WITH_WMASK(div, 0x1U, shift) argument
403 int div; in clk_cpul_set_rate() local
530 int src, div; in clk_scmi_cpul_get_rate() local
565 int div; in clk_cpub_set_rate() local
698 int value, src, div; in clk_scmi_cpub_get_rate() local
[all …]
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| /rk3399_ARM-atf/plat/rockchip/common/scmi/ |
| H A D | rockchip_common_clock.c | 59 unsigned long parent_rate, sel, div; in clk_scmi_common_get_rate() local
75 int i = 0, sel_mask, div_mask, best_sel = 0, best_div = 0, div; in clk_scmi_common_set_rate() local
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| /rk3399_ARM-atf/plat/socionext/uniphier/ |
| H A D | uniphier_console_setup.c | 52 uint32_t div; in uniphier_console_get_base() local
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| /rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/ |
| H A D | boot_init_dram_config.c | 1770 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) in boardcnf_get_brd_clk()
1801 void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) in boardcnf_get_ddr_mbps()
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| H A D | boot_init_dram.c | 1014 uint32_t div; in _f_scale() local
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| /rk3399_ARM-atf/plat/aspeed/ast2700/ |
| H A D | plat_bl31_setup.c | 143 uint32_t mul = 1, div = 1; in plat_get_pll_rate() local
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| /rk3399_ARM-atf/include/dt-bindings/clock/ |
| H A D | stm32mp21-clksrc.h | 47 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
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| H A D | stm32mp25-clksrc.h | 47 #define CLK_CFG(clk_id, sel, div, state) ((CMD_CLK << CMD_SHIFT) |\ argument
69 #define DIV_CFG(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
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| H A D | stm32mp13-clksrc.h | 68 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
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| H A D | stm32mp15-clksrc.h | 42 #define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ argument
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32-core.h | 25 uint16_t div; member
72 const struct div_cfg *div; member
252 uint8_t div; member
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| H A D | clk-stm32-core.c | 745 unsigned int div = 0U; in _clk_stm32_divider_recalc() local
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| /rk3399_ARM-atf/drivers/rpi3/sdhost/ |
| H A D | rpi3_sdhost.c | 396 uint32_t div; in rpi3_sdhost_set_clock() local
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| /rk3399_ARM-atf/drivers/imx/usdhc/ |
| H A D | imx_usdhc.c | 115 unsigned int pre_div = 1U, div = 1U; in imx_usdhc_set_clk() local
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| /rk3399_ARM-atf/include/lib/ |
| H A D | utils_def.h | 104 #define div_round_up(val, div) __extension__ ({ \ argument
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_clock.c | 219 uint8_t div:4; member
2557 uint32_t *div) in pm_api_clock_get_fixedfactor_params()
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| H A D | zynqmp_pm_api_sys.c | 1118 uint32_t *div) in pm_clock_get_fixedfactor_params()
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| /rk3399_ARM-atf/drivers/synopsys/emmc/ |
| H A D | dw_mmc.c | 160 int div; in dw_set_clk() local
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| /rk3399_ARM-atf/plat/imx/imx8ulp/ |
| H A D | dram.c | 570 static void set_cgc2_ddrclk(uint8_t src, uint8_t div) in set_cgc2_ddrclk()
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| /rk3399_ARM-atf/plat/intel/soc/common/drivers/qspi/ |
| H A D | cadence_qspi.c | 32 int cad_qspi_set_baudrate_div(uint32_t div) in cad_qspi_set_baudrate_div()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/ |
| H A D | dfs.c | 1505 uint32_t tmp, i, div, j; in gen_rk3399_phy_params() local
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