| /utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/include/ |
| H A D | drvGlobal.h | 106 #define _RV1(addr, value) (((addr) >> 8) & 0x3F), (U8)(addr), (U8)(value) argument
107 #define _RV2(addr, value) 0x40 + _RV1(addr, value), (U8)((value) >> 8) argument
108 #define _RV3(addr, value) 0x40 + _RV2(addr, value), (U8)((value) >> 16) argument
109 #define _RV4(addr, value) 0x40 + _RV3(addr, value), (U8)((value) >> 24) argument
112 #define _RV32_1(addr, value) (U8)(((addr) >> 16) & 0xFF),(U8)(((addr) >> 8) & 0xFF), (U8)(addr),… argument
113 #define _RV32_2(addr, value) 0x20 + _RV32_1(addr, value), (U8)((value) >> 8) argument
114 #define _RV32_3(addr, value) 0x20 + _RV32_2(addr, value), (U8)((value) >> 16) argument
115 #define _RV32_4(addr, value) 0x20 + _RV32_3(addr, value), (U8)((value) >> 24) argument
119 #define _RVM1(addr, value, mask) (((addr) >> 8) & 0x3F), (U8)(addr), (U8)(value), (U8)(mask) argument
120 #define _RVM2(addr, value, mask) 0x40 + _RVM1(addr, value, mask), (U8)((value) >> 8), (U8)((mask) >… argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/maserati/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/M7621/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/maldives/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/mainz/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/mustang/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/messi/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/manhattan/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/macan/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/M7821/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/maxim/sc/ |
| H A D | regSC.h | 126 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)) argument
127 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)) argument
129 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)) << 1)… argument
130 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)) << 1)… argument
132 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
133 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
135 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
136 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
140 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
141 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/hdmi/drv/mhl/ |
| H A D | mhl_hwreg_utility2.h | 113 #define RIU_READ_BYTE(addr) ( READ_BYTE( MHL_XC_RIU_BASE + (addr) ) ) argument
114 #define RIU_READ_2BYTE(addr) ( READ_WORD( MHL_XC_RIU_BASE + (addr) ) ) argument
115 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( MHL_XC_RIU_BASE + (addr), val) } argument
116 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( MHL_XC_RIU_BASE + (addr), val) } argument
119 #define PM_RIU_READ_BYTEM(addr) ( READ_BYTE( MHL_PM_RIU_BASE + (addr) ) ) argument
120 #define PM_RIU_READ_2BYTE(addr) ( READ_WORD( MHL_PM_RIU_BASE + (addr) ) ) argument
121 #define PM_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( MHL_PM_RIU_BASE + (addr), val) } argument
122 #define PM_RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( MHL_PM_RIU_BASE + (addr), val) } argument
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| /utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/source2/ |
| H A D | drvUsbMain_2.h | 135 #define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x80000000)) argument
136 #define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x80000000)) argument
143 #define KSEG02KSEG1(addr) ((void *)((U32)(addr) | 0xA0000000)) argument
150 #define KSEG12KSEG0(addr) ((void *)((U32)(((addr) & ~0x20000000) | 0x80000000))) argument
155 #define KSEG02KSEG1(addr) MsOS_PA2KSEG1(MsOS_VA2PA((U32)addr)) argument
158 #define KSEG12KSEG0(addr) MsOS_PA2KSEG0(MsOS_VA2PA((U32)addr)) argument
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| /utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/source3/ |
| H A D | drvUsbMain_3.h | 135 #define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x80000000)) argument
136 #define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x80000000)) argument
143 #define KSEG02KSEG1(addr) ((void *)((U32)(addr) | 0xA0000000)) argument
150 #define KSEG12KSEG0(addr) ((void *)((U32)(((addr) & ~0x20000000) | 0x80000000))) argument
155 #define KSEG02KSEG1(addr) MsOS_PA2KSEG1(MsOS_VA2PA((U32)addr)) argument
158 #define KSEG12KSEG0(addr) MsOS_PA2KSEG0(MsOS_VA2PA((U32)addr)) argument
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| /utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/source4/ |
| H A D | drvUsbMain_4.h | 135 #define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x80000000)) argument
136 #define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x80000000)) argument
143 #define KSEG02KSEG1(addr) ((void *)((U32)(addr) | 0xA0000000)) argument
150 #define KSEG12KSEG0(addr) ((void *)((U32)(((addr) & ~0x20000000) | 0x80000000))) argument
155 #define KSEG02KSEG1(addr) MsOS_PA2KSEG1(MsOS_VA2PA((U32)addr)) argument
158 #define KSEG12KSEG0(addr) MsOS_PA2KSEG0(MsOS_VA2PA((U32)addr)) argument
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| /utopia/UTPA2-700.0.x/modules/usb/drv/usbhost/source/ |
| H A D | drvUsbMain.h | 141 #define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x80000000)) argument
142 #define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x80000000)) argument
150 #define KSEG02KSEG1(addr) ((void *)((U32)(addr) | 0xA0000000)) argument
157 #define KSEG12KSEG0(addr) ((void *)((U32)(((addr) & ~0x20000000) | 0x80000000))) argument
162 #define KSEG02KSEG1(addr) MsOS_PA2KSEG1(MsOS_VA2PA((U32)addr)) argument
165 #define KSEG12KSEG0(addr) MsOS_PA2KSEG0(MsOS_VA2PA((U32)addr)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/curry/sc/ |
| H A D | regSC.h | 127 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)… argument
128 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)… argument
130 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1… argument
131 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1… argument
133 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
134 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
136 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
137 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
141 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
142 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/sc/hal/kano/sc/ |
| H A D | regSC.h | 127 #define UART1_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1)… argument
128 #define UART2_READ(addr) READ_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1)… argument
130 #define UART1_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE1 + ((addr) << 1… argument
131 #define UART2_WRITE(addr, val) WRITE_BYTE(RIU_BUS_BASE + ((REG_SC_BASE2 + ((addr) << 1… argument
133 #define UART1_READ(addr) READ_BYTE(REG_SC_BASE1 + ((addr) << 2)) argument
134 #define UART2_READ(addr) READ_BYTE(REG_SC_BASE2 + ((addr) << 2)) argument
136 #define UART1_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE1 + ((addr) << 2)), (val)) argument
137 #define UART2_WRITE(addr, val) WRITE_BYTE((REG_SC_BASE2 + ((addr) << 2)), (val)) argument
141 #define UART1_OR(addr, val) UART1_WRITE(addr, UART1_READ(addr) | (val)) argument
142 #define UART1_AND(addr, val) UART1_WRITE(addr, UART1_READ(addr) & (val)) argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/mooney/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/maserati/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/maldives/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/M7821/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/messi/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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| /utopia/UTPA2-700.0.x/modules/flash/hal/manhattan/flash/nor/ |
| H A D | halPARFLASH.c | 123 #define PFSH_READ(addr) READ_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2))) argument
124 #define PFSH_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PfshBaseAddr + (addr << 2)), (… argument
125 #define PFSH_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK((_hal_pfsh.u32PfshBaseAddr + (addr << 2… argument
127 #define CHIPTOP_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32ChipBaseAddr + (addr << 2))… argument
128 #define CHIPTOP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32ChipBaseAddr + ((addr)<… argument
130 #define PIU_READ(addr) READ_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2))) argument
131 #define PIU_WRITE(addr, val) WRITE_WORD((_hal_pfsh.u32PiuBaseAddr + (addr << 2)), (v… argument
132 #define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_pfsh.u32PiuBaseAddr + ((addr)<<2),… argument
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