1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * - Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * - Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * - Neither the name of the Altera Corporation nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <common.h> 29 #include <asm/io.h> 30 #include <asm/errno.h> 31 #include <wait_bit.h> 32 #include "cadence_qspi.h" 33 34 #define CQSPI_REG_POLL_US (1) /* 1us */ 35 #define CQSPI_REG_RETRY (10000) 36 #define CQSPI_POLL_IDLE_RETRY (3) 37 38 #define CQSPI_FIFO_WIDTH (4) 39 40 #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) 41 42 /* Transfer mode */ 43 #define CQSPI_INST_TYPE_SINGLE (0) 44 #define CQSPI_INST_TYPE_DUAL (1) 45 #define CQSPI_INST_TYPE_QUAD (2) 46 47 #define CQSPI_STIG_DATA_LEN_MAX (8) 48 49 #define CQSPI_DUMMY_CLKS_PER_BYTE (8) 50 #define CQSPI_DUMMY_BYTES_MAX (4) 51 52 53 #define CQSPI_REG_SRAM_FILL_THRESHOLD \ 54 ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) 55 /**************************************************************************** 56 * Controller's configuration and status register (offset from QSPI_BASE) 57 ****************************************************************************/ 58 #define CQSPI_REG_CONFIG 0x00 59 #define CQSPI_REG_CONFIG_CLK_POL_LSB 1 60 #define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 61 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 62 #define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7) 63 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 64 #define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) 65 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 66 #define CQSPI_REG_CONFIG_BAUD_LSB 19 67 #define CQSPI_REG_CONFIG_IDLE_LSB 31 68 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 69 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 70 71 #define CQSPI_REG_RD_INSTR 0x04 72 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 73 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 74 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 75 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 76 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 77 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 78 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 79 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 80 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 81 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 82 83 #define CQSPI_REG_WR_INSTR 0x08 84 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 85 86 #define CQSPI_REG_DELAY 0x0C 87 #define CQSPI_REG_DELAY_TSLCH_LSB 0 88 #define CQSPI_REG_DELAY_TCHSH_LSB 8 89 #define CQSPI_REG_DELAY_TSD2D_LSB 16 90 #define CQSPI_REG_DELAY_TSHSL_LSB 24 91 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 92 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 93 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 94 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 95 96 #define CQSPI_READLCAPTURE 0x10 97 #define CQSPI_READLCAPTURE_BYPASS_LSB 0 98 #define CQSPI_READLCAPTURE_DELAY_LSB 1 99 #define CQSPI_READLCAPTURE_DELAY_MASK 0xF 100 101 #define CQSPI_REG_SIZE 0x14 102 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 103 #define CQSPI_REG_SIZE_PAGE_LSB 4 104 #define CQSPI_REG_SIZE_BLOCK_LSB 16 105 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 106 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 107 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 108 109 #define CQSPI_REG_SRAMPARTITION 0x18 110 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 111 112 #define CQSPI_REG_REMAP 0x24 113 #define CQSPI_REG_MODE_BIT 0x28 114 115 #define CQSPI_REG_SDRAMLEVEL 0x2C 116 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 117 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 118 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 119 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 120 121 #define CQSPI_REG_IRQSTATUS 0x40 122 #define CQSPI_REG_IRQMASK 0x44 123 124 #define CQSPI_REG_INDIRECTRD 0x60 125 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 126 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 127 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2) 128 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 129 130 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 131 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 132 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 133 134 #define CQSPI_REG_CMDCTRL 0x90 135 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 136 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 137 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 138 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 139 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 140 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 141 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 142 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 143 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 144 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 145 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 146 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 147 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 148 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 149 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF 150 151 #define CQSPI_REG_INDIRECTWR 0x70 152 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 153 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 154 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2) 155 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 156 157 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 158 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 159 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 160 161 #define CQSPI_REG_CMDADDRESS 0x94 162 #define CQSPI_REG_CMDREADDATALOWER 0xA0 163 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 164 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 165 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 166 167 #define CQSPI_REG_IS_IDLE(base) \ 168 ((readl(base + CQSPI_REG_CONFIG) >> \ 169 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) 170 171 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \ 172 ((((tdelay_ns) - (tsclk_ns)) / (tref_ns))) 173 174 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ 175 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ 176 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) 177 178 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ 179 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ 180 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) 181 182 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, 183 unsigned int addr_width) 184 { 185 unsigned int addr; 186 187 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2]; 188 189 if (addr_width == 4) 190 addr = (addr << 8) | addr_buf[3]; 191 192 return addr; 193 } 194 195 void cadence_qspi_apb_controller_enable(void *reg_base) 196 { 197 unsigned int reg; 198 reg = readl(reg_base + CQSPI_REG_CONFIG); 199 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 200 writel(reg, reg_base + CQSPI_REG_CONFIG); 201 return; 202 } 203 204 void cadence_qspi_apb_controller_disable(void *reg_base) 205 { 206 unsigned int reg; 207 reg = readl(reg_base + CQSPI_REG_CONFIG); 208 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 209 writel(reg, reg_base + CQSPI_REG_CONFIG); 210 return; 211 } 212 213 /* Return 1 if idle, otherwise return 0 (busy). */ 214 static unsigned int cadence_qspi_wait_idle(void *reg_base) 215 { 216 unsigned int start, count = 0; 217 /* timeout in unit of ms */ 218 unsigned int timeout = 5000; 219 220 start = get_timer(0); 221 for ( ; get_timer(start) < timeout ; ) { 222 if (CQSPI_REG_IS_IDLE(reg_base)) 223 count++; 224 else 225 count = 0; 226 /* 227 * Ensure the QSPI controller is in true idle state after 228 * reading back the same idle status consecutively 229 */ 230 if (count >= CQSPI_POLL_IDLE_RETRY) 231 return 1; 232 } 233 234 /* Timeout, still in busy mode. */ 235 printf("QSPI: QSPI is still busy after poll for %d times.\n", 236 CQSPI_REG_RETRY); 237 return 0; 238 } 239 240 void cadence_qspi_apb_readdata_capture(void *reg_base, 241 unsigned int bypass, unsigned int delay) 242 { 243 unsigned int reg; 244 cadence_qspi_apb_controller_disable(reg_base); 245 246 reg = readl(reg_base + CQSPI_READLCAPTURE); 247 248 if (bypass) 249 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB); 250 else 251 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB); 252 253 reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK 254 << CQSPI_READLCAPTURE_DELAY_LSB); 255 256 reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK) 257 << CQSPI_READLCAPTURE_DELAY_LSB); 258 259 writel(reg, reg_base + CQSPI_READLCAPTURE); 260 261 cadence_qspi_apb_controller_enable(reg_base); 262 return; 263 } 264 265 void cadence_qspi_apb_config_baudrate_div(void *reg_base, 266 unsigned int ref_clk_hz, unsigned int sclk_hz) 267 { 268 unsigned int reg; 269 unsigned int div; 270 271 cadence_qspi_apb_controller_disable(reg_base); 272 reg = readl(reg_base + CQSPI_REG_CONFIG); 273 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 274 275 div = ref_clk_hz / sclk_hz; 276 277 if (div > 32) 278 div = 32; 279 280 /* Check if even number. */ 281 if ((div & 1)) { 282 div = (div / 2); 283 } else { 284 if (ref_clk_hz % sclk_hz) 285 /* ensure generated SCLK doesn't exceed user 286 specified sclk_hz */ 287 div = (div / 2); 288 else 289 div = (div / 2) - 1; 290 } 291 292 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, 293 ref_clk_hz, sclk_hz, div); 294 295 div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; 296 reg |= div; 297 writel(reg, reg_base + CQSPI_REG_CONFIG); 298 299 cadence_qspi_apb_controller_enable(reg_base); 300 return; 301 } 302 303 void cadence_qspi_apb_set_clk_mode(void *reg_base, 304 unsigned int clk_pol, unsigned int clk_pha) 305 { 306 unsigned int reg; 307 308 cadence_qspi_apb_controller_disable(reg_base); 309 reg = readl(reg_base + CQSPI_REG_CONFIG); 310 reg &= ~(1 << 311 (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); 312 313 reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); 314 reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); 315 316 writel(reg, reg_base + CQSPI_REG_CONFIG); 317 318 cadence_qspi_apb_controller_enable(reg_base); 319 return; 320 } 321 322 void cadence_qspi_apb_chipselect(void *reg_base, 323 unsigned int chip_select, unsigned int decoder_enable) 324 { 325 unsigned int reg; 326 327 cadence_qspi_apb_controller_disable(reg_base); 328 329 debug("%s : chipselect %d decode %d\n", __func__, chip_select, 330 decoder_enable); 331 332 reg = readl(reg_base + CQSPI_REG_CONFIG); 333 /* docoder */ 334 if (decoder_enable) { 335 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 336 } else { 337 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 338 /* Convert CS if without decoder. 339 * CS0 to 4b'1110 340 * CS1 to 4b'1101 341 * CS2 to 4b'1011 342 * CS3 to 4b'0111 343 */ 344 chip_select = 0xF & ~(1 << chip_select); 345 } 346 347 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 348 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 349 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 350 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 351 writel(reg, reg_base + CQSPI_REG_CONFIG); 352 353 cadence_qspi_apb_controller_enable(reg_base); 354 return; 355 } 356 357 void cadence_qspi_apb_delay(void *reg_base, 358 unsigned int ref_clk, unsigned int sclk_hz, 359 unsigned int tshsl_ns, unsigned int tsd2d_ns, 360 unsigned int tchsh_ns, unsigned int tslch_ns) 361 { 362 unsigned int ref_clk_ns; 363 unsigned int sclk_ns; 364 unsigned int tshsl, tchsh, tslch, tsd2d; 365 unsigned int reg; 366 367 cadence_qspi_apb_controller_disable(reg_base); 368 369 /* Convert to ns. */ 370 ref_clk_ns = (1000000000) / ref_clk; 371 372 /* Convert to ns. */ 373 sclk_ns = (1000000000) / sclk_hz; 374 375 /* Plus 1 to round up 1 clock cycle. */ 376 tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; 377 tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; 378 tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; 379 tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; 380 381 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 382 << CQSPI_REG_DELAY_TSHSL_LSB); 383 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 384 << CQSPI_REG_DELAY_TCHSH_LSB); 385 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) 386 << CQSPI_REG_DELAY_TSLCH_LSB); 387 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 388 << CQSPI_REG_DELAY_TSD2D_LSB); 389 writel(reg, reg_base + CQSPI_REG_DELAY); 390 391 cadence_qspi_apb_controller_enable(reg_base); 392 return; 393 } 394 395 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) 396 { 397 unsigned reg; 398 399 cadence_qspi_apb_controller_disable(plat->regbase); 400 401 /* Configure the device size and address bytes */ 402 reg = readl(plat->regbase + CQSPI_REG_SIZE); 403 /* Clear the previous value */ 404 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); 405 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); 406 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); 407 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); 408 writel(reg, plat->regbase + CQSPI_REG_SIZE); 409 410 /* Configure the remap address register, no remap */ 411 writel(0, plat->regbase + CQSPI_REG_REMAP); 412 413 /* Indirect mode configurations */ 414 writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); 415 416 /* Disable all interrupts */ 417 writel(0, plat->regbase + CQSPI_REG_IRQMASK); 418 419 cadence_qspi_apb_controller_enable(plat->regbase); 420 return; 421 } 422 423 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, 424 unsigned int reg) 425 { 426 unsigned int retry = CQSPI_REG_RETRY; 427 428 /* Write the CMDCTRL without start execution. */ 429 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 430 /* Start execute */ 431 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 432 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 433 434 while (retry--) { 435 reg = readl(reg_base + CQSPI_REG_CMDCTRL); 436 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) 437 break; 438 udelay(1); 439 } 440 441 if (!retry) { 442 printf("QSPI: flash command execution timeout\n"); 443 return -EIO; 444 } 445 446 /* Polling QSPI idle status. */ 447 if (!cadence_qspi_wait_idle(reg_base)) 448 return -EIO; 449 450 return 0; 451 } 452 453 /* For command RDID, RDSR. */ 454 int cadence_qspi_apb_command_read(void *reg_base, 455 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, 456 u8 *rxbuf) 457 { 458 unsigned int reg; 459 unsigned int read_len; 460 int status; 461 462 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) { 463 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n", 464 cmdlen, rxlen); 465 return -EINVAL; 466 } 467 468 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; 469 470 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 471 472 /* 0 means 1 byte. */ 473 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 474 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 475 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); 476 if (status != 0) 477 return status; 478 479 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 480 481 /* Put the read value into rx_buf */ 482 read_len = (rxlen > 4) ? 4 : rxlen; 483 memcpy(rxbuf, ®, read_len); 484 rxbuf += read_len; 485 486 if (rxlen > 4) { 487 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 488 489 read_len = rxlen - read_len; 490 memcpy(rxbuf, ®, read_len); 491 } 492 return 0; 493 } 494 495 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ 496 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, 497 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) 498 { 499 unsigned int reg = 0; 500 unsigned int addr_value; 501 unsigned int wr_data; 502 unsigned int wr_len; 503 504 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) { 505 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n", 506 cmdlen, txlen); 507 return -EINVAL; 508 } 509 510 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; 511 512 if (cmdlen == 4 || cmdlen == 5) { 513 /* Command with address */ 514 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 515 /* Number of bytes to write. */ 516 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 517 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 518 /* Get address */ 519 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], 520 cmdlen >= 5 ? 4 : 3); 521 522 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS); 523 } 524 525 if (txlen) { 526 /* writing data = yes */ 527 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 528 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 529 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 530 531 wr_len = txlen > 4 ? 4 : txlen; 532 memcpy(&wr_data, txbuf, wr_len); 533 writel(wr_data, reg_base + 534 CQSPI_REG_CMDWRITEDATALOWER); 535 536 if (txlen > 4) { 537 txbuf += wr_len; 538 wr_len = txlen - wr_len; 539 memcpy(&wr_data, txbuf, wr_len); 540 writel(wr_data, reg_base + 541 CQSPI_REG_CMDWRITEDATAUPPER); 542 } 543 } 544 545 /* Execute the command */ 546 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg); 547 } 548 549 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ 550 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, 551 unsigned int cmdlen, const u8 *cmdbuf) 552 { 553 unsigned int reg; 554 unsigned int rd_reg; 555 unsigned int addr_value; 556 unsigned int dummy_clk; 557 unsigned int dummy_bytes; 558 unsigned int addr_bytes; 559 560 /* 561 * Identify addr_byte. All NOR flash device drivers are using fast read 562 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte. 563 * With that, the length is in value of 5 or 6. Only FRAM chip from 564 * ramtron using normal read (which won't need dummy byte). 565 * Unlikely NOR flash using normal read due to performance issue. 566 */ 567 if (cmdlen >= 5) 568 /* to cater fast read where cmd + addr + dummy */ 569 addr_bytes = cmdlen - 2; 570 else 571 /* for normal read (only ramtron as of now) */ 572 addr_bytes = cmdlen - 1; 573 574 /* Setup the indirect trigger address */ 575 writel((u32)plat->ahbbase, 576 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); 577 578 /* Configure the opcode */ 579 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; 580 581 #if (CONFIG_SPI_FLASH_QUAD == 1) 582 /* Instruction and address at DQ0, data at DQ0-3. */ 583 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 584 #endif 585 586 /* Get address */ 587 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); 588 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); 589 590 /* The remaining lenght is dummy bytes. */ 591 dummy_bytes = cmdlen - addr_bytes - 1; 592 if (dummy_bytes) { 593 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) 594 dummy_bytes = CQSPI_DUMMY_BYTES_MAX; 595 596 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); 597 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) 598 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); 599 #else 600 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); 601 #endif 602 603 /* Convert to clock cycles. */ 604 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; 605 /* Need to minus the mode byte (8 clocks). */ 606 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE; 607 608 if (dummy_clk) 609 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 610 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 611 } 612 613 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR); 614 615 /* set device size */ 616 reg = readl(plat->regbase + CQSPI_REG_SIZE); 617 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 618 reg |= (addr_bytes - 1); 619 writel(reg, plat->regbase + CQSPI_REG_SIZE); 620 return 0; 621 } 622 623 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat) 624 { 625 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL); 626 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 627 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 628 } 629 630 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat) 631 { 632 unsigned int timeout = 10000; 633 u32 reg; 634 635 while (timeout--) { 636 reg = cadence_qspi_get_rd_sram_level(plat); 637 if (reg) 638 return reg; 639 udelay(1); 640 } 641 642 return -ETIMEDOUT; 643 } 644 645 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, 646 unsigned int n_rx, u8 *rxbuf) 647 { 648 unsigned int remaining = n_rx; 649 unsigned int bytes_to_read = 0; 650 int ret; 651 652 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); 653 654 /* Start the indirect read transfer */ 655 writel(CQSPI_REG_INDIRECTRD_START_MASK, 656 plat->regbase + CQSPI_REG_INDIRECTRD); 657 658 while (remaining > 0) { 659 ret = cadence_qspi_wait_for_data(plat); 660 if (ret < 0) { 661 printf("Indirect write timed out (%i)\n", ret); 662 goto failrd; 663 } 664 665 bytes_to_read = ret; 666 667 while (bytes_to_read != 0) { 668 bytes_to_read *= CQSPI_FIFO_WIDTH; 669 bytes_to_read = bytes_to_read > remaining ? 670 remaining : bytes_to_read; 671 /* Handle non-4-byte aligned access to avoid data abort. */ 672 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4)) 673 readsb(plat->ahbbase, rxbuf, bytes_to_read); 674 else 675 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2); 676 rxbuf += bytes_to_read; 677 remaining -= bytes_to_read; 678 bytes_to_read = cadence_qspi_get_rd_sram_level(plat); 679 } 680 } 681 682 /* Check indirect done status */ 683 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD, 684 CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0); 685 if (ret) { 686 printf("Indirect read completion error (%i)\n", ret); 687 goto failrd; 688 } 689 690 /* Clear indirect completion status */ 691 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 692 plat->regbase + CQSPI_REG_INDIRECTRD); 693 694 return 0; 695 696 failrd: 697 /* Cancel the indirect read */ 698 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 699 plat->regbase + CQSPI_REG_INDIRECTRD); 700 return ret; 701 } 702 703 /* Opcode + Address (3/4 bytes) */ 704 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, 705 unsigned int cmdlen, const u8 *cmdbuf) 706 { 707 unsigned int reg; 708 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; 709 710 if (cmdlen < 4 || cmdbuf == NULL) { 711 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n", 712 cmdlen, (unsigned int)cmdbuf); 713 return -EINVAL; 714 } 715 /* Setup the indirect trigger address */ 716 writel((u32)plat->ahbbase, 717 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); 718 719 /* Configure the opcode */ 720 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; 721 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); 722 723 /* Setup write address. */ 724 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); 725 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); 726 727 reg = readl(plat->regbase + CQSPI_REG_SIZE); 728 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 729 reg |= (addr_bytes - 1); 730 writel(reg, plat->regbase + CQSPI_REG_SIZE); 731 return 0; 732 } 733 734 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, 735 unsigned int n_tx, const u8 *txbuf) 736 { 737 unsigned int page_size = plat->page_size; 738 unsigned int remaining = n_tx; 739 unsigned int write_bytes; 740 int ret; 741 742 /* Configure the indirect read transfer bytes */ 743 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); 744 745 /* Start the indirect write transfer */ 746 writel(CQSPI_REG_INDIRECTWR_START_MASK, 747 plat->regbase + CQSPI_REG_INDIRECTWR); 748 749 while (remaining > 0) { 750 write_bytes = remaining > page_size ? page_size : remaining; 751 /* Handle non-4-byte aligned access to avoid data abort. */ 752 if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) 753 writesb(plat->ahbbase, txbuf, write_bytes); 754 else 755 writesl(plat->ahbbase, txbuf, write_bytes >> 2); 756 757 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, 758 CQSPI_REG_SDRAMLEVEL_WR_MASK << 759 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0); 760 if (ret) { 761 printf("Indirect write timed out (%i)\n", ret); 762 goto failwr; 763 } 764 765 txbuf += write_bytes; 766 remaining -= write_bytes; 767 } 768 769 /* Check indirect done status */ 770 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR, 771 CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0); 772 if (ret) { 773 printf("Indirect write completion error (%i)\n", ret); 774 goto failwr; 775 } 776 777 /* Clear indirect completion status */ 778 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, 779 plat->regbase + CQSPI_REG_INDIRECTWR); 780 return 0; 781 782 failwr: 783 /* Cancel the indirect write */ 784 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 785 plat->regbase + CQSPI_REG_INDIRECTWR); 786 return ret; 787 } 788 789 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) 790 { 791 unsigned int reg; 792 793 /* enter XiP mode immediately and enable direct mode */ 794 reg = readl(reg_base + CQSPI_REG_CONFIG); 795 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 796 reg |= CQSPI_REG_CONFIG_DIRECT_MASK; 797 reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; 798 writel(reg, reg_base + CQSPI_REG_CONFIG); 799 800 /* keep the XiP mode */ 801 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT); 802 803 /* Enable mode bit at devrd */ 804 reg = readl(reg_base + CQSPI_REG_RD_INSTR); 805 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); 806 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 807 } 808