1 /* 2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * - Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * - Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * - Neither the name of the Altera Corporation nor the 13 * names of its contributors may be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY 20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <common.h> 29 #include <asm/io.h> 30 #include <linux/errno.h> 31 #include <wait_bit.h> 32 #include <spi.h> 33 #include "cadence_qspi.h" 34 35 #define CQSPI_REG_POLL_US (1) /* 1us */ 36 #define CQSPI_REG_RETRY (10000) 37 #define CQSPI_POLL_IDLE_RETRY (3) 38 39 #define CQSPI_FIFO_WIDTH (4) 40 41 #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50) 42 43 /* Transfer mode */ 44 #define CQSPI_INST_TYPE_SINGLE (0) 45 #define CQSPI_INST_TYPE_DUAL (1) 46 #define CQSPI_INST_TYPE_QUAD (2) 47 48 #define CQSPI_STIG_DATA_LEN_MAX (8) 49 50 #define CQSPI_DUMMY_CLKS_PER_BYTE (8) 51 #define CQSPI_DUMMY_BYTES_MAX (4) 52 53 54 #define CQSPI_REG_SRAM_FILL_THRESHOLD \ 55 ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) 56 /**************************************************************************** 57 * Controller's configuration and status register (offset from QSPI_BASE) 58 ****************************************************************************/ 59 #define CQSPI_REG_CONFIG 0x00 60 #define CQSPI_REG_CONFIG_CLK_POL_LSB 1 61 #define CQSPI_REG_CONFIG_CLK_PHA_LSB 2 62 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) 63 #define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7) 64 #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) 65 #define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18) 66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 67 #define CQSPI_REG_CONFIG_BAUD_LSB 19 68 #define CQSPI_REG_CONFIG_IDLE_LSB 31 69 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF 70 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF 71 72 #define CQSPI_REG_RD_INSTR 0x04 73 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0 74 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8 75 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12 76 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16 77 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20 78 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24 79 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3 80 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3 81 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3 82 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F 83 84 #define CQSPI_REG_WR_INSTR 0x08 85 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 86 87 #define CQSPI_REG_DELAY 0x0C 88 #define CQSPI_REG_DELAY_TSLCH_LSB 0 89 #define CQSPI_REG_DELAY_TCHSH_LSB 8 90 #define CQSPI_REG_DELAY_TSD2D_LSB 16 91 #define CQSPI_REG_DELAY_TSHSL_LSB 24 92 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF 93 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF 94 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF 95 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF 96 97 #define CQSPI_READLCAPTURE 0x10 98 #define CQSPI_READLCAPTURE_BYPASS_LSB 0 99 #define CQSPI_READLCAPTURE_DELAY_LSB 1 100 #define CQSPI_READLCAPTURE_DELAY_MASK 0xF 101 102 #define CQSPI_REG_SIZE 0x14 103 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 104 #define CQSPI_REG_SIZE_PAGE_LSB 4 105 #define CQSPI_REG_SIZE_BLOCK_LSB 16 106 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF 107 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF 108 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F 109 110 #define CQSPI_REG_SRAMPARTITION 0x18 111 #define CQSPI_REG_INDIRECTTRIGGER 0x1C 112 113 #define CQSPI_REG_REMAP 0x24 114 #define CQSPI_REG_MODE_BIT 0x28 115 116 #define CQSPI_REG_SDRAMLEVEL 0x2C 117 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0 118 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16 119 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF 120 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF 121 122 #define CQSPI_REG_IRQSTATUS 0x40 123 #define CQSPI_REG_IRQMASK 0x44 124 125 #define CQSPI_REG_INDIRECTRD 0x60 126 #define CQSPI_REG_INDIRECTRD_START_MASK BIT(0) 127 #define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1) 128 #define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2) 129 #define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5) 130 131 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64 132 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68 133 #define CQSPI_REG_INDIRECTRDBYTES 0x6C 134 135 #define CQSPI_REG_CMDCTRL 0x90 136 #define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0) 137 #define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1) 138 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7 139 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12 140 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15 141 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16 142 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19 143 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20 144 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23 145 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24 146 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F 147 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7 148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3 149 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7 150 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF 151 152 #define CQSPI_REG_INDIRECTWR 0x70 153 #define CQSPI_REG_INDIRECTWR_START_MASK BIT(0) 154 #define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1) 155 #define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2) 156 #define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5) 157 158 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74 159 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78 160 #define CQSPI_REG_INDIRECTWRBYTES 0x7C 161 162 #define CQSPI_REG_CMDADDRESS 0x94 163 #define CQSPI_REG_CMDREADDATALOWER 0xA0 164 #define CQSPI_REG_CMDREADDATAUPPER 0xA4 165 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 166 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC 167 168 #define CQSPI_REG_IS_IDLE(base) \ 169 ((readl(base + CQSPI_REG_CONFIG) >> \ 170 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1) 171 172 #define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \ 173 ((((tdelay_ns) - (tsclk_ns)) / (tref_ns))) 174 175 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ 176 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ 177 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK) 178 179 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ 180 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \ 181 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK) 182 183 static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf, 184 unsigned int addr_width) 185 { 186 unsigned int addr; 187 188 addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2]; 189 190 if (addr_width == 4) 191 addr = (addr << 8) | addr_buf[3]; 192 193 return addr; 194 } 195 196 void cadence_qspi_apb_controller_enable(void *reg_base) 197 { 198 unsigned int reg; 199 reg = readl(reg_base + CQSPI_REG_CONFIG); 200 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 201 writel(reg, reg_base + CQSPI_REG_CONFIG); 202 return; 203 } 204 205 void cadence_qspi_apb_controller_disable(void *reg_base) 206 { 207 unsigned int reg; 208 reg = readl(reg_base + CQSPI_REG_CONFIG); 209 reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; 210 writel(reg, reg_base + CQSPI_REG_CONFIG); 211 return; 212 } 213 214 /* Return 1 if idle, otherwise return 0 (busy). */ 215 static unsigned int cadence_qspi_wait_idle(void *reg_base) 216 { 217 unsigned int start, count = 0; 218 /* timeout in unit of ms */ 219 unsigned int timeout = 5000; 220 221 start = get_timer(0); 222 for ( ; get_timer(start) < timeout ; ) { 223 if (CQSPI_REG_IS_IDLE(reg_base)) 224 count++; 225 else 226 count = 0; 227 /* 228 * Ensure the QSPI controller is in true idle state after 229 * reading back the same idle status consecutively 230 */ 231 if (count >= CQSPI_POLL_IDLE_RETRY) 232 return 1; 233 } 234 235 /* Timeout, still in busy mode. */ 236 printf("QSPI: QSPI is still busy after poll for %d times.\n", 237 CQSPI_REG_RETRY); 238 return 0; 239 } 240 241 void cadence_qspi_apb_readdata_capture(void *reg_base, 242 unsigned int bypass, unsigned int delay) 243 { 244 unsigned int reg; 245 cadence_qspi_apb_controller_disable(reg_base); 246 247 reg = readl(reg_base + CQSPI_READLCAPTURE); 248 249 if (bypass) 250 reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB); 251 else 252 reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB); 253 254 reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK 255 << CQSPI_READLCAPTURE_DELAY_LSB); 256 257 reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK) 258 << CQSPI_READLCAPTURE_DELAY_LSB); 259 260 writel(reg, reg_base + CQSPI_READLCAPTURE); 261 262 cadence_qspi_apb_controller_enable(reg_base); 263 return; 264 } 265 266 void cadence_qspi_apb_config_baudrate_div(void *reg_base, 267 unsigned int ref_clk_hz, unsigned int sclk_hz) 268 { 269 unsigned int reg; 270 unsigned int div; 271 272 cadence_qspi_apb_controller_disable(reg_base); 273 reg = readl(reg_base + CQSPI_REG_CONFIG); 274 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB); 275 276 /* 277 * The baud_div field in the config reg is 4 bits, and the ref clock is 278 * divided by 2 * (baud_div + 1). Round up the divider to ensure the 279 * SPI clock rate is less than or equal to the requested clock rate. 280 */ 281 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1; 282 283 /* ensure the baud rate doesn't exceed the max value */ 284 if (div > CQSPI_REG_CONFIG_BAUD_MASK) 285 div = CQSPI_REG_CONFIG_BAUD_MASK; 286 287 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__, 288 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1))); 289 290 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); 291 writel(reg, reg_base + CQSPI_REG_CONFIG); 292 293 cadence_qspi_apb_controller_enable(reg_base); 294 return; 295 } 296 297 void cadence_qspi_apb_set_clk_mode(void *reg_base, 298 unsigned int clk_pol, unsigned int clk_pha) 299 { 300 unsigned int reg; 301 302 cadence_qspi_apb_controller_disable(reg_base); 303 reg = readl(reg_base + CQSPI_REG_CONFIG); 304 reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB); 305 reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB); 306 307 reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); 308 reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB); 309 310 writel(reg, reg_base + CQSPI_REG_CONFIG); 311 312 cadence_qspi_apb_controller_enable(reg_base); 313 return; 314 } 315 316 void cadence_qspi_apb_chipselect(void *reg_base, 317 unsigned int chip_select, unsigned int decoder_enable) 318 { 319 unsigned int reg; 320 321 cadence_qspi_apb_controller_disable(reg_base); 322 323 debug("%s : chipselect %d decode %d\n", __func__, chip_select, 324 decoder_enable); 325 326 reg = readl(reg_base + CQSPI_REG_CONFIG); 327 /* docoder */ 328 if (decoder_enable) { 329 reg |= CQSPI_REG_CONFIG_DECODE_MASK; 330 } else { 331 reg &= ~CQSPI_REG_CONFIG_DECODE_MASK; 332 /* Convert CS if without decoder. 333 * CS0 to 4b'1110 334 * CS1 to 4b'1101 335 * CS2 to 4b'1011 336 * CS3 to 4b'0111 337 */ 338 chip_select = 0xF & ~(1 << chip_select); 339 } 340 341 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK 342 << CQSPI_REG_CONFIG_CHIPSELECT_LSB); 343 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK) 344 << CQSPI_REG_CONFIG_CHIPSELECT_LSB; 345 writel(reg, reg_base + CQSPI_REG_CONFIG); 346 347 cadence_qspi_apb_controller_enable(reg_base); 348 return; 349 } 350 351 void cadence_qspi_apb_delay(void *reg_base, 352 unsigned int ref_clk, unsigned int sclk_hz, 353 unsigned int tshsl_ns, unsigned int tsd2d_ns, 354 unsigned int tchsh_ns, unsigned int tslch_ns) 355 { 356 unsigned int ref_clk_ns; 357 unsigned int sclk_ns; 358 unsigned int tshsl, tchsh, tslch, tsd2d; 359 unsigned int reg; 360 361 cadence_qspi_apb_controller_disable(reg_base); 362 363 /* Convert to ns. */ 364 ref_clk_ns = (1000000000) / ref_clk; 365 366 /* Convert to ns. */ 367 sclk_ns = (1000000000) / sclk_hz; 368 369 /* Plus 1 to round up 1 clock cycle. */ 370 tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1; 371 tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1; 372 tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1; 373 tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1; 374 375 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK) 376 << CQSPI_REG_DELAY_TSHSL_LSB); 377 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK) 378 << CQSPI_REG_DELAY_TCHSH_LSB); 379 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK) 380 << CQSPI_REG_DELAY_TSLCH_LSB); 381 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK) 382 << CQSPI_REG_DELAY_TSD2D_LSB); 383 writel(reg, reg_base + CQSPI_REG_DELAY); 384 385 cadence_qspi_apb_controller_enable(reg_base); 386 return; 387 } 388 389 void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat) 390 { 391 unsigned reg; 392 393 cadence_qspi_apb_controller_disable(plat->regbase); 394 395 /* Configure the device size and address bytes */ 396 reg = readl(plat->regbase + CQSPI_REG_SIZE); 397 /* Clear the previous value */ 398 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); 399 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); 400 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB); 401 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB); 402 writel(reg, plat->regbase + CQSPI_REG_SIZE); 403 404 /* Configure the remap address register, no remap */ 405 writel(0, plat->regbase + CQSPI_REG_REMAP); 406 407 /* Indirect mode configurations */ 408 writel((plat->sram_size/2), plat->regbase + CQSPI_REG_SRAMPARTITION); 409 410 /* Disable all interrupts */ 411 writel(0, plat->regbase + CQSPI_REG_IRQMASK); 412 413 cadence_qspi_apb_controller_enable(plat->regbase); 414 return; 415 } 416 417 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base, 418 unsigned int reg) 419 { 420 unsigned int retry = CQSPI_REG_RETRY; 421 422 /* Write the CMDCTRL without start execution. */ 423 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 424 /* Start execute */ 425 reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK; 426 writel(reg, reg_base + CQSPI_REG_CMDCTRL); 427 428 while (retry--) { 429 reg = readl(reg_base + CQSPI_REG_CMDCTRL); 430 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0) 431 break; 432 udelay(1); 433 } 434 435 if (!retry) { 436 printf("QSPI: flash command execution timeout\n"); 437 return -EIO; 438 } 439 440 /* Polling QSPI idle status. */ 441 if (!cadence_qspi_wait_idle(reg_base)) 442 return -EIO; 443 444 return 0; 445 } 446 447 /* For command RDID, RDSR. */ 448 int cadence_qspi_apb_command_read(void *reg_base, 449 unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, 450 u8 *rxbuf) 451 { 452 unsigned int reg; 453 unsigned int read_len; 454 int status; 455 456 if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) { 457 printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n", 458 cmdlen, rxlen); 459 return -EINVAL; 460 } 461 462 reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; 463 464 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB); 465 466 /* 0 means 1 byte. */ 467 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) 468 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); 469 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg); 470 if (status != 0) 471 return status; 472 473 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER); 474 475 /* Put the read value into rx_buf */ 476 read_len = (rxlen > 4) ? 4 : rxlen; 477 memcpy(rxbuf, ®, read_len); 478 rxbuf += read_len; 479 480 if (rxlen > 4) { 481 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER); 482 483 read_len = rxlen - read_len; 484 memcpy(rxbuf, ®, read_len); 485 } 486 return 0; 487 } 488 489 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */ 490 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, 491 const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf) 492 { 493 unsigned int reg = 0; 494 unsigned int addr_value; 495 unsigned int wr_data; 496 unsigned int wr_len; 497 498 if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) { 499 printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n", 500 cmdlen, txlen); 501 return -EINVAL; 502 } 503 504 reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB; 505 506 if (cmdlen == 4 || cmdlen == 5) { 507 /* Command with address */ 508 reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); 509 /* Number of bytes to write. */ 510 reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) 511 << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; 512 /* Get address */ 513 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], 514 cmdlen >= 5 ? 4 : 3); 515 516 writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS); 517 } 518 519 if (txlen) { 520 /* writing data = yes */ 521 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB); 522 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) 523 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB; 524 525 wr_len = txlen > 4 ? 4 : txlen; 526 memcpy(&wr_data, txbuf, wr_len); 527 writel(wr_data, reg_base + 528 CQSPI_REG_CMDWRITEDATALOWER); 529 530 if (txlen > 4) { 531 txbuf += wr_len; 532 wr_len = txlen - wr_len; 533 memcpy(&wr_data, txbuf, wr_len); 534 writel(wr_data, reg_base + 535 CQSPI_REG_CMDWRITEDATAUPPER); 536 } 537 } 538 539 /* Execute the command */ 540 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg); 541 } 542 543 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ 544 int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, 545 unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf) 546 { 547 unsigned int reg; 548 unsigned int rd_reg; 549 unsigned int addr_value; 550 unsigned int dummy_clk; 551 unsigned int dummy_bytes; 552 unsigned int addr_bytes; 553 554 /* 555 * Identify addr_byte. All NOR flash device drivers are using fast read 556 * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte. 557 * With that, the length is in value of 5 or 6. Only FRAM chip from 558 * ramtron using normal read (which won't need dummy byte). 559 * Unlikely NOR flash using normal read due to performance issue. 560 */ 561 if (cmdlen >= 5) 562 /* to cater fast read where cmd + addr + dummy */ 563 addr_bytes = cmdlen - 2; 564 else 565 /* for normal read (only ramtron as of now) */ 566 addr_bytes = cmdlen - 1; 567 568 /* Setup the indirect trigger address */ 569 writel((u32)plat->ahbbase, 570 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); 571 572 /* Configure the opcode */ 573 rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; 574 575 if (rx_width & SPI_RX_QUAD) 576 /* Instruction and address at DQ0, data at DQ0-3. */ 577 rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; 578 579 /* Get address */ 580 addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); 581 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); 582 583 /* The remaining lenght is dummy bytes. */ 584 dummy_bytes = cmdlen - addr_bytes - 1; 585 if (dummy_bytes) { 586 if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX) 587 dummy_bytes = CQSPI_DUMMY_BYTES_MAX; 588 589 rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); 590 #if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD) 591 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); 592 #else 593 writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT); 594 #endif 595 596 /* Convert to clock cycles. */ 597 dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE; 598 /* Need to minus the mode byte (8 clocks). */ 599 dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE; 600 601 if (dummy_clk) 602 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK) 603 << CQSPI_REG_RD_INSTR_DUMMY_LSB; 604 } 605 606 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR); 607 608 /* set device size */ 609 reg = readl(plat->regbase + CQSPI_REG_SIZE); 610 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 611 reg |= (addr_bytes - 1); 612 writel(reg, plat->regbase + CQSPI_REG_SIZE); 613 return 0; 614 } 615 616 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat) 617 { 618 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL); 619 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB; 620 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK; 621 } 622 623 static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat) 624 { 625 unsigned int timeout = 10000; 626 u32 reg; 627 628 while (timeout--) { 629 reg = cadence_qspi_get_rd_sram_level(plat); 630 if (reg) 631 return reg; 632 udelay(1); 633 } 634 635 return -ETIMEDOUT; 636 } 637 638 int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, 639 unsigned int n_rx, u8 *rxbuf) 640 { 641 unsigned int remaining = n_rx; 642 unsigned int bytes_to_read = 0; 643 int ret; 644 645 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES); 646 647 /* Start the indirect read transfer */ 648 writel(CQSPI_REG_INDIRECTRD_START_MASK, 649 plat->regbase + CQSPI_REG_INDIRECTRD); 650 651 while (remaining > 0) { 652 ret = cadence_qspi_wait_for_data(plat); 653 if (ret < 0) { 654 printf("Indirect write timed out (%i)\n", ret); 655 goto failrd; 656 } 657 658 bytes_to_read = ret; 659 660 while (bytes_to_read != 0) { 661 bytes_to_read *= CQSPI_FIFO_WIDTH; 662 bytes_to_read = bytes_to_read > remaining ? 663 remaining : bytes_to_read; 664 /* Handle non-4-byte aligned access to avoid data abort. */ 665 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4)) 666 readsb(plat->ahbbase, rxbuf, bytes_to_read); 667 else 668 readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2); 669 rxbuf += bytes_to_read; 670 remaining -= bytes_to_read; 671 bytes_to_read = cadence_qspi_get_rd_sram_level(plat); 672 } 673 } 674 675 /* Check indirect done status */ 676 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD, 677 CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0); 678 if (ret) { 679 printf("Indirect read completion error (%i)\n", ret); 680 goto failrd; 681 } 682 683 /* Clear indirect completion status */ 684 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, 685 plat->regbase + CQSPI_REG_INDIRECTRD); 686 687 return 0; 688 689 failrd: 690 /* Cancel the indirect read */ 691 writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK, 692 plat->regbase + CQSPI_REG_INDIRECTRD); 693 return ret; 694 } 695 696 /* Opcode + Address (3/4 bytes) */ 697 int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, 698 unsigned int cmdlen, const u8 *cmdbuf) 699 { 700 unsigned int reg; 701 unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; 702 703 if (cmdlen < 4 || cmdbuf == NULL) { 704 printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n", 705 cmdlen, (unsigned int)cmdbuf); 706 return -EINVAL; 707 } 708 /* Setup the indirect trigger address */ 709 writel((u32)plat->ahbbase, 710 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); 711 712 /* Configure the opcode */ 713 reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; 714 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); 715 716 /* Setup write address. */ 717 reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); 718 writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR); 719 720 reg = readl(plat->regbase + CQSPI_REG_SIZE); 721 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; 722 reg |= (addr_bytes - 1); 723 writel(reg, plat->regbase + CQSPI_REG_SIZE); 724 return 0; 725 } 726 727 int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, 728 unsigned int n_tx, const u8 *txbuf) 729 { 730 unsigned int page_size = plat->page_size; 731 unsigned int remaining = n_tx; 732 unsigned int write_bytes; 733 int ret; 734 735 /* Configure the indirect read transfer bytes */ 736 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES); 737 738 /* Start the indirect write transfer */ 739 writel(CQSPI_REG_INDIRECTWR_START_MASK, 740 plat->regbase + CQSPI_REG_INDIRECTWR); 741 742 while (remaining > 0) { 743 write_bytes = remaining > page_size ? page_size : remaining; 744 /* Handle non-4-byte aligned access to avoid data abort. */ 745 if (((uintptr_t)txbuf % 4) || (write_bytes % 4)) 746 writesb(plat->ahbbase, txbuf, write_bytes); 747 else 748 writesl(plat->ahbbase, txbuf, write_bytes >> 2); 749 750 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL, 751 CQSPI_REG_SDRAMLEVEL_WR_MASK << 752 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0); 753 if (ret) { 754 printf("Indirect write timed out (%i)\n", ret); 755 goto failwr; 756 } 757 758 txbuf += write_bytes; 759 remaining -= write_bytes; 760 } 761 762 /* Check indirect done status */ 763 ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR, 764 CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0); 765 if (ret) { 766 printf("Indirect write completion error (%i)\n", ret); 767 goto failwr; 768 } 769 770 /* Clear indirect completion status */ 771 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, 772 plat->regbase + CQSPI_REG_INDIRECTWR); 773 return 0; 774 775 failwr: 776 /* Cancel the indirect write */ 777 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 778 plat->regbase + CQSPI_REG_INDIRECTWR); 779 return ret; 780 } 781 782 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) 783 { 784 unsigned int reg; 785 786 /* enter XiP mode immediately and enable direct mode */ 787 reg = readl(reg_base + CQSPI_REG_CONFIG); 788 reg |= CQSPI_REG_CONFIG_ENABLE_MASK; 789 reg |= CQSPI_REG_CONFIG_DIRECT_MASK; 790 reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK; 791 writel(reg, reg_base + CQSPI_REG_CONFIG); 792 793 /* keep the XiP mode */ 794 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT); 795 796 /* Enable mode bit at devrd */ 797 reg = readl(reg_base + CQSPI_REG_RD_INSTR); 798 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB); 799 writel(reg, reg_base + CQSPI_REG_RD_INSTR); 800 } 801