net: gmac_rockchip: Add rv1103b supprot

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ice7e67458657931dc8a426f83a68e18c03ab788e

net: dwc_eth_qos: Return error if start failed

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I0814cb2649b898bc029533c276549367e3985498

drivers: net: Add net qso full config option

Add this config option to reduce memory usage, if it was not necessary.

Change-Id: I11b20318f48427ccba248c1e4c4cb66b85a9529a
Signed-off-by: David Wu <da

drivers: net: Add net qso full config option

Add this config option to reduce memory usage, if it was not necessary.

Change-Id: I11b20318f48427ccba248c1e4c4cb66b85a9529a
Signed-off-by: David Wu <david.wu@rock-chips.com>

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net: dwc_eth_qos: Don't reset phy every time

Change-Id: Id2e3322f6171dfb89452757a458b5a0821136da3
Signed-off-by: David Wu <david.wu@rock-chips.com>

net: dwc_eth_qos: Fix compile error for gpio

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ife092cc2aca2c359fc465058e44ca645afbc8114

net: dwc_eth_qos: Add eqos_rockchip_ops

The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I2

net: dwc_eth_qos: Add eqos_rockchip_ops

The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I214b0b2fbe04a139de911435c4abf224264f5495

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net: dwc_eth_qos: Fix the reset for RGMII

When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.

Signed-off-by: Davi

net: dwc_eth_qos: Fix the reset for RGMII

When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Id1d2405397d0c2f59b7bf1e341cdf66b023e4226

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net: dwc_eth_qos: Export common struct and interface at head file

Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.

Signed-off-by: David Wu <david.wu@rock-ch

net: dwc_eth_qos: Export common struct and interface at head file

Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ic845d330465c1bb8f7868fb188e5bf30c865b9b5

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net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional

If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.

Signed-off-by: David Wu <david

net: dwc_eth_qos: make eqos_start_clks and eqos_stop_clks optional

If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Id5ffc944a2c066d78a784aeb28ecb846b53e52fd

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net: dwc_eth_qos: Split eqos_start() to get link speed

For Rockchip, need to obtain the current link speed to
configure the tx clocks, (for example, in rgmii mode,
1000M link: 125M, 100M link: 25M,

net: dwc_eth_qos: Split eqos_start() to get link speed

For Rockchip, need to obtain the current link speed to
configure the tx clocks, (for example, in rgmii mode,
1000M link: 125M, 100M link: 25M, 10M link is 2.5M rate)
and then enable gmac. So after the adjust_link(), before
the start gamc, this intermediate stage needs to configure
the clock according to the current link speed.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I9a46da28abca0544cb0a56b0a0574e2fd1de0c52

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net: dwc_eth_qos: Make clk_rx and clk_tx optional

For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Ch

net: dwc_eth_qos: Make clk_rx and clk_tx optional

For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I952ac6cc6a4278c887b530bd6d387752358c89a8

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net: dwc_eth_qos: Move interface() to eqos_ops structure

After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined

net: dwc_eth_qos: Move interface() to eqos_ops structure

After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ibc60f49f36bb2011454370ed7fcc6d9db3b34d9f

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net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32

It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more

net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rst gpio for stm32

It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I428c7158c113143a7e51296705fabde6f05eb0f6

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net: dwc_eth_qos: Use dev_ functions calls to get FDT data

It seems dev_ functions are more general than fdt_ functions.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia1d19c61fb8a2c

net: dwc_eth_qos: Use dev_ functions calls to get FDT data

It seems dev_ functions are more general than fdt_ functions.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia1d19c61fb8a2c8540b3dfda53b6aeb3b72acb7f

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UPSTREAM: eQos: Implement the read_rom_hwaddr callback

Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signe

UPSTREAM: eQos: Implement the read_rom_hwaddr callback

Implement the read_rom_hwaddr callback to load MAC address from fuse
for imx8m platforms.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4204948ae6a0408f7d642007d27923a3c6941562

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UPSTREAM: net: eqos: implement callbaks to get interface and set txclk rate

Implement the callbacks to get phy mode interface and txclk
rate configuration.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed

UPSTREAM: net: eqos: implement callbaks to get interface and set txclk rate

Implement the callbacks to get phy mode interface and txclk
rate configuration.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I0a5265347936c1bc821c175eea1698d2624d4873

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UPSTREAM: net: dwc_eth_qos: add dwc eqos for imx support

Add dwc eqos for imx support.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <p

UPSTREAM: net: dwc_eth_qos: add dwc eqos for imx support

Add dwc eqos for imx support.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I49127be057a49e6b45e37f940d523d808c20343b

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UPSTREAM: net: Update eQos driver and FEC driver to use eth phy interfaces

Update eQoS and fec ethernet drivers to support shared MDIO framework

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by:

UPSTREAM: net: Update eQos driver and FEC driver to use eth phy interfaces

Update eQoS and fec ethernet drivers to support shared MDIO framework

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf5f3ca585190c6469b68195aaea2499242a0096

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UPSTREAM: net: dwc_eth_qos: Prevent DMA from writing updated RX DMA descriptor

The DMA may attempt to write a DMA descriptor in the ring while it is
being updated. By writing the DMA descriptor buff

UPSTREAM: net: dwc_eth_qos: Prevent DMA from writing updated RX DMA descriptor

The DMA may attempt to write a DMA descriptor in the ring while it is
being updated. By writing the DMA descriptor buffer address to 0, it
is assured the DMA will not use such a buffer and the buffer can be
updated without any interference.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If70a57f195c146d571de20385b55ff75f7dea7db

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UPSTREAM: net: dwc_eth_qos: Invalidate RX packet DMA buffer

This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the cac

UPSTREAM: net: dwc_eth_qos: Invalidate RX packet DMA buffer

This patch prevents an issue where the RX packet might have been
accessed by the CPU, which now has cached data from the packet in
the caches and possibly various write buffers, and these data may
be evicted from the caches into the DRAM while the buffer is also
written by the DMA.

By invalidating the buffer after the CPU accessed it and before the
DMA populates the buffer, it is assured that the buffer will not be
corrupted.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6271396aad6abac3fb11e5e742a3b2c9e7cc355b

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UPSTREAM: net: dwc_eth_qos: Invalidate RX descriptor before reading

The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the R

UPSTREAM: net: dwc_eth_qos: Invalidate RX descriptor before reading

The current code polls the RX desciptor ring for new packets by reading
the RX descriptor status. This works by accident, as the RX descriptors
are often in non-cacheable memory. However, the driver does support use
of RX descriptors in cacheable memory.

This patch adds a missing RX descriptor invalidation, which assures the
CPU will read a fresh copy of the RX descriptor instead of a cached one.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Ia05e8a43d707088bc3699b7d00434c8d12d2692f

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UPSTREAM: net: dwc_eth_qos: Flush the RX descriptors on init

Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine

UPSTREAM: net: dwc_eth_qos: Flush the RX descriptors on init

Currently the code only flushes the first RX descriptor, not every entry
in the RX descriptor ring. Fix this, to make sure the DMA engine can pick
the RX descriptors correctly.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I7a37f8a1fd51b2b7ca4fb557885d711ebd72c49c

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UPSTREAM: net: dwc_eth_qos: Correctly wrap around TX descriptor tail pointer

This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The p

UPSTREAM: net: dwc_eth_qos: Correctly wrap around TX descriptor tail pointer

This code programs the next descriptor in the TX descriptor ring into
the hardware as the last valid TX descriptor. The problem is that if
the currenty descriptor is the last one in the array, the code will
not wrap around correctly and use TX descriptor 0 again, but instead
will use TX descriptor at address right past the TX descriptor ring,
which is the first descriptor in the RX ring.

Fix this by adding the necessary wrap-around.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: Iaf0f5dba76c232af1cbef628c099aaf43542757d

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UPSTREAM: net: dwc_eth_qos: Fully rewrite RX descriptor field 3

The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, righ

UPSTREAM: net: dwc_eth_qos: Fully rewrite RX descriptor field 3

The RX descriptor field 3 should contain only OWN and BUF1V bits before
being used for receiving data by the DMA engine. However, right now, if
the descriptor was already used for receiving data and is being cleared,
the field 3 is only modified and the aforementioned two bits are ORRed
into the field. This could lead to a residual dirty bits being left in
the field 3 from previous transfer, and it generally does. Fully set the
field 3 instead to clear those residual dirty bits.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I5b116fa58de65b3958c3ddd87f6c182c532b9542

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UPSTREAM: net: dwc_eth_qos: implement phy reg and max-speed for stm32

Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supporte

UPSTREAM: net: dwc_eth_qos: implement phy reg and max-speed for stm32

Add management of property "reg" to configure @ of phy and
also "max-speed" property to specify maximum speed in Mbit/s
supported by the device

Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I6ecabcffc4782f1e641d8ee1021f6c3caf360707

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