1 /* 2 * Copyright (c) 2016, NVIDIA CORPORATION. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Portions based on U-Boot's rtl8169.c. 7 */ 8 9 /* 10 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of 11 * Service) IP block. The IP supports multiple options for bus type, clocking/ 12 * reset structure, and feature list. 13 * 14 * The driver is written such that generic core logic is kept separate from 15 * configuration-specific logic. Code that interacts with configuration- 16 * specific resources is split out into separate functions to avoid polluting 17 * common code. If/when this driver is enhanced to support multiple 18 * configurations, the core code should be adapted to call all configuration- 19 * specific functions through function pointers, with the definition of those 20 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data 21 * field. 22 * 23 * The following configurations are currently supported: 24 * tegra186: 25 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an 26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and 27 * supports a single RGMII PHY. This configuration also has SW control over 28 * all clock and reset signals to the HW block. 29 */ 30 #include <common.h> 31 #include <clk.h> 32 #include <dm.h> 33 #include <errno.h> 34 #include <memalign.h> 35 #include <miiphy.h> 36 #include <net.h> 37 #include <netdev.h> 38 #include <phy.h> 39 #include <reset.h> 40 #include <wait_bit.h> 41 #include <asm/gpio.h> 42 #include <asm/io.h> 43 #include <eth_phy.h> 44 #ifdef CONFIG_ARCH_IMX8M 45 #include <asm/arch/clock.h> 46 #include <asm/mach-imx/sys_proto.h> 47 #endif 48 49 /* Core registers */ 50 51 #define EQOS_MAC_REGS_BASE 0x000 52 struct eqos_mac_regs { 53 uint32_t configuration; /* 0x000 */ 54 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ 55 uint32_t q0_tx_flow_ctrl; /* 0x070 */ 56 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ 57 uint32_t rx_flow_ctrl; /* 0x090 */ 58 uint32_t unused_094; /* 0x094 */ 59 uint32_t txq_prty_map0; /* 0x098 */ 60 uint32_t unused_09c; /* 0x09c */ 61 uint32_t rxq_ctrl0; /* 0x0a0 */ 62 uint32_t unused_0a4; /* 0x0a4 */ 63 uint32_t rxq_ctrl2; /* 0x0a8 */ 64 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ 65 uint32_t us_tic_counter; /* 0x0dc */ 66 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ 67 uint32_t hw_feature0; /* 0x11c */ 68 uint32_t hw_feature1; /* 0x120 */ 69 uint32_t hw_feature2; /* 0x124 */ 70 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ 71 uint32_t mdio_address; /* 0x200 */ 72 uint32_t mdio_data; /* 0x204 */ 73 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ 74 uint32_t address0_high; /* 0x300 */ 75 uint32_t address0_low; /* 0x304 */ 76 }; 77 78 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) 79 #define EQOS_MAC_CONFIGURATION_CST BIT(21) 80 #define EQOS_MAC_CONFIGURATION_ACS BIT(20) 81 #define EQOS_MAC_CONFIGURATION_WD BIT(19) 82 #define EQOS_MAC_CONFIGURATION_JD BIT(17) 83 #define EQOS_MAC_CONFIGURATION_JE BIT(16) 84 #define EQOS_MAC_CONFIGURATION_PS BIT(15) 85 #define EQOS_MAC_CONFIGURATION_FES BIT(14) 86 #define EQOS_MAC_CONFIGURATION_DM BIT(13) 87 #define EQOS_MAC_CONFIGURATION_LM BIT(12) 88 #define EQOS_MAC_CONFIGURATION_TE BIT(1) 89 #define EQOS_MAC_CONFIGURATION_RE BIT(0) 90 91 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 92 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff 93 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) 94 95 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) 96 97 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 98 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff 99 100 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 101 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 102 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 103 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 104 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 105 106 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 107 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff 108 109 #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8 110 #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2 111 #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1 112 #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0 113 114 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 115 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f 116 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 117 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f 118 119 #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28 120 #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3 121 122 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 123 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 124 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 125 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 126 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 127 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) 128 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 129 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 130 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 131 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) 132 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) 133 134 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff 135 136 #define EQOS_MTL_REGS_BASE 0xd00 137 struct eqos_mtl_regs { 138 uint32_t txq0_operation_mode; /* 0xd00 */ 139 uint32_t unused_d04; /* 0xd04 */ 140 uint32_t txq0_debug; /* 0xd08 */ 141 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ 142 uint32_t txq0_quantum_weight; /* 0xd18 */ 143 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ 144 uint32_t rxq0_operation_mode; /* 0xd30 */ 145 uint32_t unused_d34; /* 0xd34 */ 146 uint32_t rxq0_debug; /* 0xd38 */ 147 }; 148 149 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 150 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff 151 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 152 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 153 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 154 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) 155 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) 156 157 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4) 158 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 159 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3 160 161 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 162 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff 163 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 164 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f 165 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 166 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f 167 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) 168 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) 169 #define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4) 170 #define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3) 171 172 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 173 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff 174 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 175 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3 176 177 #define EQOS_DMA_REGS_BASE 0x1000 178 struct eqos_dma_regs { 179 uint32_t mode; /* 0x1000 */ 180 uint32_t sysbus_mode; /* 0x1004 */ 181 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */ 182 uint32_t ch0_control; /* 0x1100 */ 183 uint32_t ch0_tx_control; /* 0x1104 */ 184 uint32_t ch0_rx_control; /* 0x1108 */ 185 uint32_t unused_110c; /* 0x110c */ 186 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */ 187 uint32_t ch0_txdesc_list_address; /* 0x1114 */ 188 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */ 189 uint32_t ch0_rxdesc_list_address; /* 0x111c */ 190 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */ 191 uint32_t unused_1124; /* 0x1124 */ 192 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */ 193 uint32_t ch0_txdesc_ring_length; /* 0x112c */ 194 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */ 195 }; 196 197 #define EQOS_DMA_MODE_SWR BIT(0) 198 199 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 200 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf 201 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) 202 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) 203 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) 204 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) 205 206 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) 207 208 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 209 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f 210 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) 211 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) 212 213 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 214 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f 215 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 216 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff 217 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) 218 219 /* These registers are Tegra186-specific */ 220 #define EQOS_TEGRA186_REGS_BASE 0x8800 221 struct eqos_tegra186_regs { 222 uint32_t sdmemcomppadctrl; /* 0x8800 */ 223 uint32_t auto_cal_config; /* 0x8804 */ 224 uint32_t unused_8808; /* 0x8808 */ 225 uint32_t auto_cal_status; /* 0x880c */ 226 }; 227 228 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) 229 230 #define EQOS_AUTO_CAL_CONFIG_START BIT(31) 231 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29) 232 233 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) 234 235 /* Descriptors */ 236 237 #define EQOS_DESCRIPTOR_WORDS 4 238 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) 239 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ 240 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN 241 #define EQOS_DESCRIPTORS_TX 4 242 #define EQOS_DESCRIPTORS_RX 4 243 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) 244 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \ 245 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) 246 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN 247 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) 248 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) 249 250 /* 251 * Warn if the cache-line size is larger than the descriptor size. In such 252 * cases the driver will likely fail because the CPU needs to flush the cache 253 * when requeuing RX buffers, therefore descriptors written by the hardware 254 * may be discarded. Architectures with full IO coherence, such as x86, do not 255 * experience this issue, and hence are excluded from this condition. 256 * 257 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 258 * the driver to allocate descriptors from a pool of non-cached memory. 259 */ 260 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN 261 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 262 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 263 #warning Cache line size is larger than descriptor size 264 #endif 265 #endif 266 267 struct eqos_desc { 268 u32 des0; 269 u32 des1; 270 u32 des2; 271 u32 des3; 272 }; 273 274 #define EQOS_DESC3_OWN BIT(31) 275 #define EQOS_DESC3_FD BIT(29) 276 #define EQOS_DESC3_LD BIT(28) 277 #define EQOS_DESC3_BUF1V BIT(24) 278 279 struct eqos_config { 280 bool reg_access_always_ok; 281 int mdio_wait; 282 int swr_wait; 283 int config_mac; 284 int config_mac_mdio; 285 phy_interface_t (*interface)(struct udevice *dev); 286 struct eqos_ops *ops; 287 }; 288 289 struct eqos_ops { 290 void (*eqos_inval_desc)(void *desc); 291 void (*eqos_flush_desc)(void *desc); 292 void (*eqos_inval_buffer)(void *buf, size_t size); 293 void (*eqos_flush_buffer)(void *buf, size_t size); 294 int (*eqos_probe_resources)(struct udevice *dev); 295 int (*eqos_remove_resources)(struct udevice *dev); 296 int (*eqos_stop_resets)(struct udevice *dev); 297 int (*eqos_start_resets)(struct udevice *dev); 298 void (*eqos_stop_clks)(struct udevice *dev); 299 int (*eqos_start_clks)(struct udevice *dev); 300 int (*eqos_calibrate_pads)(struct udevice *dev); 301 int (*eqos_disable_calibration)(struct udevice *dev); 302 int (*eqos_set_tx_clk_speed)(struct udevice *dev); 303 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev); 304 }; 305 306 struct eqos_priv { 307 struct udevice *dev; 308 const struct eqos_config *config; 309 fdt_addr_t regs; 310 struct eqos_mac_regs *mac_regs; 311 struct eqos_mtl_regs *mtl_regs; 312 struct eqos_dma_regs *dma_regs; 313 struct eqos_tegra186_regs *tegra186_regs; 314 struct reset_ctl reset_ctl; 315 struct gpio_desc phy_reset_gpio; 316 struct clk clk_master_bus; 317 struct clk clk_rx; 318 struct clk clk_ptp_ref; 319 struct clk clk_tx; 320 struct clk clk_ck; 321 struct clk clk_slave_bus; 322 struct mii_dev *mii; 323 struct phy_device *phy; 324 int phyaddr; 325 u32 max_speed; 326 void *descs; 327 struct eqos_desc *tx_descs; 328 struct eqos_desc *rx_descs; 329 int tx_desc_idx, rx_desc_idx; 330 void *tx_dma_buf; 331 void *rx_dma_buf; 332 void *rx_pkt; 333 bool started; 334 bool reg_access_ok; 335 }; 336 337 /* 338 * TX and RX descriptors are 16 bytes. This causes problems with the cache 339 * maintenance on CPUs where the cache-line size exceeds the size of these 340 * descriptors. What will happen is that when the driver receives a packet 341 * it will be immediately requeued for the hardware to reuse. The CPU will 342 * therefore need to flush the cache-line containing the descriptor, which 343 * will cause all other descriptors in the same cache-line to be flushed 344 * along with it. If one of those descriptors had been written to by the 345 * device those changes (and the associated packet) will be lost. 346 * 347 * To work around this, we make use of non-cached memory if available. If 348 * descriptors are mapped uncached there's no need to manually flush them 349 * or invalidate them. 350 * 351 * Note that this only applies to descriptors. The packet data buffers do 352 * not have the same constraints since they are 1536 bytes large, so they 353 * are unlikely to share cache-lines. 354 */ 355 static void *eqos_alloc_descs(unsigned int num) 356 { 357 #ifdef CONFIG_SYS_NONCACHED_MEMORY 358 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE, 359 EQOS_DESCRIPTOR_ALIGN); 360 #else 361 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE); 362 #endif 363 } 364 365 static void eqos_free_descs(void *descs) 366 { 367 #ifdef CONFIG_SYS_NONCACHED_MEMORY 368 /* FIXME: noncached_alloc() has no opposite */ 369 #else 370 free(descs); 371 #endif 372 } 373 374 static void eqos_inval_desc_tegra186(void *desc) 375 { 376 #ifndef CONFIG_SYS_NONCACHED_MEMORY 377 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 378 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE, 379 ARCH_DMA_MINALIGN); 380 381 invalidate_dcache_range(start, end); 382 #endif 383 } 384 385 static void eqos_inval_desc_generic(void *desc) 386 { 387 #ifndef CONFIG_SYS_NONCACHED_MEMORY 388 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); 389 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, 390 ARCH_DMA_MINALIGN); 391 392 invalidate_dcache_range(start, end); 393 #endif 394 } 395 396 static void eqos_flush_desc_tegra186(void *desc) 397 { 398 #ifndef CONFIG_SYS_NONCACHED_MEMORY 399 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE); 400 #endif 401 } 402 403 static void eqos_flush_desc_generic(void *desc) 404 { 405 #ifndef CONFIG_SYS_NONCACHED_MEMORY 406 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); 407 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, 408 ARCH_DMA_MINALIGN); 409 410 flush_dcache_range(start, end); 411 #endif 412 } 413 414 static void eqos_inval_buffer_tegra186(void *buf, size_t size) 415 { 416 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 417 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 418 419 invalidate_dcache_range(start, end); 420 } 421 422 static void eqos_inval_buffer_generic(void *buf, size_t size) 423 { 424 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); 425 unsigned long end = roundup((unsigned long)buf + size, 426 ARCH_DMA_MINALIGN); 427 428 invalidate_dcache_range(start, end); 429 } 430 431 static void eqos_flush_buffer_tegra186(void *buf, size_t size) 432 { 433 flush_cache((unsigned long)buf, size); 434 } 435 436 static void eqos_flush_buffer_generic(void *buf, size_t size) 437 { 438 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); 439 unsigned long end = roundup((unsigned long)buf + size, 440 ARCH_DMA_MINALIGN); 441 442 flush_dcache_range(start, end); 443 } 444 445 static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 446 { 447 return wait_for_bit_le32(&eqos->mac_regs->mdio_address, 448 EQOS_MAC_MDIO_ADDRESS_GB, false, 449 1000000, true); 450 } 451 452 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, 453 int mdio_reg) 454 { 455 struct eqos_priv *eqos = bus->priv; 456 u32 val; 457 int ret; 458 459 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr, 460 mdio_reg); 461 462 ret = eqos_mdio_wait_idle(eqos); 463 if (ret) { 464 pr_err("MDIO not idle at entry"); 465 return ret; 466 } 467 468 val = readl(&eqos->mac_regs->mdio_address); 469 val &= EQOS_MAC_MDIO_ADDRESS_SKAP | 470 EQOS_MAC_MDIO_ADDRESS_C45E; 471 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | 472 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | 473 (eqos->config->config_mac_mdio << 474 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | 475 (EQOS_MAC_MDIO_ADDRESS_GOC_READ << 476 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | 477 EQOS_MAC_MDIO_ADDRESS_GB; 478 writel(val, &eqos->mac_regs->mdio_address); 479 480 udelay(eqos->config->mdio_wait); 481 482 ret = eqos_mdio_wait_idle(eqos); 483 if (ret) { 484 pr_err("MDIO read didn't complete"); 485 return ret; 486 } 487 488 val = readl(&eqos->mac_regs->mdio_data); 489 val &= EQOS_MAC_MDIO_DATA_GD_MASK; 490 491 debug("%s: val=%x\n", __func__, val); 492 493 return val; 494 } 495 496 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, 497 int mdio_reg, u16 mdio_val) 498 { 499 struct eqos_priv *eqos = bus->priv; 500 u32 val; 501 int ret; 502 503 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, 504 mdio_addr, mdio_reg, mdio_val); 505 506 ret = eqos_mdio_wait_idle(eqos); 507 if (ret) { 508 pr_err("MDIO not idle at entry"); 509 return ret; 510 } 511 512 writel(mdio_val, &eqos->mac_regs->mdio_data); 513 514 val = readl(&eqos->mac_regs->mdio_address); 515 val &= EQOS_MAC_MDIO_ADDRESS_SKAP | 516 EQOS_MAC_MDIO_ADDRESS_C45E; 517 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | 518 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | 519 (eqos->config->config_mac_mdio << 520 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | 521 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << 522 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | 523 EQOS_MAC_MDIO_ADDRESS_GB; 524 writel(val, &eqos->mac_regs->mdio_address); 525 526 udelay(eqos->config->mdio_wait); 527 528 ret = eqos_mdio_wait_idle(eqos); 529 if (ret) { 530 pr_err("MDIO read didn't complete"); 531 return ret; 532 } 533 534 return 0; 535 } 536 537 static int eqos_start_clks_tegra186(struct udevice *dev) 538 { 539 #ifdef CONFIG_CLK 540 struct eqos_priv *eqos = dev_get_priv(dev); 541 int ret; 542 543 debug("%s(dev=%p):\n", __func__, dev); 544 545 ret = clk_enable(&eqos->clk_slave_bus); 546 if (ret < 0) { 547 pr_err("clk_enable(clk_slave_bus) failed: %d", ret); 548 goto err; 549 } 550 551 ret = clk_enable(&eqos->clk_master_bus); 552 if (ret < 0) { 553 pr_err("clk_enable(clk_master_bus) failed: %d", ret); 554 goto err_disable_clk_slave_bus; 555 } 556 557 ret = clk_enable(&eqos->clk_rx); 558 if (ret < 0) { 559 pr_err("clk_enable(clk_rx) failed: %d", ret); 560 goto err_disable_clk_master_bus; 561 } 562 563 ret = clk_enable(&eqos->clk_ptp_ref); 564 if (ret < 0) { 565 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret); 566 goto err_disable_clk_rx; 567 } 568 569 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); 570 if (ret < 0) { 571 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret); 572 goto err_disable_clk_ptp_ref; 573 } 574 575 ret = clk_enable(&eqos->clk_tx); 576 if (ret < 0) { 577 pr_err("clk_enable(clk_tx) failed: %d", ret); 578 goto err_disable_clk_ptp_ref; 579 } 580 #endif 581 582 debug("%s: OK\n", __func__); 583 return 0; 584 585 #ifdef CONFIG_CLK 586 err_disable_clk_ptp_ref: 587 clk_disable(&eqos->clk_ptp_ref); 588 err_disable_clk_rx: 589 clk_disable(&eqos->clk_rx); 590 err_disable_clk_master_bus: 591 clk_disable(&eqos->clk_master_bus); 592 err_disable_clk_slave_bus: 593 clk_disable(&eqos->clk_slave_bus); 594 err: 595 debug("%s: FAILED: %d\n", __func__, ret); 596 return ret; 597 #endif 598 } 599 600 static int eqos_start_clks_stm32(struct udevice *dev) 601 { 602 #ifdef CONFIG_CLK 603 struct eqos_priv *eqos = dev_get_priv(dev); 604 int ret; 605 606 debug("%s(dev=%p):\n", __func__, dev); 607 608 ret = clk_enable(&eqos->clk_master_bus); 609 if (ret < 0) { 610 pr_err("clk_enable(clk_master_bus) failed: %d", ret); 611 goto err; 612 } 613 614 ret = clk_enable(&eqos->clk_rx); 615 if (ret < 0) { 616 pr_err("clk_enable(clk_rx) failed: %d", ret); 617 goto err_disable_clk_master_bus; 618 } 619 620 ret = clk_enable(&eqos->clk_tx); 621 if (ret < 0) { 622 pr_err("clk_enable(clk_tx) failed: %d", ret); 623 goto err_disable_clk_rx; 624 } 625 626 if (clk_valid(&eqos->clk_ck)) { 627 ret = clk_enable(&eqos->clk_ck); 628 if (ret < 0) { 629 pr_err("clk_enable(clk_ck) failed: %d", ret); 630 goto err_disable_clk_tx; 631 } 632 } 633 #endif 634 635 debug("%s: OK\n", __func__); 636 return 0; 637 638 #ifdef CONFIG_CLK 639 err_disable_clk_tx: 640 clk_disable(&eqos->clk_tx); 641 err_disable_clk_rx: 642 clk_disable(&eqos->clk_rx); 643 err_disable_clk_master_bus: 644 clk_disable(&eqos->clk_master_bus); 645 err: 646 debug("%s: FAILED: %d\n", __func__, ret); 647 return ret; 648 #endif 649 } 650 651 static int eqos_start_clks_imx(struct udevice *dev) 652 { 653 return 0; 654 } 655 656 static void eqos_stop_clks_tegra186(struct udevice *dev) 657 { 658 #ifdef CONFIG_CLK 659 struct eqos_priv *eqos = dev_get_priv(dev); 660 661 debug("%s(dev=%p):\n", __func__, dev); 662 663 clk_disable(&eqos->clk_tx); 664 clk_disable(&eqos->clk_ptp_ref); 665 clk_disable(&eqos->clk_rx); 666 clk_disable(&eqos->clk_master_bus); 667 clk_disable(&eqos->clk_slave_bus); 668 #endif 669 670 debug("%s: OK\n", __func__); 671 } 672 673 static void eqos_stop_clks_stm32(struct udevice *dev) 674 { 675 #ifdef CONFIG_CLK 676 struct eqos_priv *eqos = dev_get_priv(dev); 677 678 debug("%s(dev=%p):\n", __func__, dev); 679 680 clk_disable(&eqos->clk_tx); 681 clk_disable(&eqos->clk_rx); 682 clk_disable(&eqos->clk_master_bus); 683 if (clk_valid(&eqos->clk_ck)) 684 clk_disable(&eqos->clk_ck); 685 #endif 686 687 debug("%s: OK\n", __func__); 688 } 689 690 static void eqos_stop_clks_imx(struct udevice *dev) 691 { 692 /* empty */ 693 } 694 695 static int eqos_start_resets_tegra186(struct udevice *dev) 696 { 697 struct eqos_priv *eqos = dev_get_priv(dev); 698 int ret; 699 700 debug("%s(dev=%p):\n", __func__, dev); 701 702 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 703 if (ret < 0) { 704 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); 705 return ret; 706 } 707 708 udelay(2); 709 710 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 711 if (ret < 0) { 712 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); 713 return ret; 714 } 715 716 ret = reset_assert(&eqos->reset_ctl); 717 if (ret < 0) { 718 pr_err("reset_assert() failed: %d", ret); 719 return ret; 720 } 721 722 udelay(2); 723 724 ret = reset_deassert(&eqos->reset_ctl); 725 if (ret < 0) { 726 pr_err("reset_deassert() failed: %d", ret); 727 return ret; 728 } 729 730 debug("%s: OK\n", __func__); 731 return 0; 732 } 733 734 static int eqos_start_resets_stm32(struct udevice *dev) 735 { 736 struct eqos_priv *eqos = dev_get_priv(dev); 737 int ret; 738 739 debug("%s(dev=%p):\n", __func__, dev); 740 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 741 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 742 if (ret < 0) { 743 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", 744 ret); 745 return ret; 746 } 747 748 udelay(2); 749 750 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 751 if (ret < 0) { 752 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", 753 ret); 754 return ret; 755 } 756 } 757 debug("%s: OK\n", __func__); 758 759 return 0; 760 } 761 762 static int eqos_start_resets_imx(struct udevice *dev) 763 { 764 return 0; 765 } 766 767 static int eqos_stop_resets_tegra186(struct udevice *dev) 768 { 769 struct eqos_priv *eqos = dev_get_priv(dev); 770 771 reset_assert(&eqos->reset_ctl); 772 dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 773 774 return 0; 775 } 776 777 static int eqos_stop_resets_stm32(struct udevice *dev) 778 { 779 struct eqos_priv *eqos = dev_get_priv(dev); 780 int ret; 781 782 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 783 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 784 if (ret < 0) { 785 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", 786 ret); 787 return ret; 788 } 789 } 790 791 return 0; 792 } 793 794 static int eqos_stop_resets_imx(struct udevice *dev) 795 { 796 return 0; 797 } 798 799 static int eqos_calibrate_pads_tegra186(struct udevice *dev) 800 { 801 struct eqos_priv *eqos = dev_get_priv(dev); 802 int ret; 803 804 debug("%s(dev=%p):\n", __func__, dev); 805 806 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, 807 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); 808 809 udelay(1); 810 811 setbits_le32(&eqos->tegra186_regs->auto_cal_config, 812 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE); 813 814 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, 815 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false); 816 if (ret) { 817 pr_err("calibrate didn't start"); 818 goto failed; 819 } 820 821 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, 822 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false); 823 if (ret) { 824 pr_err("calibrate didn't finish"); 825 goto failed; 826 } 827 828 ret = 0; 829 830 failed: 831 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, 832 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); 833 834 debug("%s: returns %d\n", __func__, ret); 835 836 return ret; 837 } 838 839 static int eqos_disable_calibration_tegra186(struct udevice *dev) 840 { 841 struct eqos_priv *eqos = dev_get_priv(dev); 842 843 debug("%s(dev=%p):\n", __func__, dev); 844 845 clrbits_le32(&eqos->tegra186_regs->auto_cal_config, 846 EQOS_AUTO_CAL_CONFIG_ENABLE); 847 848 return 0; 849 } 850 851 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) 852 { 853 #ifdef CONFIG_CLK 854 struct eqos_priv *eqos = dev_get_priv(dev); 855 856 return clk_get_rate(&eqos->clk_slave_bus); 857 #else 858 return 0; 859 #endif 860 } 861 862 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) 863 { 864 #ifdef CONFIG_CLK 865 struct eqos_priv *eqos = dev_get_priv(dev); 866 867 return clk_get_rate(&eqos->clk_master_bus); 868 #else 869 return 0; 870 #endif 871 } 872 873 __weak u32 imx_get_eqos_csr_clk(void) 874 { 875 return 100 * 1000000; 876 } 877 __weak int imx_eqos_txclk_set_rate(unsigned long rate) 878 { 879 return 0; 880 } 881 882 static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev) 883 { 884 return imx_get_eqos_csr_clk(); 885 } 886 887 static int eqos_calibrate_pads_stm32(struct udevice *dev) 888 { 889 return 0; 890 } 891 892 static int eqos_calibrate_pads_imx(struct udevice *dev) 893 { 894 return 0; 895 } 896 897 static int eqos_disable_calibration_stm32(struct udevice *dev) 898 { 899 return 0; 900 } 901 902 static int eqos_disable_calibration_imx(struct udevice *dev) 903 { 904 return 0; 905 } 906 907 static int eqos_set_full_duplex(struct udevice *dev) 908 { 909 struct eqos_priv *eqos = dev_get_priv(dev); 910 911 debug("%s(dev=%p):\n", __func__, dev); 912 913 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); 914 915 return 0; 916 } 917 918 static int eqos_set_half_duplex(struct udevice *dev) 919 { 920 struct eqos_priv *eqos = dev_get_priv(dev); 921 922 debug("%s(dev=%p):\n", __func__, dev); 923 924 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); 925 926 /* WAR: Flush TX queue when switching to half-duplex */ 927 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, 928 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ); 929 930 return 0; 931 } 932 933 static int eqos_set_gmii_speed(struct udevice *dev) 934 { 935 struct eqos_priv *eqos = dev_get_priv(dev); 936 937 debug("%s(dev=%p):\n", __func__, dev); 938 939 clrbits_le32(&eqos->mac_regs->configuration, 940 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); 941 942 return 0; 943 } 944 945 static int eqos_set_mii_speed_100(struct udevice *dev) 946 { 947 struct eqos_priv *eqos = dev_get_priv(dev); 948 949 debug("%s(dev=%p):\n", __func__, dev); 950 951 setbits_le32(&eqos->mac_regs->configuration, 952 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); 953 954 return 0; 955 } 956 957 static int eqos_set_mii_speed_10(struct udevice *dev) 958 { 959 struct eqos_priv *eqos = dev_get_priv(dev); 960 961 debug("%s(dev=%p):\n", __func__, dev); 962 963 clrsetbits_le32(&eqos->mac_regs->configuration, 964 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS); 965 966 return 0; 967 } 968 969 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev) 970 { 971 #ifdef CONFIG_CLK 972 struct eqos_priv *eqos = dev_get_priv(dev); 973 ulong rate; 974 int ret; 975 976 debug("%s(dev=%p):\n", __func__, dev); 977 978 switch (eqos->phy->speed) { 979 case SPEED_1000: 980 rate = 125 * 1000 * 1000; 981 break; 982 case SPEED_100: 983 rate = 25 * 1000 * 1000; 984 break; 985 case SPEED_10: 986 rate = 2.5 * 1000 * 1000; 987 break; 988 default: 989 pr_err("invalid speed %d", eqos->phy->speed); 990 return -EINVAL; 991 } 992 993 ret = clk_set_rate(&eqos->clk_tx, rate); 994 if (ret < 0) { 995 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); 996 return ret; 997 } 998 #endif 999 1000 return 0; 1001 } 1002 1003 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev) 1004 { 1005 return 0; 1006 } 1007 1008 static int eqos_set_tx_clk_speed_imx(struct udevice *dev) 1009 { 1010 struct eqos_priv *eqos = dev_get_priv(dev); 1011 ulong rate; 1012 int ret; 1013 1014 debug("%s(dev=%p):\n", __func__, dev); 1015 1016 switch (eqos->phy->speed) { 1017 case SPEED_1000: 1018 rate = 125 * 1000 * 1000; 1019 break; 1020 case SPEED_100: 1021 rate = 25 * 1000 * 1000; 1022 break; 1023 case SPEED_10: 1024 rate = 2.5 * 1000 * 1000; 1025 break; 1026 default: 1027 pr_err("invalid speed %d", eqos->phy->speed); 1028 return -EINVAL; 1029 } 1030 1031 ret = imx_eqos_txclk_set_rate(rate); 1032 if (ret < 0) { 1033 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret); 1034 return ret; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int eqos_adjust_link(struct udevice *dev) 1041 { 1042 struct eqos_priv *eqos = dev_get_priv(dev); 1043 int ret; 1044 bool en_calibration; 1045 1046 debug("%s(dev=%p):\n", __func__, dev); 1047 1048 if (eqos->phy->duplex) 1049 ret = eqos_set_full_duplex(dev); 1050 else 1051 ret = eqos_set_half_duplex(dev); 1052 if (ret < 0) { 1053 pr_err("eqos_set_*_duplex() failed: %d", ret); 1054 return ret; 1055 } 1056 1057 switch (eqos->phy->speed) { 1058 case SPEED_1000: 1059 en_calibration = true; 1060 ret = eqos_set_gmii_speed(dev); 1061 break; 1062 case SPEED_100: 1063 en_calibration = true; 1064 ret = eqos_set_mii_speed_100(dev); 1065 break; 1066 case SPEED_10: 1067 en_calibration = false; 1068 ret = eqos_set_mii_speed_10(dev); 1069 break; 1070 default: 1071 pr_err("invalid speed %d", eqos->phy->speed); 1072 return -EINVAL; 1073 } 1074 if (ret < 0) { 1075 pr_err("eqos_set_*mii_speed*() failed: %d", ret); 1076 return ret; 1077 } 1078 1079 if (en_calibration) { 1080 ret = eqos->config->ops->eqos_calibrate_pads(dev); 1081 if (ret < 0) { 1082 pr_err("eqos_calibrate_pads() failed: %d", 1083 ret); 1084 return ret; 1085 } 1086 } else { 1087 ret = eqos->config->ops->eqos_disable_calibration(dev); 1088 if (ret < 0) { 1089 pr_err("eqos_disable_calibration() failed: %d", 1090 ret); 1091 return ret; 1092 } 1093 } 1094 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev); 1095 if (ret < 0) { 1096 pr_err("eqos_set_tx_clk_speed() failed: %d", ret); 1097 return ret; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int eqos_write_hwaddr(struct udevice *dev) 1104 { 1105 struct eth_pdata *plat = dev_get_platdata(dev); 1106 struct eqos_priv *eqos = dev_get_priv(dev); 1107 uint32_t val; 1108 1109 /* 1110 * This function may be called before start() or after stop(). At that 1111 * time, on at least some configurations of the EQoS HW, all clocks to 1112 * the EQoS HW block will be stopped, and a reset signal applied. If 1113 * any register access is attempted in this state, bus timeouts or CPU 1114 * hangs may occur. This check prevents that. 1115 * 1116 * A simple solution to this problem would be to not implement 1117 * write_hwaddr(), since start() always writes the MAC address into HW 1118 * anyway. However, it is desirable to implement write_hwaddr() to 1119 * support the case of SW that runs subsequent to U-Boot which expects 1120 * the MAC address to already be programmed into the EQoS registers, 1121 * which must happen irrespective of whether the U-Boot user (or 1122 * scripts) actually made use of the EQoS device, and hence 1123 * irrespective of whether start() was ever called. 1124 * 1125 * Note that this requirement by subsequent SW is not valid for 1126 * Tegra186, and is likely not valid for any non-PCI instantiation of 1127 * the EQoS HW block. This function is implemented solely as 1128 * future-proofing with the expectation the driver will eventually be 1129 * ported to some system where the expectation above is true. 1130 */ 1131 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok) 1132 return 0; 1133 1134 /* Update the MAC address */ 1135 val = (plat->enetaddr[5] << 8) | 1136 (plat->enetaddr[4]); 1137 writel(val, &eqos->mac_regs->address0_high); 1138 val = (plat->enetaddr[3] << 24) | 1139 (plat->enetaddr[2] << 16) | 1140 (plat->enetaddr[1] << 8) | 1141 (plat->enetaddr[0]); 1142 writel(val, &eqos->mac_regs->address0_low); 1143 1144 return 0; 1145 } 1146 1147 static int eqos_start(struct udevice *dev) 1148 { 1149 struct eqos_priv *eqos = dev_get_priv(dev); 1150 int ret, i; 1151 ulong rate; 1152 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; 1153 ulong last_rx_desc; 1154 1155 debug("%s(dev=%p):\n", __func__, dev); 1156 1157 eqos->tx_desc_idx = 0; 1158 eqos->rx_desc_idx = 0; 1159 1160 ret = eqos->config->ops->eqos_start_clks(dev); 1161 if (ret < 0) { 1162 pr_err("eqos_start_clks() failed: %d", ret); 1163 goto err; 1164 } 1165 1166 ret = eqos->config->ops->eqos_start_resets(dev); 1167 if (ret < 0) { 1168 pr_err("eqos_start_resets() failed: %d", ret); 1169 goto err_stop_clks; 1170 } 1171 1172 udelay(10); 1173 1174 eqos->reg_access_ok = true; 1175 1176 ret = wait_for_bit_le32(&eqos->dma_regs->mode, 1177 EQOS_DMA_MODE_SWR, false, 1178 eqos->config->swr_wait, false); 1179 if (ret) { 1180 pr_err("EQOS_DMA_MODE_SWR stuck"); 1181 goto err_stop_resets; 1182 } 1183 1184 ret = eqos->config->ops->eqos_calibrate_pads(dev); 1185 if (ret < 0) { 1186 pr_err("eqos_calibrate_pads() failed: %d", ret); 1187 goto err_stop_resets; 1188 } 1189 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); 1190 1191 val = (rate / 1000000) - 1; 1192 writel(val, &eqos->mac_regs->us_tic_counter); 1193 1194 /* 1195 * if PHY was already connected and configured, 1196 * don't need to reconnect/reconfigure again 1197 */ 1198 if (!eqos->phy) { 1199 int addr = -1; 1200 #ifdef CONFIG_DM_ETH_PHY 1201 addr = eth_phy_get_addr(dev); 1202 #endif 1203 #ifdef DWC_NET_PHYADDR 1204 addr = DWC_NET_PHYADDR; 1205 #endif 1206 eqos->phy = phy_connect(eqos->mii, addr, dev, 1207 eqos->config->interface(dev)); 1208 if (!eqos->phy) { 1209 pr_err("phy_connect() failed"); 1210 goto err_stop_resets; 1211 } 1212 1213 if (eqos->max_speed) { 1214 ret = phy_set_supported(eqos->phy, eqos->max_speed); 1215 if (ret) { 1216 pr_err("phy_set_supported() failed: %d", ret); 1217 goto err_shutdown_phy; 1218 } 1219 } 1220 1221 ret = phy_config(eqos->phy); 1222 if (ret < 0) { 1223 pr_err("phy_config() failed: %d", ret); 1224 goto err_shutdown_phy; 1225 } 1226 } 1227 1228 ret = phy_startup(eqos->phy); 1229 if (ret < 0) { 1230 pr_err("phy_startup() failed: %d", ret); 1231 goto err_shutdown_phy; 1232 } 1233 1234 if (!eqos->phy->link) { 1235 pr_err("No link"); 1236 goto err_shutdown_phy; 1237 } 1238 1239 ret = eqos_adjust_link(dev); 1240 if (ret < 0) { 1241 pr_err("eqos_adjust_link() failed: %d", ret); 1242 goto err_shutdown_phy; 1243 } 1244 1245 /* Configure MTL */ 1246 writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100); 1247 1248 /* Enable Store and Forward mode for TX */ 1249 /* Program Tx operating mode */ 1250 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, 1251 EQOS_MTL_TXQ0_OPERATION_MODE_TSF | 1252 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << 1253 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); 1254 1255 /* Transmit Queue weight */ 1256 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight); 1257 1258 /* Enable Store and Forward mode for RX, since no jumbo frame */ 1259 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1260 EQOS_MTL_RXQ0_OPERATION_MODE_RSF | 1261 EQOS_MTL_RXQ0_OPERATION_MODE_FEP | 1262 EQOS_MTL_RXQ0_OPERATION_MODE_FUP); 1263 1264 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ 1265 val = readl(&eqos->mac_regs->hw_feature1); 1266 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & 1267 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; 1268 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & 1269 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; 1270 1271 /* 1272 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. 1273 * r/tqs is encoded as (n / 256) - 1. 1274 */ 1275 tqs = (128 << tx_fifo_sz) / 256 - 1; 1276 rqs = (128 << rx_fifo_sz) / 256 - 1; 1277 1278 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, 1279 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << 1280 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, 1281 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); 1282 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1283 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK << 1284 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, 1285 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); 1286 1287 /* Flow control used only if each channel gets 4KB or more FIFO */ 1288 if (rqs >= ((4096 / 256) - 1)) { 1289 u32 rfd, rfa; 1290 1291 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1292 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC); 1293 1294 /* 1295 * Set Threshold for Activating Flow Contol space for min 2 1296 * frames ie, (1500 * 1) = 1500 bytes. 1297 * 1298 * Set Threshold for Deactivating Flow Contol for space of 1299 * min 1 frame (frame size 1500bytes) in receive fifo 1300 */ 1301 if (rqs == ((4096 / 256) - 1)) { 1302 /* 1303 * This violates the above formula because of FIFO size 1304 * limit therefore overflow may occur inspite of this. 1305 */ 1306 rfd = 0x3; /* Full-3K */ 1307 rfa = 0x1; /* Full-1.5K */ 1308 } else if (rqs == ((8192 / 256) - 1)) { 1309 rfd = 0x6; /* Full-4K */ 1310 rfa = 0xa; /* Full-6K */ 1311 } else if (rqs == ((16384 / 256) - 1)) { 1312 rfd = 0x6; /* Full-4K */ 1313 rfa = 0x12; /* Full-10K */ 1314 } else { 1315 rfd = 0x6; /* Full-4K */ 1316 rfa = 0x1E; /* Full-16K */ 1317 } 1318 1319 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1320 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK << 1321 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | 1322 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK << 1323 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT), 1324 (rfd << 1325 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | 1326 (rfa << 1327 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)); 1328 } 1329 1330 /* Configure MAC */ 1331 1332 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, 1333 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << 1334 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, 1335 eqos->config->config_mac << 1336 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); 1337 1338 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, 1339 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << 1340 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, 1341 0x2 << 1342 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); 1343 1344 /* Multicast and Broadcast Queue Enable */ 1345 setbits_le32(&eqos->mac_regs->unused_0a4, 1346 0x00100000); 1347 /* enable promise mode */ 1348 setbits_le32(&eqos->mac_regs->unused_004[1], 1349 0x1); 1350 1351 /* Set TX flow control parameters */ 1352 /* Set Pause Time */ 1353 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, 1354 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); 1355 /* Assign priority for TX flow control */ 1356 clrbits_le32(&eqos->mac_regs->txq_prty_map0, 1357 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK << 1358 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT); 1359 /* Assign priority for RX flow control */ 1360 clrbits_le32(&eqos->mac_regs->rxq_ctrl2, 1361 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK << 1362 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT); 1363 /* Enable flow control */ 1364 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, 1365 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE); 1366 setbits_le32(&eqos->mac_regs->rx_flow_ctrl, 1367 EQOS_MAC_RX_FLOW_CTRL_RFE); 1368 1369 clrsetbits_le32(&eqos->mac_regs->configuration, 1370 EQOS_MAC_CONFIGURATION_GPSLCE | 1371 EQOS_MAC_CONFIGURATION_WD | 1372 EQOS_MAC_CONFIGURATION_JD | 1373 EQOS_MAC_CONFIGURATION_JE, 1374 EQOS_MAC_CONFIGURATION_CST | 1375 EQOS_MAC_CONFIGURATION_ACS); 1376 1377 eqos_write_hwaddr(dev); 1378 1379 /* Configure DMA */ 1380 1381 /* Enable OSP mode */ 1382 setbits_le32(&eqos->dma_regs->ch0_tx_control, 1383 EQOS_DMA_CH0_TX_CONTROL_OSP); 1384 1385 /* RX buffer size. Must be a multiple of bus width */ 1386 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, 1387 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK << 1388 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, 1389 EQOS_MAX_PACKET_SIZE << 1390 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); 1391 1392 setbits_le32(&eqos->dma_regs->ch0_control, 1393 EQOS_DMA_CH0_CONTROL_PBLX8); 1394 1395 /* 1396 * Burst length must be < 1/2 FIFO size. 1397 * FIFO size in tqs is encoded as (n / 256) - 1. 1398 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. 1399 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. 1400 */ 1401 pbl = tqs + 1; 1402 if (pbl > 32) 1403 pbl = 32; 1404 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control, 1405 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK << 1406 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, 1407 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); 1408 1409 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, 1410 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK << 1411 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, 1412 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); 1413 1414 /* DMA performance configuration */ 1415 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | 1416 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 | 1417 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4; 1418 writel(val, &eqos->dma_regs->sysbus_mode); 1419 1420 /* Set up descriptors */ 1421 1422 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE); 1423 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { 1424 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); 1425 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + 1426 (i * EQOS_MAX_PACKET_SIZE)); 1427 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; 1428 mb(); 1429 eqos->config->ops->eqos_flush_desc(rx_desc); 1430 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf + 1431 (i * EQOS_MAX_PACKET_SIZE), 1432 EQOS_MAX_PACKET_SIZE); 1433 } 1434 1435 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); 1436 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); 1437 writel(EQOS_DESCRIPTORS_TX - 1, 1438 &eqos->dma_regs->ch0_txdesc_ring_length); 1439 1440 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); 1441 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address); 1442 writel(EQOS_DESCRIPTORS_RX - 1, 1443 &eqos->dma_regs->ch0_rxdesc_ring_length); 1444 1445 /* Enable everything */ 1446 setbits_le32(&eqos->dma_regs->ch0_tx_control, 1447 EQOS_DMA_CH0_TX_CONTROL_ST); 1448 setbits_le32(&eqos->dma_regs->ch0_rx_control, 1449 EQOS_DMA_CH0_RX_CONTROL_SR); 1450 setbits_le32(&eqos->mac_regs->configuration, 1451 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); 1452 1453 /* TX tail pointer not written until we need to TX a packet */ 1454 /* 1455 * Point RX tail pointer at last descriptor. Ideally, we'd point at the 1456 * first descriptor, implying all descriptors were available. However, 1457 * that's not distinguishable from none of the descriptors being 1458 * available. 1459 */ 1460 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]); 1461 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); 1462 1463 eqos->started = true; 1464 1465 debug("%s: OK\n", __func__); 1466 return 0; 1467 1468 err_shutdown_phy: 1469 phy_shutdown(eqos->phy); 1470 err_stop_resets: 1471 eqos->config->ops->eqos_stop_resets(dev); 1472 err_stop_clks: 1473 eqos->config->ops->eqos_stop_clks(dev); 1474 err: 1475 pr_err("FAILED: %d", ret); 1476 return ret; 1477 } 1478 1479 static void eqos_stop(struct udevice *dev) 1480 { 1481 struct eqos_priv *eqos = dev_get_priv(dev); 1482 int i; 1483 1484 debug("%s(dev=%p):\n", __func__, dev); 1485 1486 if (!eqos->started) 1487 return; 1488 eqos->started = false; 1489 eqos->reg_access_ok = false; 1490 1491 /* Disable TX DMA */ 1492 clrbits_le32(&eqos->dma_regs->ch0_tx_control, 1493 EQOS_DMA_CH0_TX_CONTROL_ST); 1494 1495 /* Wait for TX all packets to drain out of MTL */ 1496 for (i = 0; i < 1000000; i++) { 1497 u32 val = readl(&eqos->mtl_regs->txq0_debug); 1498 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & 1499 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK; 1500 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS; 1501 if ((trcsts != 1) && (!txqsts)) 1502 break; 1503 } 1504 1505 /* Turn off MAC TX and RX */ 1506 clrbits_le32(&eqos->mac_regs->configuration, 1507 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); 1508 1509 /* Wait for all RX packets to drain out of MTL */ 1510 for (i = 0; i < 1000000; i++) { 1511 u32 val = readl(&eqos->mtl_regs->rxq0_debug); 1512 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & 1513 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK; 1514 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & 1515 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK; 1516 if ((!prxq) && (!rxqsts)) 1517 break; 1518 } 1519 1520 /* Turn off RX DMA */ 1521 clrbits_le32(&eqos->dma_regs->ch0_rx_control, 1522 EQOS_DMA_CH0_RX_CONTROL_SR); 1523 1524 if (eqos->phy) { 1525 phy_shutdown(eqos->phy); 1526 } 1527 eqos->config->ops->eqos_stop_resets(dev); 1528 eqos->config->ops->eqos_stop_clks(dev); 1529 1530 debug("%s: OK\n", __func__); 1531 } 1532 1533 static int eqos_send(struct udevice *dev, void *packet, int length) 1534 { 1535 struct eqos_priv *eqos = dev_get_priv(dev); 1536 struct eqos_desc *tx_desc; 1537 int i; 1538 1539 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, 1540 length); 1541 1542 memcpy(eqos->tx_dma_buf, packet, length); 1543 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length); 1544 1545 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]); 1546 eqos->tx_desc_idx++; 1547 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; 1548 1549 tx_desc->des0 = (ulong)eqos->tx_dma_buf; 1550 tx_desc->des1 = 0; 1551 tx_desc->des2 = length; 1552 /* 1553 * Make sure that if HW sees the _OWN write below, it will see all the 1554 * writes to the rest of the descriptor too. 1555 */ 1556 mb(); 1557 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; 1558 eqos->config->ops->eqos_flush_desc(tx_desc); 1559 1560 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), 1561 &eqos->dma_regs->ch0_txdesc_tail_pointer); 1562 1563 for (i = 0; i < 1000000; i++) { 1564 eqos->config->ops->eqos_inval_desc(tx_desc); 1565 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) 1566 return 0; 1567 udelay(1); 1568 } 1569 1570 debug("%s: TX timeout\n", __func__); 1571 1572 return -ETIMEDOUT; 1573 } 1574 1575 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) 1576 { 1577 struct eqos_priv *eqos = dev_get_priv(dev); 1578 struct eqos_desc *rx_desc; 1579 int length; 1580 1581 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); 1582 1583 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); 1584 eqos->config->ops->eqos_inval_desc(rx_desc); 1585 if (rx_desc->des3 & EQOS_DESC3_OWN) { 1586 debug("%s: RX packet not available\n", __func__); 1587 return -EAGAIN; 1588 } 1589 1590 *packetp = eqos->rx_dma_buf + 1591 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); 1592 length = rx_desc->des3 & 0x7fff; 1593 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); 1594 1595 eqos->config->ops->eqos_inval_buffer(*packetp, length); 1596 1597 return length; 1598 } 1599 1600 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) 1601 { 1602 struct eqos_priv *eqos = dev_get_priv(dev); 1603 uchar *packet_expected; 1604 struct eqos_desc *rx_desc; 1605 1606 debug("%s(packet=%p, length=%d)\n", __func__, packet, length); 1607 1608 packet_expected = eqos->rx_dma_buf + 1609 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); 1610 if (packet != packet_expected) { 1611 debug("%s: Unexpected packet (expected %p)\n", __func__, 1612 packet_expected); 1613 return -EINVAL; 1614 } 1615 1616 eqos->config->ops->eqos_inval_buffer(packet, length); 1617 1618 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); 1619 1620 rx_desc->des0 = 0; 1621 mb(); 1622 eqos->config->ops->eqos_flush_desc(rx_desc); 1623 eqos->config->ops->eqos_inval_buffer(packet, length); 1624 rx_desc->des0 = (u32)(ulong)packet; 1625 rx_desc->des1 = 0; 1626 rx_desc->des2 = 0; 1627 /* 1628 * Make sure that if HW sees the _OWN write below, it will see all the 1629 * writes to the rest of the descriptor too. 1630 */ 1631 mb(); 1632 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; 1633 eqos->config->ops->eqos_flush_desc(rx_desc); 1634 1635 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); 1636 1637 eqos->rx_desc_idx++; 1638 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX; 1639 1640 return 0; 1641 } 1642 1643 static int eqos_probe_resources_core(struct udevice *dev) 1644 { 1645 struct eqos_priv *eqos = dev_get_priv(dev); 1646 int ret; 1647 1648 debug("%s(dev=%p):\n", __func__, dev); 1649 1650 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX + 1651 EQOS_DESCRIPTORS_RX); 1652 if (!eqos->descs) { 1653 debug("%s: eqos_alloc_descs() failed\n", __func__); 1654 ret = -ENOMEM; 1655 goto err; 1656 } 1657 eqos->tx_descs = (struct eqos_desc *)eqos->descs; 1658 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX); 1659 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs, 1660 eqos->rx_descs); 1661 1662 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); 1663 if (!eqos->tx_dma_buf) { 1664 debug("%s: memalign(tx_dma_buf) failed\n", __func__); 1665 ret = -ENOMEM; 1666 goto err_free_descs; 1667 } 1668 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf); 1669 1670 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE); 1671 if (!eqos->rx_dma_buf) { 1672 debug("%s: memalign(rx_dma_buf) failed\n", __func__); 1673 ret = -ENOMEM; 1674 goto err_free_tx_dma_buf; 1675 } 1676 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf); 1677 1678 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE); 1679 if (!eqos->rx_pkt) { 1680 debug("%s: malloc(rx_pkt) failed\n", __func__); 1681 ret = -ENOMEM; 1682 goto err_free_rx_dma_buf; 1683 } 1684 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); 1685 1686 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf, 1687 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX); 1688 1689 debug("%s: OK\n", __func__); 1690 return 0; 1691 1692 err_free_rx_dma_buf: 1693 free(eqos->rx_dma_buf); 1694 err_free_tx_dma_buf: 1695 free(eqos->tx_dma_buf); 1696 err_free_descs: 1697 eqos_free_descs(eqos->descs); 1698 err: 1699 1700 debug("%s: returns %d\n", __func__, ret); 1701 return ret; 1702 } 1703 1704 static int eqos_remove_resources_core(struct udevice *dev) 1705 { 1706 struct eqos_priv *eqos = dev_get_priv(dev); 1707 1708 debug("%s(dev=%p):\n", __func__, dev); 1709 1710 free(eqos->rx_pkt); 1711 free(eqos->rx_dma_buf); 1712 free(eqos->tx_dma_buf); 1713 eqos_free_descs(eqos->descs); 1714 1715 debug("%s: OK\n", __func__); 1716 return 0; 1717 } 1718 1719 static int eqos_probe_resources_tegra186(struct udevice *dev) 1720 { 1721 struct eqos_priv *eqos = dev_get_priv(dev); 1722 int ret; 1723 1724 debug("%s(dev=%p):\n", __func__, dev); 1725 1726 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); 1727 if (ret) { 1728 pr_err("reset_get_by_name(rst) failed: %d", ret); 1729 return ret; 1730 } 1731 1732 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, 1733 &eqos->phy_reset_gpio, 1734 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 1735 if (ret) { 1736 pr_err("gpio_request_by_name(phy reset) failed: %d", ret); 1737 goto err_free_reset_eqos; 1738 } 1739 1740 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); 1741 if (ret) { 1742 pr_err("clk_get_by_name(slave_bus) failed: %d", ret); 1743 goto err_free_gpio_phy_reset; 1744 } 1745 1746 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); 1747 if (ret) { 1748 pr_err("clk_get_by_name(master_bus) failed: %d", ret); 1749 goto err_free_clk_slave_bus; 1750 } 1751 1752 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); 1753 if (ret) { 1754 pr_err("clk_get_by_name(rx) failed: %d", ret); 1755 goto err_free_clk_master_bus; 1756 } 1757 1758 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); 1759 if (ret) { 1760 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret); 1761 goto err_free_clk_rx; 1762 return ret; 1763 } 1764 1765 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); 1766 if (ret) { 1767 pr_err("clk_get_by_name(tx) failed: %d", ret); 1768 goto err_free_clk_ptp_ref; 1769 } 1770 1771 debug("%s: OK\n", __func__); 1772 return 0; 1773 1774 err_free_clk_ptp_ref: 1775 clk_free(&eqos->clk_ptp_ref); 1776 err_free_clk_rx: 1777 clk_free(&eqos->clk_rx); 1778 err_free_clk_master_bus: 1779 clk_free(&eqos->clk_master_bus); 1780 err_free_clk_slave_bus: 1781 clk_free(&eqos->clk_slave_bus); 1782 err_free_gpio_phy_reset: 1783 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1784 err_free_reset_eqos: 1785 reset_free(&eqos->reset_ctl); 1786 1787 debug("%s: returns %d\n", __func__, ret); 1788 return ret; 1789 } 1790 1791 /* board-specific Ethernet Interface initializations. */ 1792 __weak int board_interface_eth_init(struct udevice *dev, 1793 phy_interface_t interface_type) 1794 { 1795 return 0; 1796 } 1797 1798 static int eqos_probe_resources_stm32(struct udevice *dev) 1799 { 1800 struct eqos_priv *eqos = dev_get_priv(dev); 1801 int ret; 1802 phy_interface_t interface; 1803 struct ofnode_phandle_args phandle_args; 1804 1805 debug("%s(dev=%p):\n", __func__, dev); 1806 1807 interface = eqos->config->interface(dev); 1808 1809 if (interface == PHY_INTERFACE_MODE_NONE) { 1810 pr_err("Invalid PHY interface\n"); 1811 return -EINVAL; 1812 } 1813 1814 ret = board_interface_eth_init(dev, interface); 1815 if (ret) 1816 return -EINVAL; 1817 1818 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); 1819 1820 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); 1821 if (ret) { 1822 pr_err("clk_get_by_name(master_bus) failed: %d", ret); 1823 goto err_probe; 1824 } 1825 1826 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); 1827 if (ret) { 1828 pr_err("clk_get_by_name(rx) failed: %d", ret); 1829 goto err_free_clk_master_bus; 1830 } 1831 1832 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); 1833 if (ret) { 1834 pr_err("clk_get_by_name(tx) failed: %d", ret); 1835 goto err_free_clk_rx; 1836 } 1837 1838 /* Get ETH_CLK clocks (optional) */ 1839 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); 1840 if (ret) 1841 pr_warn("No phy clock provided %d", ret); 1842 1843 eqos->phyaddr = -1; 1844 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, 1845 &phandle_args); 1846 if (!ret) { 1847 /* search "reset-gpios" in phy node */ 1848 ret = gpio_request_by_name_nodev(phandle_args.node, 1849 "reset-gpios", 0, 1850 &eqos->phy_reset_gpio, 1851 GPIOD_IS_OUT | 1852 GPIOD_IS_OUT_ACTIVE); 1853 if (ret) 1854 pr_warn("gpio_request_by_name(phy reset) not provided %d", 1855 ret); 1856 1857 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node, 1858 "reg", -1); 1859 } 1860 1861 debug("%s: OK\n", __func__); 1862 return 0; 1863 1864 err_free_clk_rx: 1865 clk_free(&eqos->clk_rx); 1866 err_free_clk_master_bus: 1867 clk_free(&eqos->clk_master_bus); 1868 err_probe: 1869 1870 debug("%s: returns %d\n", __func__, ret); 1871 return ret; 1872 } 1873 1874 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev) 1875 { 1876 const char *phy_mode; 1877 phy_interface_t interface = PHY_INTERFACE_MODE_NONE; 1878 1879 debug("%s(dev=%p):\n", __func__, dev); 1880 1881 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1882 NULL); 1883 if (phy_mode) 1884 interface = phy_get_interface_by_name(phy_mode); 1885 1886 return interface; 1887 } 1888 1889 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev) 1890 { 1891 return PHY_INTERFACE_MODE_MII; 1892 } 1893 1894 static int eqos_probe_resources_imx(struct udevice *dev) 1895 { 1896 struct eqos_priv *eqos = dev_get_priv(dev); 1897 phy_interface_t interface; 1898 1899 debug("%s(dev=%p):\n", __func__, dev); 1900 1901 interface = eqos->config->interface(dev); 1902 1903 if (interface == PHY_INTERFACE_MODE_NONE) { 1904 pr_err("Invalid PHY interface\n"); 1905 return -EINVAL; 1906 } 1907 1908 debug("%s: OK\n", __func__); 1909 return 0; 1910 } 1911 1912 static phy_interface_t eqos_get_interface_imx(struct udevice *dev) 1913 { 1914 const char *phy_mode; 1915 phy_interface_t interface = PHY_INTERFACE_MODE_NONE; 1916 1917 debug("%s(dev=%p):\n", __func__, dev); 1918 1919 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1920 NULL); 1921 if (phy_mode) 1922 interface = phy_get_interface_by_name(phy_mode); 1923 1924 return interface; 1925 } 1926 1927 static int eqos_remove_resources_tegra186(struct udevice *dev) 1928 { 1929 struct eqos_priv *eqos = dev_get_priv(dev); 1930 1931 debug("%s(dev=%p):\n", __func__, dev); 1932 1933 #ifdef CONFIG_CLK 1934 clk_free(&eqos->clk_tx); 1935 clk_free(&eqos->clk_ptp_ref); 1936 clk_free(&eqos->clk_rx); 1937 clk_free(&eqos->clk_slave_bus); 1938 clk_free(&eqos->clk_master_bus); 1939 #endif 1940 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1941 reset_free(&eqos->reset_ctl); 1942 1943 debug("%s: OK\n", __func__); 1944 return 0; 1945 } 1946 1947 static int eqos_remove_resources_stm32(struct udevice *dev) 1948 { 1949 #ifdef CONFIG_CLK 1950 struct eqos_priv *eqos = dev_get_priv(dev); 1951 1952 debug("%s(dev=%p):\n", __func__, dev); 1953 1954 clk_free(&eqos->clk_tx); 1955 clk_free(&eqos->clk_rx); 1956 clk_free(&eqos->clk_master_bus); 1957 if (clk_valid(&eqos->clk_ck)) 1958 clk_free(&eqos->clk_ck); 1959 #endif 1960 1961 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) 1962 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1963 1964 debug("%s: OK\n", __func__); 1965 return 0; 1966 } 1967 1968 static int eqos_remove_resources_imx(struct udevice *dev) 1969 { 1970 return 0; 1971 } 1972 1973 static int eqos_probe(struct udevice *dev) 1974 { 1975 struct eqos_priv *eqos = dev_get_priv(dev); 1976 int ret; 1977 1978 debug("%s(dev=%p):\n", __func__, dev); 1979 1980 eqos->dev = dev; 1981 eqos->config = (void *)dev_get_driver_data(dev); 1982 1983 eqos->regs = devfdt_get_addr(dev); 1984 if (eqos->regs == FDT_ADDR_T_NONE) { 1985 pr_err("devfdt_get_addr() failed"); 1986 return -ENODEV; 1987 } 1988 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); 1989 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); 1990 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); 1991 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); 1992 1993 ret = eqos_probe_resources_core(dev); 1994 if (ret < 0) { 1995 pr_err("eqos_probe_resources_core() failed: %d", ret); 1996 return ret; 1997 } 1998 1999 ret = eqos->config->ops->eqos_probe_resources(dev); 2000 if (ret < 0) { 2001 pr_err("eqos_probe_resources() failed: %d", ret); 2002 goto err_remove_resources_core; 2003 } 2004 2005 #ifdef CONFIG_DM_ETH_PHY 2006 eqos->mii = eth_phy_get_mdio_bus(dev); 2007 #endif 2008 if (!eqos->mii) { 2009 eqos->mii = mdio_alloc(); 2010 if (!eqos->mii) { 2011 pr_err("mdio_alloc() failed"); 2012 ret = -ENOMEM; 2013 goto err_remove_resources_tegra; 2014 } 2015 eqos->mii->read = eqos_mdio_read; 2016 eqos->mii->write = eqos_mdio_write; 2017 eqos->mii->priv = eqos; 2018 strcpy(eqos->mii->name, dev->name); 2019 2020 ret = mdio_register(eqos->mii); 2021 if (ret < 0) { 2022 pr_err("mdio_register() failed: %d", ret); 2023 goto err_free_mdio; 2024 } 2025 } 2026 2027 #ifdef CONFIG_DM_ETH_PHY 2028 eth_phy_set_mdio_bus(dev, eqos->mii); 2029 #endif 2030 2031 debug("%s: OK\n", __func__); 2032 return 0; 2033 2034 err_free_mdio: 2035 mdio_free(eqos->mii); 2036 err_remove_resources_tegra: 2037 eqos->config->ops->eqos_remove_resources(dev); 2038 err_remove_resources_core: 2039 eqos_remove_resources_core(dev); 2040 2041 debug("%s: returns %d\n", __func__, ret); 2042 return ret; 2043 } 2044 2045 static int eqos_remove(struct udevice *dev) 2046 { 2047 struct eqos_priv *eqos = dev_get_priv(dev); 2048 2049 debug("%s(dev=%p):\n", __func__, dev); 2050 2051 mdio_unregister(eqos->mii); 2052 mdio_free(eqos->mii); 2053 eqos->config->ops->eqos_remove_resources(dev); 2054 2055 eqos_probe_resources_core(dev); 2056 2057 debug("%s: OK\n", __func__); 2058 return 0; 2059 } 2060 2061 static const struct eth_ops eqos_ops = { 2062 .start = eqos_start, 2063 .stop = eqos_stop, 2064 .send = eqos_send, 2065 .recv = eqos_recv, 2066 .free_pkt = eqos_free_pkt, 2067 .write_hwaddr = eqos_write_hwaddr, 2068 }; 2069 2070 static struct eqos_ops eqos_tegra186_ops = { 2071 .eqos_inval_desc = eqos_inval_desc_tegra186, 2072 .eqos_flush_desc = eqos_flush_desc_tegra186, 2073 .eqos_inval_buffer = eqos_inval_buffer_tegra186, 2074 .eqos_flush_buffer = eqos_flush_buffer_tegra186, 2075 .eqos_probe_resources = eqos_probe_resources_tegra186, 2076 .eqos_remove_resources = eqos_remove_resources_tegra186, 2077 .eqos_stop_resets = eqos_stop_resets_tegra186, 2078 .eqos_start_resets = eqos_start_resets_tegra186, 2079 .eqos_stop_clks = eqos_stop_clks_tegra186, 2080 .eqos_start_clks = eqos_start_clks_tegra186, 2081 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186, 2082 .eqos_disable_calibration = eqos_disable_calibration_tegra186, 2083 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186, 2084 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186 2085 }; 2086 2087 static const struct eqos_config eqos_tegra186_config = { 2088 .reg_access_always_ok = false, 2089 .mdio_wait = 10, 2090 .swr_wait = 10, 2091 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, 2092 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35, 2093 .interface = eqos_get_interface_tegra186, 2094 .ops = &eqos_tegra186_ops 2095 }; 2096 2097 static struct eqos_ops eqos_stm32_ops = { 2098 .eqos_inval_desc = eqos_inval_desc_generic, 2099 .eqos_flush_desc = eqos_flush_desc_generic, 2100 .eqos_inval_buffer = eqos_inval_buffer_generic, 2101 .eqos_flush_buffer = eqos_flush_buffer_generic, 2102 .eqos_probe_resources = eqos_probe_resources_stm32, 2103 .eqos_remove_resources = eqos_remove_resources_stm32, 2104 .eqos_stop_resets = eqos_stop_resets_stm32, 2105 .eqos_start_resets = eqos_start_resets_stm32, 2106 .eqos_stop_clks = eqos_stop_clks_stm32, 2107 .eqos_start_clks = eqos_start_clks_stm32, 2108 .eqos_calibrate_pads = eqos_calibrate_pads_stm32, 2109 .eqos_disable_calibration = eqos_disable_calibration_stm32, 2110 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32, 2111 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 2112 }; 2113 2114 static const struct eqos_config eqos_stm32_config = { 2115 .reg_access_always_ok = false, 2116 .mdio_wait = 10000, 2117 .swr_wait = 50, 2118 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, 2119 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, 2120 .interface = eqos_get_interface_stm32, 2121 .ops = &eqos_stm32_ops 2122 }; 2123 2124 static struct eqos_ops eqos_imx_ops = { 2125 .eqos_inval_desc = eqos_inval_desc_generic, 2126 .eqos_flush_desc = eqos_flush_desc_generic, 2127 .eqos_inval_buffer = eqos_inval_buffer_generic, 2128 .eqos_flush_buffer = eqos_flush_buffer_generic, 2129 .eqos_probe_resources = eqos_probe_resources_imx, 2130 .eqos_remove_resources = eqos_remove_resources_imx, 2131 .eqos_stop_resets = eqos_stop_resets_imx, 2132 .eqos_start_resets = eqos_start_resets_imx, 2133 .eqos_stop_clks = eqos_stop_clks_imx, 2134 .eqos_start_clks = eqos_start_clks_imx, 2135 .eqos_calibrate_pads = eqos_calibrate_pads_imx, 2136 .eqos_disable_calibration = eqos_disable_calibration_imx, 2137 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx, 2138 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx 2139 }; 2140 2141 struct eqos_config eqos_imx_config = { 2142 .reg_access_always_ok = false, 2143 .mdio_wait = 10000, 2144 .swr_wait = 50, 2145 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, 2146 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, 2147 .interface = eqos_get_interface_imx, 2148 .ops = &eqos_imx_ops 2149 }; 2150 2151 static const struct udevice_id eqos_ids[] = { 2152 { 2153 .compatible = "nvidia,tegra186-eqos", 2154 .data = (ulong)&eqos_tegra186_config 2155 }, 2156 { 2157 .compatible = "snps,dwmac-4.20a", 2158 .data = (ulong)&eqos_stm32_config 2159 }, 2160 { 2161 .compatible = "fsl,imx-eqos", 2162 .data = (ulong)&eqos_imx_config 2163 }, 2164 2165 { } 2166 }; 2167 2168 U_BOOT_DRIVER(eth_eqos) = { 2169 .name = "eth_eqos", 2170 .id = UCLASS_ETH, 2171 .of_match = of_match_ptr(eqos_ids), 2172 .probe = eqos_probe, 2173 .remove = eqos_remove, 2174 .ops = &eqos_ops, 2175 .priv_auto_alloc_size = sizeof(struct eqos_priv), 2176 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 2177 }; 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