1 /* 2 * Copyright (c) 2016, NVIDIA CORPORATION. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Portions based on U-Boot's rtl8169.c. 7 */ 8 9 /* 10 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of 11 * Service) IP block. The IP supports multiple options for bus type, clocking/ 12 * reset structure, and feature list. 13 * 14 * The driver is written such that generic core logic is kept separate from 15 * configuration-specific logic. Code that interacts with configuration- 16 * specific resources is split out into separate functions to avoid polluting 17 * common code. If/when this driver is enhanced to support multiple 18 * configurations, the core code should be adapted to call all configuration- 19 * specific functions through function pointers, with the definition of those 20 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data 21 * field. 22 * 23 * The following configurations are currently supported: 24 * tegra186: 25 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an 26 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and 27 * supports a single RGMII PHY. This configuration also has SW control over 28 * all clock and reset signals to the HW block. 29 */ 30 #include <common.h> 31 #include <clk.h> 32 #include <dm.h> 33 #include <errno.h> 34 #include <memalign.h> 35 #include <miiphy.h> 36 #include <net.h> 37 #include <netdev.h> 38 #include <phy.h> 39 #include <reset.h> 40 #include <wait_bit.h> 41 #include <asm/gpio.h> 42 #include <asm/io.h> 43 44 /* Core registers */ 45 46 #define EQOS_MAC_REGS_BASE 0x000 47 struct eqos_mac_regs { 48 uint32_t configuration; /* 0x000 */ 49 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ 50 uint32_t q0_tx_flow_ctrl; /* 0x070 */ 51 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ 52 uint32_t rx_flow_ctrl; /* 0x090 */ 53 uint32_t unused_094; /* 0x094 */ 54 uint32_t txq_prty_map0; /* 0x098 */ 55 uint32_t unused_09c; /* 0x09c */ 56 uint32_t rxq_ctrl0; /* 0x0a0 */ 57 uint32_t unused_0a4; /* 0x0a4 */ 58 uint32_t rxq_ctrl2; /* 0x0a8 */ 59 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ 60 uint32_t us_tic_counter; /* 0x0dc */ 61 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ 62 uint32_t hw_feature0; /* 0x11c */ 63 uint32_t hw_feature1; /* 0x120 */ 64 uint32_t hw_feature2; /* 0x124 */ 65 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ 66 uint32_t mdio_address; /* 0x200 */ 67 uint32_t mdio_data; /* 0x204 */ 68 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ 69 uint32_t address0_high; /* 0x300 */ 70 uint32_t address0_low; /* 0x304 */ 71 }; 72 73 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) 74 #define EQOS_MAC_CONFIGURATION_CST BIT(21) 75 #define EQOS_MAC_CONFIGURATION_ACS BIT(20) 76 #define EQOS_MAC_CONFIGURATION_WD BIT(19) 77 #define EQOS_MAC_CONFIGURATION_JD BIT(17) 78 #define EQOS_MAC_CONFIGURATION_JE BIT(16) 79 #define EQOS_MAC_CONFIGURATION_PS BIT(15) 80 #define EQOS_MAC_CONFIGURATION_FES BIT(14) 81 #define EQOS_MAC_CONFIGURATION_DM BIT(13) 82 #define EQOS_MAC_CONFIGURATION_TE BIT(1) 83 #define EQOS_MAC_CONFIGURATION_RE BIT(0) 84 85 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 86 #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff 87 #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) 88 89 #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) 90 91 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 92 #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff 93 94 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 95 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 96 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 97 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 98 #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 99 100 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 101 #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff 102 103 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 104 #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f 105 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 106 #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f 107 108 #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21 109 #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16 110 #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8 111 #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 112 #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 113 #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) 114 #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2 115 #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 116 #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 117 #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) 118 #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) 119 120 #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff 121 122 #define EQOS_MTL_REGS_BASE 0xd00 123 struct eqos_mtl_regs { 124 uint32_t txq0_operation_mode; /* 0xd00 */ 125 uint32_t unused_d04; /* 0xd04 */ 126 uint32_t txq0_debug; /* 0xd08 */ 127 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ 128 uint32_t txq0_quantum_weight; /* 0xd18 */ 129 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ 130 uint32_t rxq0_operation_mode; /* 0xd30 */ 131 uint32_t unused_d34; /* 0xd34 */ 132 uint32_t rxq0_debug; /* 0xd38 */ 133 }; 134 135 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 136 #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff 137 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 138 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 139 #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 140 #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) 141 #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) 142 143 #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4) 144 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 145 #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3 146 147 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 148 #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff 149 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 150 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f 151 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 152 #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f 153 #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) 154 #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) 155 156 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 157 #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff 158 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 159 #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3 160 161 #define EQOS_DMA_REGS_BASE 0x1000 162 struct eqos_dma_regs { 163 uint32_t mode; /* 0x1000 */ 164 uint32_t sysbus_mode; /* 0x1004 */ 165 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */ 166 uint32_t ch0_control; /* 0x1100 */ 167 uint32_t ch0_tx_control; /* 0x1104 */ 168 uint32_t ch0_rx_control; /* 0x1108 */ 169 uint32_t unused_110c; /* 0x110c */ 170 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */ 171 uint32_t ch0_txdesc_list_address; /* 0x1114 */ 172 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */ 173 uint32_t ch0_rxdesc_list_address; /* 0x111c */ 174 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */ 175 uint32_t unused_1124; /* 0x1124 */ 176 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */ 177 uint32_t ch0_txdesc_ring_length; /* 0x112c */ 178 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */ 179 }; 180 181 #define EQOS_DMA_MODE_SWR BIT(0) 182 183 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 184 #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf 185 #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) 186 #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) 187 #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) 188 #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) 189 190 #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) 191 192 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 193 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f 194 #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) 195 #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) 196 197 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 198 #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f 199 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 200 #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff 201 #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) 202 203 /* These registers are Tegra186-specific */ 204 #define EQOS_TEGRA186_REGS_BASE 0x8800 205 struct eqos_tegra186_regs { 206 uint32_t sdmemcomppadctrl; /* 0x8800 */ 207 uint32_t auto_cal_config; /* 0x8804 */ 208 uint32_t unused_8808; /* 0x8808 */ 209 uint32_t auto_cal_status; /* 0x880c */ 210 }; 211 212 #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) 213 214 #define EQOS_AUTO_CAL_CONFIG_START BIT(31) 215 #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29) 216 217 #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) 218 219 /* Descriptors */ 220 221 #define EQOS_DESCRIPTOR_WORDS 4 222 #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4) 223 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */ 224 #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN 225 #define EQOS_DESCRIPTORS_TX 4 226 #define EQOS_DESCRIPTORS_RX 4 227 #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) 228 #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \ 229 EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN) 230 #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN 231 #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) 232 #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) 233 234 /* 235 * Warn if the cache-line size is larger than the descriptor size. In such 236 * cases the driver will likely fail because the CPU needs to flush the cache 237 * when requeuing RX buffers, therefore descriptors written by the hardware 238 * may be discarded. Architectures with full IO coherence, such as x86, do not 239 * experience this issue, and hence are excluded from this condition. 240 * 241 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 242 * the driver to allocate descriptors from a pool of non-cached memory. 243 */ 244 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN 245 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 246 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 247 #warning Cache line size is larger than descriptor size 248 #endif 249 #endif 250 251 struct eqos_desc { 252 u32 des0; 253 u32 des1; 254 u32 des2; 255 u32 des3; 256 }; 257 258 #define EQOS_DESC3_OWN BIT(31) 259 #define EQOS_DESC3_FD BIT(29) 260 #define EQOS_DESC3_LD BIT(28) 261 #define EQOS_DESC3_BUF1V BIT(24) 262 263 struct eqos_config { 264 bool reg_access_always_ok; 265 int mdio_wait; 266 int swr_wait; 267 int config_mac; 268 int config_mac_mdio; 269 phy_interface_t (*interface)(struct udevice *dev); 270 struct eqos_ops *ops; 271 }; 272 273 struct eqos_ops { 274 void (*eqos_inval_desc)(void *desc); 275 void (*eqos_flush_desc)(void *desc); 276 void (*eqos_inval_buffer)(void *buf, size_t size); 277 void (*eqos_flush_buffer)(void *buf, size_t size); 278 int (*eqos_probe_resources)(struct udevice *dev); 279 int (*eqos_remove_resources)(struct udevice *dev); 280 int (*eqos_stop_resets)(struct udevice *dev); 281 int (*eqos_start_resets)(struct udevice *dev); 282 void (*eqos_stop_clks)(struct udevice *dev); 283 int (*eqos_start_clks)(struct udevice *dev); 284 int (*eqos_calibrate_pads)(struct udevice *dev); 285 int (*eqos_disable_calibration)(struct udevice *dev); 286 int (*eqos_set_tx_clk_speed)(struct udevice *dev); 287 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev); 288 }; 289 290 struct eqos_priv { 291 struct udevice *dev; 292 const struct eqos_config *config; 293 fdt_addr_t regs; 294 struct eqos_mac_regs *mac_regs; 295 struct eqos_mtl_regs *mtl_regs; 296 struct eqos_dma_regs *dma_regs; 297 struct eqos_tegra186_regs *tegra186_regs; 298 struct reset_ctl reset_ctl; 299 struct gpio_desc phy_reset_gpio; 300 struct clk clk_master_bus; 301 struct clk clk_rx; 302 struct clk clk_ptp_ref; 303 struct clk clk_tx; 304 struct clk clk_ck; 305 struct clk clk_slave_bus; 306 struct mii_dev *mii; 307 struct phy_device *phy; 308 int phyaddr; 309 u32 max_speed; 310 void *descs; 311 struct eqos_desc *tx_descs; 312 struct eqos_desc *rx_descs; 313 int tx_desc_idx, rx_desc_idx; 314 void *tx_dma_buf; 315 void *rx_dma_buf; 316 void *rx_pkt; 317 bool started; 318 bool reg_access_ok; 319 }; 320 321 /* 322 * TX and RX descriptors are 16 bytes. This causes problems with the cache 323 * maintenance on CPUs where the cache-line size exceeds the size of these 324 * descriptors. What will happen is that when the driver receives a packet 325 * it will be immediately requeued for the hardware to reuse. The CPU will 326 * therefore need to flush the cache-line containing the descriptor, which 327 * will cause all other descriptors in the same cache-line to be flushed 328 * along with it. If one of those descriptors had been written to by the 329 * device those changes (and the associated packet) will be lost. 330 * 331 * To work around this, we make use of non-cached memory if available. If 332 * descriptors are mapped uncached there's no need to manually flush them 333 * or invalidate them. 334 * 335 * Note that this only applies to descriptors. The packet data buffers do 336 * not have the same constraints since they are 1536 bytes large, so they 337 * are unlikely to share cache-lines. 338 */ 339 static void *eqos_alloc_descs(unsigned int num) 340 { 341 #ifdef CONFIG_SYS_NONCACHED_MEMORY 342 return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE, 343 EQOS_DESCRIPTOR_ALIGN); 344 #else 345 return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE); 346 #endif 347 } 348 349 static void eqos_free_descs(void *descs) 350 { 351 #ifdef CONFIG_SYS_NONCACHED_MEMORY 352 /* FIXME: noncached_alloc() has no opposite */ 353 #else 354 free(descs); 355 #endif 356 } 357 358 static void eqos_inval_desc_tegra186(void *desc) 359 { 360 #ifndef CONFIG_SYS_NONCACHED_MEMORY 361 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 362 unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE, 363 ARCH_DMA_MINALIGN); 364 365 invalidate_dcache_range(start, end); 366 #endif 367 } 368 369 static void eqos_inval_desc_stm32(void *desc) 370 { 371 #ifndef CONFIG_SYS_NONCACHED_MEMORY 372 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); 373 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, 374 ARCH_DMA_MINALIGN); 375 376 invalidate_dcache_range(start, end); 377 #endif 378 } 379 380 static void eqos_flush_desc_tegra186(void *desc) 381 { 382 #ifndef CONFIG_SYS_NONCACHED_MEMORY 383 flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE); 384 #endif 385 } 386 387 static void eqos_flush_desc_stm32(void *desc) 388 { 389 #ifndef CONFIG_SYS_NONCACHED_MEMORY 390 unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN); 391 unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE, 392 ARCH_DMA_MINALIGN); 393 394 flush_dcache_range(start, end); 395 #endif 396 } 397 398 static void eqos_inval_buffer_tegra186(void *buf, size_t size) 399 { 400 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 401 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 402 403 invalidate_dcache_range(start, end); 404 } 405 406 static void eqos_inval_buffer_stm32(void *buf, size_t size) 407 { 408 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); 409 unsigned long end = roundup((unsigned long)buf + size, 410 ARCH_DMA_MINALIGN); 411 412 invalidate_dcache_range(start, end); 413 } 414 415 static void eqos_flush_buffer_tegra186(void *buf, size_t size) 416 { 417 flush_cache((unsigned long)buf, size); 418 } 419 420 static void eqos_flush_buffer_stm32(void *buf, size_t size) 421 { 422 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); 423 unsigned long end = roundup((unsigned long)buf + size, 424 ARCH_DMA_MINALIGN); 425 426 flush_dcache_range(start, end); 427 } 428 429 static int eqos_mdio_wait_idle(struct eqos_priv *eqos) 430 { 431 return wait_for_bit_le32(&eqos->mac_regs->mdio_address, 432 EQOS_MAC_MDIO_ADDRESS_GB, false, 433 1000000, true); 434 } 435 436 static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, 437 int mdio_reg) 438 { 439 struct eqos_priv *eqos = bus->priv; 440 u32 val; 441 int ret; 442 443 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr, 444 mdio_reg); 445 446 ret = eqos_mdio_wait_idle(eqos); 447 if (ret) { 448 pr_err("MDIO not idle at entry"); 449 return ret; 450 } 451 452 val = readl(&eqos->mac_regs->mdio_address); 453 val &= EQOS_MAC_MDIO_ADDRESS_SKAP | 454 EQOS_MAC_MDIO_ADDRESS_C45E; 455 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | 456 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | 457 (eqos->config->config_mac_mdio << 458 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | 459 (EQOS_MAC_MDIO_ADDRESS_GOC_READ << 460 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | 461 EQOS_MAC_MDIO_ADDRESS_GB; 462 writel(val, &eqos->mac_regs->mdio_address); 463 464 udelay(eqos->config->mdio_wait); 465 466 ret = eqos_mdio_wait_idle(eqos); 467 if (ret) { 468 pr_err("MDIO read didn't complete"); 469 return ret; 470 } 471 472 val = readl(&eqos->mac_regs->mdio_data); 473 val &= EQOS_MAC_MDIO_DATA_GD_MASK; 474 475 debug("%s: val=%x\n", __func__, val); 476 477 return val; 478 } 479 480 static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, 481 int mdio_reg, u16 mdio_val) 482 { 483 struct eqos_priv *eqos = bus->priv; 484 u32 val; 485 int ret; 486 487 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, 488 mdio_addr, mdio_reg, mdio_val); 489 490 ret = eqos_mdio_wait_idle(eqos); 491 if (ret) { 492 pr_err("MDIO not idle at entry"); 493 return ret; 494 } 495 496 writel(mdio_val, &eqos->mac_regs->mdio_data); 497 498 val = readl(&eqos->mac_regs->mdio_address); 499 val &= EQOS_MAC_MDIO_ADDRESS_SKAP | 500 EQOS_MAC_MDIO_ADDRESS_C45E; 501 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) | 502 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) | 503 (eqos->config->config_mac_mdio << 504 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) | 505 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE << 506 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) | 507 EQOS_MAC_MDIO_ADDRESS_GB; 508 writel(val, &eqos->mac_regs->mdio_address); 509 510 udelay(eqos->config->mdio_wait); 511 512 ret = eqos_mdio_wait_idle(eqos); 513 if (ret) { 514 pr_err("MDIO read didn't complete"); 515 return ret; 516 } 517 518 return 0; 519 } 520 521 static int eqos_start_clks_tegra186(struct udevice *dev) 522 { 523 struct eqos_priv *eqos = dev_get_priv(dev); 524 int ret; 525 526 debug("%s(dev=%p):\n", __func__, dev); 527 528 ret = clk_enable(&eqos->clk_slave_bus); 529 if (ret < 0) { 530 pr_err("clk_enable(clk_slave_bus) failed: %d", ret); 531 goto err; 532 } 533 534 ret = clk_enable(&eqos->clk_master_bus); 535 if (ret < 0) { 536 pr_err("clk_enable(clk_master_bus) failed: %d", ret); 537 goto err_disable_clk_slave_bus; 538 } 539 540 ret = clk_enable(&eqos->clk_rx); 541 if (ret < 0) { 542 pr_err("clk_enable(clk_rx) failed: %d", ret); 543 goto err_disable_clk_master_bus; 544 } 545 546 ret = clk_enable(&eqos->clk_ptp_ref); 547 if (ret < 0) { 548 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret); 549 goto err_disable_clk_rx; 550 } 551 552 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); 553 if (ret < 0) { 554 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret); 555 goto err_disable_clk_ptp_ref; 556 } 557 558 ret = clk_enable(&eqos->clk_tx); 559 if (ret < 0) { 560 pr_err("clk_enable(clk_tx) failed: %d", ret); 561 goto err_disable_clk_ptp_ref; 562 } 563 564 debug("%s: OK\n", __func__); 565 return 0; 566 567 err_disable_clk_ptp_ref: 568 clk_disable(&eqos->clk_ptp_ref); 569 err_disable_clk_rx: 570 clk_disable(&eqos->clk_rx); 571 err_disable_clk_master_bus: 572 clk_disable(&eqos->clk_master_bus); 573 err_disable_clk_slave_bus: 574 clk_disable(&eqos->clk_slave_bus); 575 err: 576 debug("%s: FAILED: %d\n", __func__, ret); 577 return ret; 578 } 579 580 static int eqos_start_clks_stm32(struct udevice *dev) 581 { 582 struct eqos_priv *eqos = dev_get_priv(dev); 583 int ret; 584 585 debug("%s(dev=%p):\n", __func__, dev); 586 587 ret = clk_enable(&eqos->clk_master_bus); 588 if (ret < 0) { 589 pr_err("clk_enable(clk_master_bus) failed: %d", ret); 590 goto err; 591 } 592 593 ret = clk_enable(&eqos->clk_rx); 594 if (ret < 0) { 595 pr_err("clk_enable(clk_rx) failed: %d", ret); 596 goto err_disable_clk_master_bus; 597 } 598 599 ret = clk_enable(&eqos->clk_tx); 600 if (ret < 0) { 601 pr_err("clk_enable(clk_tx) failed: %d", ret); 602 goto err_disable_clk_rx; 603 } 604 605 if (clk_valid(&eqos->clk_ck)) { 606 ret = clk_enable(&eqos->clk_ck); 607 if (ret < 0) { 608 pr_err("clk_enable(clk_ck) failed: %d", ret); 609 goto err_disable_clk_tx; 610 } 611 } 612 613 debug("%s: OK\n", __func__); 614 return 0; 615 616 err_disable_clk_tx: 617 clk_disable(&eqos->clk_tx); 618 err_disable_clk_rx: 619 clk_disable(&eqos->clk_rx); 620 err_disable_clk_master_bus: 621 clk_disable(&eqos->clk_master_bus); 622 err: 623 debug("%s: FAILED: %d\n", __func__, ret); 624 return ret; 625 } 626 627 static void eqos_stop_clks_tegra186(struct udevice *dev) 628 { 629 struct eqos_priv *eqos = dev_get_priv(dev); 630 631 debug("%s(dev=%p):\n", __func__, dev); 632 633 clk_disable(&eqos->clk_tx); 634 clk_disable(&eqos->clk_ptp_ref); 635 clk_disable(&eqos->clk_rx); 636 clk_disable(&eqos->clk_master_bus); 637 clk_disable(&eqos->clk_slave_bus); 638 639 debug("%s: OK\n", __func__); 640 } 641 642 static void eqos_stop_clks_stm32(struct udevice *dev) 643 { 644 struct eqos_priv *eqos = dev_get_priv(dev); 645 646 debug("%s(dev=%p):\n", __func__, dev); 647 648 clk_disable(&eqos->clk_tx); 649 clk_disable(&eqos->clk_rx); 650 clk_disable(&eqos->clk_master_bus); 651 if (clk_valid(&eqos->clk_ck)) 652 clk_disable(&eqos->clk_ck); 653 654 debug("%s: OK\n", __func__); 655 } 656 657 static int eqos_start_resets_tegra186(struct udevice *dev) 658 { 659 struct eqos_priv *eqos = dev_get_priv(dev); 660 int ret; 661 662 debug("%s(dev=%p):\n", __func__, dev); 663 664 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 665 if (ret < 0) { 666 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); 667 return ret; 668 } 669 670 udelay(2); 671 672 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 673 if (ret < 0) { 674 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); 675 return ret; 676 } 677 678 ret = reset_assert(&eqos->reset_ctl); 679 if (ret < 0) { 680 pr_err("reset_assert() failed: %d", ret); 681 return ret; 682 } 683 684 udelay(2); 685 686 ret = reset_deassert(&eqos->reset_ctl); 687 if (ret < 0) { 688 pr_err("reset_deassert() failed: %d", ret); 689 return ret; 690 } 691 692 debug("%s: OK\n", __func__); 693 return 0; 694 } 695 696 static int eqos_start_resets_stm32(struct udevice *dev) 697 { 698 struct eqos_priv *eqos = dev_get_priv(dev); 699 int ret; 700 701 debug("%s(dev=%p):\n", __func__, dev); 702 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 703 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 704 if (ret < 0) { 705 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", 706 ret); 707 return ret; 708 } 709 710 udelay(2); 711 712 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); 713 if (ret < 0) { 714 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", 715 ret); 716 return ret; 717 } 718 } 719 debug("%s: OK\n", __func__); 720 721 return 0; 722 } 723 724 static int eqos_stop_resets_tegra186(struct udevice *dev) 725 { 726 struct eqos_priv *eqos = dev_get_priv(dev); 727 728 reset_assert(&eqos->reset_ctl); 729 dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 730 731 return 0; 732 } 733 734 static int eqos_stop_resets_stm32(struct udevice *dev) 735 { 736 struct eqos_priv *eqos = dev_get_priv(dev); 737 int ret; 738 739 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { 740 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); 741 if (ret < 0) { 742 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", 743 ret); 744 return ret; 745 } 746 } 747 748 return 0; 749 } 750 751 static int eqos_calibrate_pads_tegra186(struct udevice *dev) 752 { 753 struct eqos_priv *eqos = dev_get_priv(dev); 754 int ret; 755 756 debug("%s(dev=%p):\n", __func__, dev); 757 758 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, 759 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); 760 761 udelay(1); 762 763 setbits_le32(&eqos->tegra186_regs->auto_cal_config, 764 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE); 765 766 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, 767 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false); 768 if (ret) { 769 pr_err("calibrate didn't start"); 770 goto failed; 771 } 772 773 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, 774 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false); 775 if (ret) { 776 pr_err("calibrate didn't finish"); 777 goto failed; 778 } 779 780 ret = 0; 781 782 failed: 783 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, 784 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); 785 786 debug("%s: returns %d\n", __func__, ret); 787 788 return ret; 789 } 790 791 static int eqos_disable_calibration_tegra186(struct udevice *dev) 792 { 793 struct eqos_priv *eqos = dev_get_priv(dev); 794 795 debug("%s(dev=%p):\n", __func__, dev); 796 797 clrbits_le32(&eqos->tegra186_regs->auto_cal_config, 798 EQOS_AUTO_CAL_CONFIG_ENABLE); 799 800 return 0; 801 } 802 803 static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) 804 { 805 struct eqos_priv *eqos = dev_get_priv(dev); 806 807 return clk_get_rate(&eqos->clk_slave_bus); 808 } 809 810 static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev) 811 { 812 struct eqos_priv *eqos = dev_get_priv(dev); 813 814 return clk_get_rate(&eqos->clk_master_bus); 815 } 816 817 static int eqos_calibrate_pads_stm32(struct udevice *dev) 818 { 819 return 0; 820 } 821 822 static int eqos_disable_calibration_stm32(struct udevice *dev) 823 { 824 return 0; 825 } 826 827 static int eqos_set_full_duplex(struct udevice *dev) 828 { 829 struct eqos_priv *eqos = dev_get_priv(dev); 830 831 debug("%s(dev=%p):\n", __func__, dev); 832 833 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); 834 835 return 0; 836 } 837 838 static int eqos_set_half_duplex(struct udevice *dev) 839 { 840 struct eqos_priv *eqos = dev_get_priv(dev); 841 842 debug("%s(dev=%p):\n", __func__, dev); 843 844 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); 845 846 /* WAR: Flush TX queue when switching to half-duplex */ 847 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, 848 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ); 849 850 return 0; 851 } 852 853 static int eqos_set_gmii_speed(struct udevice *dev) 854 { 855 struct eqos_priv *eqos = dev_get_priv(dev); 856 857 debug("%s(dev=%p):\n", __func__, dev); 858 859 clrbits_le32(&eqos->mac_regs->configuration, 860 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); 861 862 return 0; 863 } 864 865 static int eqos_set_mii_speed_100(struct udevice *dev) 866 { 867 struct eqos_priv *eqos = dev_get_priv(dev); 868 869 debug("%s(dev=%p):\n", __func__, dev); 870 871 setbits_le32(&eqos->mac_regs->configuration, 872 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); 873 874 return 0; 875 } 876 877 static int eqos_set_mii_speed_10(struct udevice *dev) 878 { 879 struct eqos_priv *eqos = dev_get_priv(dev); 880 881 debug("%s(dev=%p):\n", __func__, dev); 882 883 clrsetbits_le32(&eqos->mac_regs->configuration, 884 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS); 885 886 return 0; 887 } 888 889 static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev) 890 { 891 struct eqos_priv *eqos = dev_get_priv(dev); 892 ulong rate; 893 int ret; 894 895 debug("%s(dev=%p):\n", __func__, dev); 896 897 switch (eqos->phy->speed) { 898 case SPEED_1000: 899 rate = 125 * 1000 * 1000; 900 break; 901 case SPEED_100: 902 rate = 25 * 1000 * 1000; 903 break; 904 case SPEED_10: 905 rate = 2.5 * 1000 * 1000; 906 break; 907 default: 908 pr_err("invalid speed %d", eqos->phy->speed); 909 return -EINVAL; 910 } 911 912 ret = clk_set_rate(&eqos->clk_tx, rate); 913 if (ret < 0) { 914 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); 915 return ret; 916 } 917 918 return 0; 919 } 920 921 static int eqos_set_tx_clk_speed_stm32(struct udevice *dev) 922 { 923 return 0; 924 } 925 926 static int eqos_adjust_link(struct udevice *dev) 927 { 928 struct eqos_priv *eqos = dev_get_priv(dev); 929 int ret; 930 bool en_calibration; 931 932 debug("%s(dev=%p):\n", __func__, dev); 933 934 if (eqos->phy->duplex) 935 ret = eqos_set_full_duplex(dev); 936 else 937 ret = eqos_set_half_duplex(dev); 938 if (ret < 0) { 939 pr_err("eqos_set_*_duplex() failed: %d", ret); 940 return ret; 941 } 942 943 switch (eqos->phy->speed) { 944 case SPEED_1000: 945 en_calibration = true; 946 ret = eqos_set_gmii_speed(dev); 947 break; 948 case SPEED_100: 949 en_calibration = true; 950 ret = eqos_set_mii_speed_100(dev); 951 break; 952 case SPEED_10: 953 en_calibration = false; 954 ret = eqos_set_mii_speed_10(dev); 955 break; 956 default: 957 pr_err("invalid speed %d", eqos->phy->speed); 958 return -EINVAL; 959 } 960 if (ret < 0) { 961 pr_err("eqos_set_*mii_speed*() failed: %d", ret); 962 return ret; 963 } 964 965 if (en_calibration) { 966 ret = eqos->config->ops->eqos_calibrate_pads(dev); 967 if (ret < 0) { 968 pr_err("eqos_calibrate_pads() failed: %d", 969 ret); 970 return ret; 971 } 972 } else { 973 ret = eqos->config->ops->eqos_disable_calibration(dev); 974 if (ret < 0) { 975 pr_err("eqos_disable_calibration() failed: %d", 976 ret); 977 return ret; 978 } 979 } 980 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev); 981 if (ret < 0) { 982 pr_err("eqos_set_tx_clk_speed() failed: %d", ret); 983 return ret; 984 } 985 986 return 0; 987 } 988 989 static int eqos_write_hwaddr(struct udevice *dev) 990 { 991 struct eth_pdata *plat = dev_get_platdata(dev); 992 struct eqos_priv *eqos = dev_get_priv(dev); 993 uint32_t val; 994 995 /* 996 * This function may be called before start() or after stop(). At that 997 * time, on at least some configurations of the EQoS HW, all clocks to 998 * the EQoS HW block will be stopped, and a reset signal applied. If 999 * any register access is attempted in this state, bus timeouts or CPU 1000 * hangs may occur. This check prevents that. 1001 * 1002 * A simple solution to this problem would be to not implement 1003 * write_hwaddr(), since start() always writes the MAC address into HW 1004 * anyway. However, it is desirable to implement write_hwaddr() to 1005 * support the case of SW that runs subsequent to U-Boot which expects 1006 * the MAC address to already be programmed into the EQoS registers, 1007 * which must happen irrespective of whether the U-Boot user (or 1008 * scripts) actually made use of the EQoS device, and hence 1009 * irrespective of whether start() was ever called. 1010 * 1011 * Note that this requirement by subsequent SW is not valid for 1012 * Tegra186, and is likely not valid for any non-PCI instantiation of 1013 * the EQoS HW block. This function is implemented solely as 1014 * future-proofing with the expectation the driver will eventually be 1015 * ported to some system where the expectation above is true. 1016 */ 1017 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok) 1018 return 0; 1019 1020 /* Update the MAC address */ 1021 val = (plat->enetaddr[5] << 8) | 1022 (plat->enetaddr[4]); 1023 writel(val, &eqos->mac_regs->address0_high); 1024 val = (plat->enetaddr[3] << 24) | 1025 (plat->enetaddr[2] << 16) | 1026 (plat->enetaddr[1] << 8) | 1027 (plat->enetaddr[0]); 1028 writel(val, &eqos->mac_regs->address0_low); 1029 1030 return 0; 1031 } 1032 1033 static int eqos_start(struct udevice *dev) 1034 { 1035 struct eqos_priv *eqos = dev_get_priv(dev); 1036 int ret, i; 1037 ulong rate; 1038 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; 1039 ulong last_rx_desc; 1040 1041 debug("%s(dev=%p):\n", __func__, dev); 1042 1043 eqos->tx_desc_idx = 0; 1044 eqos->rx_desc_idx = 0; 1045 1046 ret = eqos->config->ops->eqos_start_clks(dev); 1047 if (ret < 0) { 1048 pr_err("eqos_start_clks() failed: %d", ret); 1049 goto err; 1050 } 1051 1052 ret = eqos->config->ops->eqos_start_resets(dev); 1053 if (ret < 0) { 1054 pr_err("eqos_start_resets() failed: %d", ret); 1055 goto err_stop_clks; 1056 } 1057 1058 udelay(10); 1059 1060 eqos->reg_access_ok = true; 1061 1062 ret = wait_for_bit_le32(&eqos->dma_regs->mode, 1063 EQOS_DMA_MODE_SWR, false, 1064 eqos->config->swr_wait, false); 1065 if (ret) { 1066 pr_err("EQOS_DMA_MODE_SWR stuck"); 1067 goto err_stop_resets; 1068 } 1069 1070 ret = eqos->config->ops->eqos_calibrate_pads(dev); 1071 if (ret < 0) { 1072 pr_err("eqos_calibrate_pads() failed: %d", ret); 1073 goto err_stop_resets; 1074 } 1075 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); 1076 1077 val = (rate / 1000000) - 1; 1078 writel(val, &eqos->mac_regs->us_tic_counter); 1079 1080 /* 1081 * if PHY was already connected and configured, 1082 * don't need to reconnect/reconfigure again 1083 */ 1084 if (!eqos->phy) { 1085 eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev, 1086 eqos->config->interface(dev)); 1087 if (!eqos->phy) { 1088 pr_err("phy_connect() failed"); 1089 goto err_stop_resets; 1090 } 1091 1092 if (eqos->max_speed) { 1093 ret = phy_set_supported(eqos->phy, eqos->max_speed); 1094 if (ret) { 1095 pr_err("phy_set_supported() failed: %d", ret); 1096 goto err_shutdown_phy; 1097 } 1098 } 1099 1100 ret = phy_config(eqos->phy); 1101 if (ret < 0) { 1102 pr_err("phy_config() failed: %d", ret); 1103 goto err_shutdown_phy; 1104 } 1105 } 1106 1107 ret = phy_startup(eqos->phy); 1108 if (ret < 0) { 1109 pr_err("phy_startup() failed: %d", ret); 1110 goto err_shutdown_phy; 1111 } 1112 1113 if (!eqos->phy->link) { 1114 pr_err("No link"); 1115 goto err_shutdown_phy; 1116 } 1117 1118 ret = eqos_adjust_link(dev); 1119 if (ret < 0) { 1120 pr_err("eqos_adjust_link() failed: %d", ret); 1121 goto err_shutdown_phy; 1122 } 1123 1124 /* Configure MTL */ 1125 1126 /* Enable Store and Forward mode for TX */ 1127 /* Program Tx operating mode */ 1128 setbits_le32(&eqos->mtl_regs->txq0_operation_mode, 1129 EQOS_MTL_TXQ0_OPERATION_MODE_TSF | 1130 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << 1131 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); 1132 1133 /* Transmit Queue weight */ 1134 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight); 1135 1136 /* Enable Store and Forward mode for RX, since no jumbo frame */ 1137 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1138 EQOS_MTL_RXQ0_OPERATION_MODE_RSF); 1139 1140 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ 1141 val = readl(&eqos->mac_regs->hw_feature1); 1142 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & 1143 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; 1144 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & 1145 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; 1146 1147 /* 1148 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. 1149 * r/tqs is encoded as (n / 256) - 1. 1150 */ 1151 tqs = (128 << tx_fifo_sz) / 256 - 1; 1152 rqs = (128 << rx_fifo_sz) / 256 - 1; 1153 1154 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, 1155 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << 1156 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, 1157 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); 1158 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1159 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK << 1160 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, 1161 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); 1162 1163 /* Flow control used only if each channel gets 4KB or more FIFO */ 1164 if (rqs >= ((4096 / 256) - 1)) { 1165 u32 rfd, rfa; 1166 1167 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1168 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC); 1169 1170 /* 1171 * Set Threshold for Activating Flow Contol space for min 2 1172 * frames ie, (1500 * 1) = 1500 bytes. 1173 * 1174 * Set Threshold for Deactivating Flow Contol for space of 1175 * min 1 frame (frame size 1500bytes) in receive fifo 1176 */ 1177 if (rqs == ((4096 / 256) - 1)) { 1178 /* 1179 * This violates the above formula because of FIFO size 1180 * limit therefore overflow may occur inspite of this. 1181 */ 1182 rfd = 0x3; /* Full-3K */ 1183 rfa = 0x1; /* Full-1.5K */ 1184 } else if (rqs == ((8192 / 256) - 1)) { 1185 rfd = 0x6; /* Full-4K */ 1186 rfa = 0xa; /* Full-6K */ 1187 } else if (rqs == ((16384 / 256) - 1)) { 1188 rfd = 0x6; /* Full-4K */ 1189 rfa = 0x12; /* Full-10K */ 1190 } else { 1191 rfd = 0x6; /* Full-4K */ 1192 rfa = 0x1E; /* Full-16K */ 1193 } 1194 1195 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, 1196 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK << 1197 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | 1198 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK << 1199 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT), 1200 (rfd << 1201 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | 1202 (rfa << 1203 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)); 1204 } 1205 1206 /* Configure MAC */ 1207 1208 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, 1209 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << 1210 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, 1211 eqos->config->config_mac << 1212 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); 1213 1214 /* Set TX flow control parameters */ 1215 /* Set Pause Time */ 1216 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, 1217 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); 1218 /* Assign priority for TX flow control */ 1219 clrbits_le32(&eqos->mac_regs->txq_prty_map0, 1220 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK << 1221 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT); 1222 /* Assign priority for RX flow control */ 1223 clrbits_le32(&eqos->mac_regs->rxq_ctrl2, 1224 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK << 1225 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT); 1226 /* Enable flow control */ 1227 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, 1228 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE); 1229 setbits_le32(&eqos->mac_regs->rx_flow_ctrl, 1230 EQOS_MAC_RX_FLOW_CTRL_RFE); 1231 1232 clrsetbits_le32(&eqos->mac_regs->configuration, 1233 EQOS_MAC_CONFIGURATION_GPSLCE | 1234 EQOS_MAC_CONFIGURATION_WD | 1235 EQOS_MAC_CONFIGURATION_JD | 1236 EQOS_MAC_CONFIGURATION_JE, 1237 EQOS_MAC_CONFIGURATION_CST | 1238 EQOS_MAC_CONFIGURATION_ACS); 1239 1240 eqos_write_hwaddr(dev); 1241 1242 /* Configure DMA */ 1243 1244 /* Enable OSP mode */ 1245 setbits_le32(&eqos->dma_regs->ch0_tx_control, 1246 EQOS_DMA_CH0_TX_CONTROL_OSP); 1247 1248 /* RX buffer size. Must be a multiple of bus width */ 1249 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, 1250 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK << 1251 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, 1252 EQOS_MAX_PACKET_SIZE << 1253 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); 1254 1255 setbits_le32(&eqos->dma_regs->ch0_control, 1256 EQOS_DMA_CH0_CONTROL_PBLX8); 1257 1258 /* 1259 * Burst length must be < 1/2 FIFO size. 1260 * FIFO size in tqs is encoded as (n / 256) - 1. 1261 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. 1262 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. 1263 */ 1264 pbl = tqs + 1; 1265 if (pbl > 32) 1266 pbl = 32; 1267 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control, 1268 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK << 1269 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, 1270 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); 1271 1272 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, 1273 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK << 1274 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, 1275 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); 1276 1277 /* DMA performance configuration */ 1278 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | 1279 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 | 1280 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4; 1281 writel(val, &eqos->dma_regs->sysbus_mode); 1282 1283 /* Set up descriptors */ 1284 1285 memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE); 1286 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { 1287 struct eqos_desc *rx_desc = &(eqos->rx_descs[i]); 1288 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf + 1289 (i * EQOS_MAX_PACKET_SIZE)); 1290 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; 1291 eqos->config->ops->eqos_flush_desc(rx_desc); 1292 } 1293 1294 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress); 1295 writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address); 1296 writel(EQOS_DESCRIPTORS_TX - 1, 1297 &eqos->dma_regs->ch0_txdesc_ring_length); 1298 1299 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress); 1300 writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address); 1301 writel(EQOS_DESCRIPTORS_RX - 1, 1302 &eqos->dma_regs->ch0_rxdesc_ring_length); 1303 1304 /* Enable everything */ 1305 1306 setbits_le32(&eqos->mac_regs->configuration, 1307 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); 1308 1309 setbits_le32(&eqos->dma_regs->ch0_tx_control, 1310 EQOS_DMA_CH0_TX_CONTROL_ST); 1311 setbits_le32(&eqos->dma_regs->ch0_rx_control, 1312 EQOS_DMA_CH0_RX_CONTROL_SR); 1313 1314 /* TX tail pointer not written until we need to TX a packet */ 1315 /* 1316 * Point RX tail pointer at last descriptor. Ideally, we'd point at the 1317 * first descriptor, implying all descriptors were available. However, 1318 * that's not distinguishable from none of the descriptors being 1319 * available. 1320 */ 1321 last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]); 1322 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); 1323 1324 eqos->started = true; 1325 1326 debug("%s: OK\n", __func__); 1327 return 0; 1328 1329 err_shutdown_phy: 1330 phy_shutdown(eqos->phy); 1331 err_stop_resets: 1332 eqos->config->ops->eqos_stop_resets(dev); 1333 err_stop_clks: 1334 eqos->config->ops->eqos_stop_clks(dev); 1335 err: 1336 pr_err("FAILED: %d", ret); 1337 return ret; 1338 } 1339 1340 static void eqos_stop(struct udevice *dev) 1341 { 1342 struct eqos_priv *eqos = dev_get_priv(dev); 1343 int i; 1344 1345 debug("%s(dev=%p):\n", __func__, dev); 1346 1347 if (!eqos->started) 1348 return; 1349 eqos->started = false; 1350 eqos->reg_access_ok = false; 1351 1352 /* Disable TX DMA */ 1353 clrbits_le32(&eqos->dma_regs->ch0_tx_control, 1354 EQOS_DMA_CH0_TX_CONTROL_ST); 1355 1356 /* Wait for TX all packets to drain out of MTL */ 1357 for (i = 0; i < 1000000; i++) { 1358 u32 val = readl(&eqos->mtl_regs->txq0_debug); 1359 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & 1360 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK; 1361 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS; 1362 if ((trcsts != 1) && (!txqsts)) 1363 break; 1364 } 1365 1366 /* Turn off MAC TX and RX */ 1367 clrbits_le32(&eqos->mac_regs->configuration, 1368 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); 1369 1370 /* Wait for all RX packets to drain out of MTL */ 1371 for (i = 0; i < 1000000; i++) { 1372 u32 val = readl(&eqos->mtl_regs->rxq0_debug); 1373 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & 1374 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK; 1375 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & 1376 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK; 1377 if ((!prxq) && (!rxqsts)) 1378 break; 1379 } 1380 1381 /* Turn off RX DMA */ 1382 clrbits_le32(&eqos->dma_regs->ch0_rx_control, 1383 EQOS_DMA_CH0_RX_CONTROL_SR); 1384 1385 if (eqos->phy) { 1386 phy_shutdown(eqos->phy); 1387 } 1388 eqos->config->ops->eqos_stop_resets(dev); 1389 eqos->config->ops->eqos_stop_clks(dev); 1390 1391 debug("%s: OK\n", __func__); 1392 } 1393 1394 static int eqos_send(struct udevice *dev, void *packet, int length) 1395 { 1396 struct eqos_priv *eqos = dev_get_priv(dev); 1397 struct eqos_desc *tx_desc; 1398 int i; 1399 1400 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, 1401 length); 1402 1403 memcpy(eqos->tx_dma_buf, packet, length); 1404 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length); 1405 1406 tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]); 1407 eqos->tx_desc_idx++; 1408 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; 1409 1410 tx_desc->des0 = (ulong)eqos->tx_dma_buf; 1411 tx_desc->des1 = 0; 1412 tx_desc->des2 = length; 1413 /* 1414 * Make sure that if HW sees the _OWN write below, it will see all the 1415 * writes to the rest of the descriptor too. 1416 */ 1417 mb(); 1418 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; 1419 eqos->config->ops->eqos_flush_desc(tx_desc); 1420 1421 writel((ulong)(&(eqos->tx_descs[eqos->tx_desc_idx])), 1422 &eqos->dma_regs->ch0_txdesc_tail_pointer); 1423 1424 for (i = 0; i < 1000000; i++) { 1425 eqos->config->ops->eqos_inval_desc(tx_desc); 1426 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) 1427 return 0; 1428 udelay(1); 1429 } 1430 1431 debug("%s: TX timeout\n", __func__); 1432 1433 return -ETIMEDOUT; 1434 } 1435 1436 static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) 1437 { 1438 struct eqos_priv *eqos = dev_get_priv(dev); 1439 struct eqos_desc *rx_desc; 1440 int length; 1441 1442 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); 1443 1444 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); 1445 eqos->config->ops->eqos_inval_desc(rx_desc); 1446 if (rx_desc->des3 & EQOS_DESC3_OWN) { 1447 debug("%s: RX packet not available\n", __func__); 1448 return -EAGAIN; 1449 } 1450 1451 *packetp = eqos->rx_dma_buf + 1452 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); 1453 length = rx_desc->des3 & 0x7fff; 1454 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); 1455 1456 eqos->config->ops->eqos_inval_buffer(*packetp, length); 1457 1458 return length; 1459 } 1460 1461 static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) 1462 { 1463 struct eqos_priv *eqos = dev_get_priv(dev); 1464 uchar *packet_expected; 1465 struct eqos_desc *rx_desc; 1466 1467 debug("%s(packet=%p, length=%d)\n", __func__, packet, length); 1468 1469 packet_expected = eqos->rx_dma_buf + 1470 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); 1471 if (packet != packet_expected) { 1472 debug("%s: Unexpected packet (expected %p)\n", __func__, 1473 packet_expected); 1474 return -EINVAL; 1475 } 1476 1477 rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]); 1478 rx_desc->des0 = (u32)(ulong)packet; 1479 rx_desc->des1 = 0; 1480 rx_desc->des2 = 0; 1481 /* 1482 * Make sure that if HW sees the _OWN write below, it will see all the 1483 * writes to the rest of the descriptor too. 1484 */ 1485 mb(); 1486 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; 1487 eqos->config->ops->eqos_flush_desc(rx_desc); 1488 1489 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); 1490 1491 eqos->rx_desc_idx++; 1492 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX; 1493 1494 return 0; 1495 } 1496 1497 static int eqos_probe_resources_core(struct udevice *dev) 1498 { 1499 struct eqos_priv *eqos = dev_get_priv(dev); 1500 int ret; 1501 1502 debug("%s(dev=%p):\n", __func__, dev); 1503 1504 eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX + 1505 EQOS_DESCRIPTORS_RX); 1506 if (!eqos->descs) { 1507 debug("%s: eqos_alloc_descs() failed\n", __func__); 1508 ret = -ENOMEM; 1509 goto err; 1510 } 1511 eqos->tx_descs = (struct eqos_desc *)eqos->descs; 1512 eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX); 1513 debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs, 1514 eqos->rx_descs); 1515 1516 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); 1517 if (!eqos->tx_dma_buf) { 1518 debug("%s: memalign(tx_dma_buf) failed\n", __func__); 1519 ret = -ENOMEM; 1520 goto err_free_descs; 1521 } 1522 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf); 1523 1524 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE); 1525 if (!eqos->rx_dma_buf) { 1526 debug("%s: memalign(rx_dma_buf) failed\n", __func__); 1527 ret = -ENOMEM; 1528 goto err_free_tx_dma_buf; 1529 } 1530 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf); 1531 1532 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE); 1533 if (!eqos->rx_pkt) { 1534 debug("%s: malloc(rx_pkt) failed\n", __func__); 1535 ret = -ENOMEM; 1536 goto err_free_rx_dma_buf; 1537 } 1538 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt); 1539 1540 debug("%s: OK\n", __func__); 1541 return 0; 1542 1543 err_free_rx_dma_buf: 1544 free(eqos->rx_dma_buf); 1545 err_free_tx_dma_buf: 1546 free(eqos->tx_dma_buf); 1547 err_free_descs: 1548 eqos_free_descs(eqos->descs); 1549 err: 1550 1551 debug("%s: returns %d\n", __func__, ret); 1552 return ret; 1553 } 1554 1555 static int eqos_remove_resources_core(struct udevice *dev) 1556 { 1557 struct eqos_priv *eqos = dev_get_priv(dev); 1558 1559 debug("%s(dev=%p):\n", __func__, dev); 1560 1561 free(eqos->rx_pkt); 1562 free(eqos->rx_dma_buf); 1563 free(eqos->tx_dma_buf); 1564 eqos_free_descs(eqos->descs); 1565 1566 debug("%s: OK\n", __func__); 1567 return 0; 1568 } 1569 1570 static int eqos_probe_resources_tegra186(struct udevice *dev) 1571 { 1572 struct eqos_priv *eqos = dev_get_priv(dev); 1573 int ret; 1574 1575 debug("%s(dev=%p):\n", __func__, dev); 1576 1577 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); 1578 if (ret) { 1579 pr_err("reset_get_by_name(rst) failed: %d", ret); 1580 return ret; 1581 } 1582 1583 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, 1584 &eqos->phy_reset_gpio, 1585 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 1586 if (ret) { 1587 pr_err("gpio_request_by_name(phy reset) failed: %d", ret); 1588 goto err_free_reset_eqos; 1589 } 1590 1591 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); 1592 if (ret) { 1593 pr_err("clk_get_by_name(slave_bus) failed: %d", ret); 1594 goto err_free_gpio_phy_reset; 1595 } 1596 1597 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); 1598 if (ret) { 1599 pr_err("clk_get_by_name(master_bus) failed: %d", ret); 1600 goto err_free_clk_slave_bus; 1601 } 1602 1603 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); 1604 if (ret) { 1605 pr_err("clk_get_by_name(rx) failed: %d", ret); 1606 goto err_free_clk_master_bus; 1607 } 1608 1609 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); 1610 if (ret) { 1611 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret); 1612 goto err_free_clk_rx; 1613 return ret; 1614 } 1615 1616 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); 1617 if (ret) { 1618 pr_err("clk_get_by_name(tx) failed: %d", ret); 1619 goto err_free_clk_ptp_ref; 1620 } 1621 1622 debug("%s: OK\n", __func__); 1623 return 0; 1624 1625 err_free_clk_ptp_ref: 1626 clk_free(&eqos->clk_ptp_ref); 1627 err_free_clk_rx: 1628 clk_free(&eqos->clk_rx); 1629 err_free_clk_master_bus: 1630 clk_free(&eqos->clk_master_bus); 1631 err_free_clk_slave_bus: 1632 clk_free(&eqos->clk_slave_bus); 1633 err_free_gpio_phy_reset: 1634 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1635 err_free_reset_eqos: 1636 reset_free(&eqos->reset_ctl); 1637 1638 debug("%s: returns %d\n", __func__, ret); 1639 return ret; 1640 } 1641 1642 /* board-specific Ethernet Interface initializations. */ 1643 __weak int board_interface_eth_init(struct udevice *dev, 1644 phy_interface_t interface_type) 1645 { 1646 return 0; 1647 } 1648 1649 static int eqos_probe_resources_stm32(struct udevice *dev) 1650 { 1651 struct eqos_priv *eqos = dev_get_priv(dev); 1652 int ret; 1653 phy_interface_t interface; 1654 struct ofnode_phandle_args phandle_args; 1655 1656 debug("%s(dev=%p):\n", __func__, dev); 1657 1658 interface = eqos->config->interface(dev); 1659 1660 if (interface == PHY_INTERFACE_MODE_NONE) { 1661 pr_err("Invalid PHY interface\n"); 1662 return -EINVAL; 1663 } 1664 1665 ret = board_interface_eth_init(dev, interface); 1666 if (ret) 1667 return -EINVAL; 1668 1669 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); 1670 1671 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus); 1672 if (ret) { 1673 pr_err("clk_get_by_name(master_bus) failed: %d", ret); 1674 goto err_probe; 1675 } 1676 1677 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx); 1678 if (ret) { 1679 pr_err("clk_get_by_name(rx) failed: %d", ret); 1680 goto err_free_clk_master_bus; 1681 } 1682 1683 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx); 1684 if (ret) { 1685 pr_err("clk_get_by_name(tx) failed: %d", ret); 1686 goto err_free_clk_rx; 1687 } 1688 1689 /* Get ETH_CLK clocks (optional) */ 1690 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck); 1691 if (ret) 1692 pr_warn("No phy clock provided %d", ret); 1693 1694 eqos->phyaddr = -1; 1695 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, 1696 &phandle_args); 1697 if (!ret) { 1698 /* search "reset-gpios" in phy node */ 1699 ret = gpio_request_by_name_nodev(phandle_args.node, 1700 "reset-gpios", 0, 1701 &eqos->phy_reset_gpio, 1702 GPIOD_IS_OUT | 1703 GPIOD_IS_OUT_ACTIVE); 1704 if (ret) 1705 pr_warn("gpio_request_by_name(phy reset) not provided %d", 1706 ret); 1707 1708 eqos->phyaddr = ofnode_read_u32_default(phandle_args.node, 1709 "reg", -1); 1710 } 1711 1712 debug("%s: OK\n", __func__); 1713 return 0; 1714 1715 err_free_clk_rx: 1716 clk_free(&eqos->clk_rx); 1717 err_free_clk_master_bus: 1718 clk_free(&eqos->clk_master_bus); 1719 err_probe: 1720 1721 debug("%s: returns %d\n", __func__, ret); 1722 return ret; 1723 } 1724 1725 static phy_interface_t eqos_get_interface_stm32(struct udevice *dev) 1726 { 1727 const char *phy_mode; 1728 phy_interface_t interface = PHY_INTERFACE_MODE_NONE; 1729 1730 debug("%s(dev=%p):\n", __func__, dev); 1731 1732 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1733 NULL); 1734 if (phy_mode) 1735 interface = phy_get_interface_by_name(phy_mode); 1736 1737 return interface; 1738 } 1739 1740 static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev) 1741 { 1742 return PHY_INTERFACE_MODE_MII; 1743 } 1744 1745 static int eqos_remove_resources_tegra186(struct udevice *dev) 1746 { 1747 struct eqos_priv *eqos = dev_get_priv(dev); 1748 1749 debug("%s(dev=%p):\n", __func__, dev); 1750 1751 clk_free(&eqos->clk_tx); 1752 clk_free(&eqos->clk_ptp_ref); 1753 clk_free(&eqos->clk_rx); 1754 clk_free(&eqos->clk_slave_bus); 1755 clk_free(&eqos->clk_master_bus); 1756 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1757 reset_free(&eqos->reset_ctl); 1758 1759 debug("%s: OK\n", __func__); 1760 return 0; 1761 } 1762 1763 static int eqos_remove_resources_stm32(struct udevice *dev) 1764 { 1765 struct eqos_priv *eqos = dev_get_priv(dev); 1766 1767 debug("%s(dev=%p):\n", __func__, dev); 1768 1769 clk_free(&eqos->clk_tx); 1770 clk_free(&eqos->clk_rx); 1771 clk_free(&eqos->clk_master_bus); 1772 if (clk_valid(&eqos->clk_ck)) 1773 clk_free(&eqos->clk_ck); 1774 1775 if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) 1776 dm_gpio_free(dev, &eqos->phy_reset_gpio); 1777 1778 debug("%s: OK\n", __func__); 1779 return 0; 1780 } 1781 1782 static int eqos_probe(struct udevice *dev) 1783 { 1784 struct eqos_priv *eqos = dev_get_priv(dev); 1785 int ret; 1786 1787 debug("%s(dev=%p):\n", __func__, dev); 1788 1789 eqos->dev = dev; 1790 eqos->config = (void *)dev_get_driver_data(dev); 1791 1792 eqos->regs = devfdt_get_addr(dev); 1793 if (eqos->regs == FDT_ADDR_T_NONE) { 1794 pr_err("devfdt_get_addr() failed"); 1795 return -ENODEV; 1796 } 1797 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE); 1798 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE); 1799 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE); 1800 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); 1801 1802 ret = eqos_probe_resources_core(dev); 1803 if (ret < 0) { 1804 pr_err("eqos_probe_resources_core() failed: %d", ret); 1805 return ret; 1806 } 1807 1808 ret = eqos->config->ops->eqos_probe_resources(dev); 1809 if (ret < 0) { 1810 pr_err("eqos_probe_resources() failed: %d", ret); 1811 goto err_remove_resources_core; 1812 } 1813 1814 eqos->mii = mdio_alloc(); 1815 if (!eqos->mii) { 1816 pr_err("mdio_alloc() failed"); 1817 ret = -ENOMEM; 1818 goto err_remove_resources_tegra; 1819 } 1820 eqos->mii->read = eqos_mdio_read; 1821 eqos->mii->write = eqos_mdio_write; 1822 eqos->mii->priv = eqos; 1823 strcpy(eqos->mii->name, dev->name); 1824 1825 ret = mdio_register(eqos->mii); 1826 if (ret < 0) { 1827 pr_err("mdio_register() failed: %d", ret); 1828 goto err_free_mdio; 1829 } 1830 1831 debug("%s: OK\n", __func__); 1832 return 0; 1833 1834 err_free_mdio: 1835 mdio_free(eqos->mii); 1836 err_remove_resources_tegra: 1837 eqos->config->ops->eqos_remove_resources(dev); 1838 err_remove_resources_core: 1839 eqos_remove_resources_core(dev); 1840 1841 debug("%s: returns %d\n", __func__, ret); 1842 return ret; 1843 } 1844 1845 static int eqos_remove(struct udevice *dev) 1846 { 1847 struct eqos_priv *eqos = dev_get_priv(dev); 1848 1849 debug("%s(dev=%p):\n", __func__, dev); 1850 1851 mdio_unregister(eqos->mii); 1852 mdio_free(eqos->mii); 1853 eqos->config->ops->eqos_remove_resources(dev); 1854 1855 eqos_probe_resources_core(dev); 1856 1857 debug("%s: OK\n", __func__); 1858 return 0; 1859 } 1860 1861 static const struct eth_ops eqos_ops = { 1862 .start = eqos_start, 1863 .stop = eqos_stop, 1864 .send = eqos_send, 1865 .recv = eqos_recv, 1866 .free_pkt = eqos_free_pkt, 1867 .write_hwaddr = eqos_write_hwaddr, 1868 }; 1869 1870 static struct eqos_ops eqos_tegra186_ops = { 1871 .eqos_inval_desc = eqos_inval_desc_tegra186, 1872 .eqos_flush_desc = eqos_flush_desc_tegra186, 1873 .eqos_inval_buffer = eqos_inval_buffer_tegra186, 1874 .eqos_flush_buffer = eqos_flush_buffer_tegra186, 1875 .eqos_probe_resources = eqos_probe_resources_tegra186, 1876 .eqos_remove_resources = eqos_remove_resources_tegra186, 1877 .eqos_stop_resets = eqos_stop_resets_tegra186, 1878 .eqos_start_resets = eqos_start_resets_tegra186, 1879 .eqos_stop_clks = eqos_stop_clks_tegra186, 1880 .eqos_start_clks = eqos_start_clks_tegra186, 1881 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186, 1882 .eqos_disable_calibration = eqos_disable_calibration_tegra186, 1883 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186, 1884 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186 1885 }; 1886 1887 static const struct eqos_config eqos_tegra186_config = { 1888 .reg_access_always_ok = false, 1889 .mdio_wait = 10, 1890 .swr_wait = 10, 1891 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, 1892 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35, 1893 .interface = eqos_get_interface_tegra186, 1894 .ops = &eqos_tegra186_ops 1895 }; 1896 1897 static struct eqos_ops eqos_stm32_ops = { 1898 .eqos_inval_desc = eqos_inval_desc_stm32, 1899 .eqos_flush_desc = eqos_flush_desc_stm32, 1900 .eqos_inval_buffer = eqos_inval_buffer_stm32, 1901 .eqos_flush_buffer = eqos_flush_buffer_stm32, 1902 .eqos_probe_resources = eqos_probe_resources_stm32, 1903 .eqos_remove_resources = eqos_remove_resources_stm32, 1904 .eqos_stop_resets = eqos_stop_resets_stm32, 1905 .eqos_start_resets = eqos_start_resets_stm32, 1906 .eqos_stop_clks = eqos_stop_clks_stm32, 1907 .eqos_start_clks = eqos_start_clks_stm32, 1908 .eqos_calibrate_pads = eqos_calibrate_pads_stm32, 1909 .eqos_disable_calibration = eqos_disable_calibration_stm32, 1910 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32, 1911 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32 1912 }; 1913 1914 static const struct eqos_config eqos_stm32_config = { 1915 .reg_access_always_ok = false, 1916 .mdio_wait = 10000, 1917 .swr_wait = 50, 1918 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV, 1919 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, 1920 .interface = eqos_get_interface_stm32, 1921 .ops = &eqos_stm32_ops 1922 }; 1923 1924 static const struct udevice_id eqos_ids[] = { 1925 { 1926 .compatible = "nvidia,tegra186-eqos", 1927 .data = (ulong)&eqos_tegra186_config 1928 }, 1929 { 1930 .compatible = "snps,dwmac-4.20a", 1931 .data = (ulong)&eqos_stm32_config 1932 }, 1933 1934 { } 1935 }; 1936 1937 U_BOOT_DRIVER(eth_eqos) = { 1938 .name = "eth_eqos", 1939 .id = UCLASS_ETH, 1940 .of_match = eqos_ids, 1941 .probe = eqos_probe, 1942 .remove = eqos_remove, 1943 .ops = &eqos_ops, 1944 .priv_auto_alloc_size = sizeof(struct eqos_priv), 1945 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1946 }; 1947