1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3128.h> 15 #include <asm/arch/hardware.h> 16 #include <dm/lists.h> 17 #include <dt-bindings/clock/rk3128-cru.h> 18 #include <linux/log2.h> 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 enum { 23 VCO_MAX_HZ = 2400U * 1000000, 24 VCO_MIN_HZ = 600 * 1000000, 25 OUTPUT_MAX_HZ = 2400U * 1000000, 26 OUTPUT_MIN_HZ = 24 * 1000000, 27 }; 28 29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 30 31 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 32 .refdiv = _refdiv,\ 33 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 35 36 /* use integer mode*/ 37 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 38 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 39 40 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, 41 const struct pll_div *div) 42 { 43 int pll_id = rk_pll_id(clk_id); 44 struct rk3128_pll *pll = &cru->pll[pll_id]; 45 46 /* All PLLs have same VCO and output frequency range restrictions. */ 47 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 48 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 49 50 debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n", 51 pll, div->fbdiv, div->refdiv, div->postdiv1, 52 div->postdiv2, vco_hz, output_hz); 53 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 54 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 55 56 /* use integer mode */ 57 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 58 /* Power down */ 59 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 60 61 rk_clrsetreg(&pll->con0, 62 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 63 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 64 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 65 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 66 div->refdiv << PLL_REFDIV_SHIFT)); 67 68 /* Power Up */ 69 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 70 71 /* waiting for pll lock */ 72 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 73 udelay(1); 74 75 return 0; 76 } 77 78 static void rkclk_init(struct rk3128_cru *cru) 79 { 80 u32 aclk_div; 81 u32 hclk_div; 82 u32 pclk_div; 83 84 /* pll enter slow-mode */ 85 rk_clrsetreg(&cru->cru_mode_con, 86 GPLL_MODE_MASK | APLL_MODE_MASK, 87 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 88 APLL_MODE_SLOW << APLL_MODE_SHIFT); 89 90 /* init pll */ 91 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 92 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 93 94 /* 95 * select apll as cpu/core clock pll source and 96 * set up dependent divisors for PERI and ACLK clocks. 97 * core hz : apll = 1:1 98 */ 99 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 100 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 101 102 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 103 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 104 105 rk_clrsetreg(&cru->cru_clksel_con[0], 106 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 107 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 108 0 << CORE_DIV_CON_SHIFT); 109 110 rk_clrsetreg(&cru->cru_clksel_con[1], 111 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 112 aclk_div << CORE_ACLK_DIV_SHIFT | 113 pclk_div << CORE_PERI_DIV_SHIFT); 114 115 /* 116 * select gpll as pd_bus bus clock source and 117 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 118 */ 119 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 120 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 121 122 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 123 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); 124 125 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 126 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); 127 128 rk_clrsetreg(&cru->cru_clksel_con[0], 129 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 130 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 131 aclk_div << BUS_ACLK_DIV_SHIFT); 132 133 rk_clrsetreg(&cru->cru_clksel_con[1], 134 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 135 pclk_div << BUS_PCLK_DIV_SHIFT | 136 hclk_div << BUS_HCLK_DIV_SHIFT); 137 138 /* 139 * select gpll as pd_peri bus clock source and 140 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 141 */ 142 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 143 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 144 145 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 146 assert((1 << hclk_div) * PERI_HCLK_HZ == 147 PERI_ACLK_HZ && (hclk_div < 0x4)); 148 149 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 150 assert((1 << pclk_div) * PERI_PCLK_HZ == 151 PERI_ACLK_HZ && pclk_div < 0x8); 152 153 rk_clrsetreg(&cru->cru_clksel_con[10], 154 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 155 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 156 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 157 pclk_div << PERI_PCLK_DIV_SHIFT | 158 hclk_div << PERI_HCLK_DIV_SHIFT | 159 aclk_div << PERI_ACLK_DIV_SHIFT); 160 161 /* PLL enter normal-mode */ 162 rk_clrsetreg(&cru->cru_mode_con, 163 GPLL_MODE_MASK | APLL_MODE_MASK, 164 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 165 APLL_MODE_NORM << APLL_MODE_SHIFT); 166 } 167 168 /* Get pll rate by id */ 169 static uint32_t rkclk_pll_get_rate(struct rk3128_cru *cru, 170 enum rk_clk_id clk_id) 171 { 172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 173 uint32_t con; 174 int pll_id = rk_pll_id(clk_id); 175 struct rk3128_pll *pll = &cru->pll[pll_id]; 176 static u8 clk_shift[CLK_COUNT] = { 177 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 178 GPLL_MODE_SHIFT, 0xff 179 }; 180 static u32 clk_mask[CLK_COUNT] = { 181 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, 182 GPLL_MODE_MASK, 0xff 183 }; 184 uint shift; 185 uint mask; 186 187 con = readl(&cru->cru_mode_con); 188 shift = clk_shift[clk_id]; 189 mask = clk_mask[clk_id]; 190 191 switch ((con & mask) >> shift) { 192 case GPLL_MODE_SLOW: 193 return OSC_HZ; 194 case GPLL_MODE_NORM: 195 196 /* normal mode */ 197 con = readl(&pll->con0); 198 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 199 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 200 con = readl(&pll->con1); 201 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 202 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 204 case GPLL_MODE_DEEP: 205 default: 206 return 32768; 207 } 208 } 209 210 static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate, 211 int periph) 212 { 213 uint src_rate; 214 uint div, mux; 215 u32 con; 216 217 switch (periph) { 218 case HCLK_EMMC: 219 case SCLK_EMMC: 220 case SCLK_EMMC_SAMPLE: 221 con = readl(&cru->cru_clksel_con[12]); 222 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 223 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 224 break; 225 case HCLK_SDMMC: 226 case SCLK_SDMMC: 227 con = readl(&cru->cru_clksel_con[11]); 228 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 229 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 230 break; 231 default: 232 return -EINVAL; 233 } 234 235 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 236 return DIV_TO_RATE(src_rate, div); 237 } 238 239 static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate, 240 int periph, uint freq) 241 { 242 int src_clk_div; 243 int mux; 244 245 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 246 247 /* mmc clock defaulg div 2 internal, need provide double in cru */ 248 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 249 250 if (src_clk_div > 128) { 251 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 252 mux = EMMC_SEL_24M; 253 } else { 254 mux = EMMC_SEL_GPLL; 255 } 256 257 switch (periph) { 258 case HCLK_EMMC: 259 rk_clrsetreg(&cru->cru_clksel_con[12], 260 EMMC_PLL_MASK | EMMC_DIV_MASK, 261 mux << EMMC_PLL_SHIFT | 262 (src_clk_div - 1) << EMMC_DIV_SHIFT); 263 break; 264 case HCLK_SDMMC: 265 case SCLK_SDMMC: 266 rk_clrsetreg(&cru->cru_clksel_con[11], 267 MMC0_PLL_MASK | MMC0_DIV_MASK, 268 mux << MMC0_PLL_SHIFT | 269 (src_clk_div - 1) << MMC0_DIV_SHIFT); 270 break; 271 default: 272 return -EINVAL; 273 } 274 275 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 276 } 277 278 static ulong rk3128_clk_get_rate(struct clk *clk) 279 { 280 struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); 281 282 switch (clk->id) { 283 case 0 ... 63: 284 return rkclk_pll_get_rate(priv->cru, clk->id); 285 default: 286 return -ENOENT; 287 } 288 } 289 290 static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate) 291 { 292 struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); 293 ulong new_rate, gclk_rate; 294 295 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 296 switch (clk->id) { 297 case 0 ... 63: 298 return 0; 299 case HCLK_EMMC: 300 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 301 clk->id, rate); 302 break; 303 default: 304 return -ENOENT; 305 } 306 307 return new_rate; 308 } 309 310 static struct clk_ops rk3128_clk_ops = { 311 .get_rate = rk3128_clk_get_rate, 312 .set_rate = rk3128_clk_set_rate, 313 }; 314 315 static int rk3128_clk_probe(struct udevice *dev) 316 { 317 struct rk3128_clk_priv *priv = dev_get_priv(dev); 318 319 priv->cru = (struct rk3128_cru *)devfdt_get_addr(dev); 320 rkclk_init(priv->cru); 321 322 return 0; 323 } 324 325 static int rk3128_clk_bind(struct udevice *dev) 326 { 327 int ret; 328 329 /* The reset driver does not have a device node, so bind it here */ 330 ret = device_bind_driver(gd->dm_root, "rk3128_sysreset", "reset", &dev); 331 if (ret) 332 debug("Warning: No RK3128 reset driver: ret=%d\n", ret); 333 334 return 0; 335 } 336 337 static const struct udevice_id rk3128_clk_ids[] = { 338 { .compatible = "rockchip,rk3128-cru" }, 339 { } 340 }; 341 342 U_BOOT_DRIVER(rockchip_rk3128_cru) = { 343 .name = "clk_rk3128", 344 .id = UCLASS_CLK, 345 .of_match = rk3128_clk_ids, 346 .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv), 347 .ops = &rk3128_clk_ops, 348 .bind = rk3128_clk_bind, 349 .probe = rk3128_clk_probe, 350 }; 351