1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3128.h> 15 #include <asm/arch/hardware.h> 16 #include <bitfield.h> 17 #include <dm/lists.h> 18 #include <dt-bindings/clock/rk3128-cru.h> 19 #include <linux/log2.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 enum { 24 VCO_MAX_HZ = 2400U * 1000000, 25 VCO_MIN_HZ = 600 * 1000000, 26 OUTPUT_MAX_HZ = 2400U * 1000000, 27 OUTPUT_MIN_HZ = 24 * 1000000, 28 }; 29 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) 31 32 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ 33 .refdiv = _refdiv,\ 34 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ 35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; 36 37 /* use integer mode*/ 38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); 39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); 40 41 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, 42 const struct pll_div *div) 43 { 44 int pll_id = rk_pll_id(clk_id); 45 struct rk3128_pll *pll = &cru->pll[pll_id]; 46 47 /* All PLLs have same VCO and output frequency range restrictions. */ 48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000; 49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; 50 51 debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n", 52 pll, div->fbdiv, div->refdiv, div->postdiv1, 53 div->postdiv2, vco_hz, output_hz); 54 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && 55 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); 56 57 /* use integer mode */ 58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 59 /* Power down */ 60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); 61 62 rk_clrsetreg(&pll->con0, 63 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); 65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 66 (div->postdiv2 << PLL_POSTDIV2_SHIFT | 67 div->refdiv << PLL_REFDIV_SHIFT)); 68 69 /* Power Up */ 70 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); 71 72 /* waiting for pll lock */ 73 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 74 udelay(1); 75 76 return 0; 77 } 78 79 static void rkclk_init(struct rk3128_cru *cru) 80 { 81 u32 aclk_div; 82 u32 hclk_div; 83 u32 pclk_div; 84 85 /* pll enter slow-mode */ 86 rk_clrsetreg(&cru->cru_mode_con, 87 GPLL_MODE_MASK | APLL_MODE_MASK, 88 GPLL_MODE_SLOW << GPLL_MODE_SHIFT | 89 APLL_MODE_SLOW << APLL_MODE_SHIFT); 90 91 /* init pll */ 92 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); 93 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); 94 95 /* 96 * select apll as cpu/core clock pll source and 97 * set up dependent divisors for PERI and ACLK clocks. 98 * core hz : apll = 1:1 99 */ 100 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1; 101 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7); 102 103 pclk_div = APLL_HZ / CORE_PERI_HZ - 1; 104 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf); 105 106 rk_clrsetreg(&cru->cru_clksel_con[0], 107 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK, 108 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT | 109 0 << CORE_DIV_CON_SHIFT); 110 111 rk_clrsetreg(&cru->cru_clksel_con[1], 112 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK, 113 aclk_div << CORE_ACLK_DIV_SHIFT | 114 pclk_div << CORE_PERI_DIV_SHIFT); 115 116 /* 117 * select gpll as pd_bus bus clock source and 118 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 119 */ 120 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1; 121 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); 122 123 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1; 124 assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7); 125 126 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1; 127 assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3); 128 129 rk_clrsetreg(&cru->cru_clksel_con[0], 130 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK, 131 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT | 132 aclk_div << BUS_ACLK_DIV_SHIFT); 133 134 rk_clrsetreg(&cru->cru_clksel_con[1], 135 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK, 136 pclk_div << BUS_PCLK_DIV_SHIFT | 137 hclk_div << BUS_HCLK_DIV_SHIFT); 138 139 /* 140 * select gpll as pd_peri bus clock source and 141 * set up dependent divisors for PCLK/HCLK and ACLK clocks. 142 */ 143 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; 144 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); 145 146 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); 147 assert((1 << hclk_div) * PERI_HCLK_HZ == 148 PERI_ACLK_HZ && (hclk_div < 0x4)); 149 150 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); 151 assert((1 << pclk_div) * PERI_PCLK_HZ == 152 PERI_ACLK_HZ && pclk_div < 0x8); 153 154 rk_clrsetreg(&cru->cru_clksel_con[10], 155 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK | 156 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK, 157 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT | 158 pclk_div << PERI_PCLK_DIV_SHIFT | 159 hclk_div << PERI_HCLK_DIV_SHIFT | 160 aclk_div << PERI_ACLK_DIV_SHIFT); 161 162 /* PLL enter normal-mode */ 163 rk_clrsetreg(&cru->cru_mode_con, 164 GPLL_MODE_MASK | APLL_MODE_MASK, 165 GPLL_MODE_NORM << GPLL_MODE_SHIFT | 166 APLL_MODE_NORM << APLL_MODE_SHIFT); 167 } 168 169 /* Get pll rate by id */ 170 static uint32_t rkclk_pll_get_rate(struct rk3128_cru *cru, 171 enum rk_clk_id clk_id) 172 { 173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; 174 uint32_t con; 175 int pll_id = rk_pll_id(clk_id); 176 struct rk3128_pll *pll = &cru->pll[pll_id]; 177 static u8 clk_shift[CLK_COUNT] = { 178 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff, 179 GPLL_MODE_SHIFT, 0xff 180 }; 181 static u32 clk_mask[CLK_COUNT] = { 182 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff, 183 GPLL_MODE_MASK, 0xff 184 }; 185 uint shift; 186 uint mask; 187 188 con = readl(&cru->cru_mode_con); 189 shift = clk_shift[clk_id]; 190 mask = clk_mask[clk_id]; 191 192 switch ((con & mask) >> shift) { 193 case GPLL_MODE_SLOW: 194 return OSC_HZ; 195 case GPLL_MODE_NORM: 196 197 /* normal mode */ 198 con = readl(&pll->con0); 199 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 200 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 201 con = readl(&pll->con1); 202 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 203 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; 205 case GPLL_MODE_DEEP: 206 default: 207 return 32768; 208 } 209 } 210 211 static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate, 212 int periph) 213 { 214 uint src_rate; 215 uint div, mux; 216 u32 con; 217 218 switch (periph) { 219 case HCLK_EMMC: 220 case SCLK_EMMC: 221 case SCLK_EMMC_SAMPLE: 222 con = readl(&cru->cru_clksel_con[12]); 223 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; 224 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 225 break; 226 case HCLK_SDMMC: 227 case SCLK_SDMMC: 228 con = readl(&cru->cru_clksel_con[11]); 229 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; 230 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; 231 break; 232 default: 233 return -EINVAL; 234 } 235 236 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate; 237 return DIV_TO_RATE(src_rate, div); 238 } 239 240 static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate, 241 int periph, uint freq) 242 { 243 int src_clk_div; 244 int mux; 245 246 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate); 247 248 /* mmc clock defaulg div 2 internal, need provide double in cru */ 249 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq); 250 251 if (src_clk_div > 128) { 252 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); 253 mux = EMMC_SEL_24M; 254 } else { 255 mux = EMMC_SEL_GPLL; 256 } 257 258 switch (periph) { 259 case HCLK_EMMC: 260 rk_clrsetreg(&cru->cru_clksel_con[12], 261 EMMC_PLL_MASK | EMMC_DIV_MASK, 262 mux << EMMC_PLL_SHIFT | 263 (src_clk_div - 1) << EMMC_DIV_SHIFT); 264 break; 265 case HCLK_SDMMC: 266 case SCLK_SDMMC: 267 rk_clrsetreg(&cru->cru_clksel_con[11], 268 MMC0_PLL_MASK | MMC0_DIV_MASK, 269 mux << MMC0_PLL_SHIFT | 270 (src_clk_div - 1) << MMC0_DIV_SHIFT); 271 break; 272 default: 273 return -EINVAL; 274 } 275 276 return rockchip_mmc_get_clk(cru, clk_general_rate, periph); 277 } 278 279 static ulong rk3128_i2c_get_clk(struct rk3128_cru *cru, ulong clk_id) 280 { 281 u32 div, con; 282 283 switch (clk_id) { 284 case PCLK_I2C0: 285 case PCLK_I2C1: 286 case PCLK_I2C2: 287 case PCLK_I2C3: 288 con = readl(&cru->cru_clksel_con[10]); 289 div = con >> 12 & 0x3; 290 break; 291 default: 292 printf("do not support this i2c bus\n"); 293 return -EINVAL; 294 } 295 296 return DIV_TO_RATE(PERI_ACLK_HZ, div); 297 } 298 299 static ulong rk3128_i2c_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz) 300 { 301 int src_clk_div; 302 303 src_clk_div = PERI_ACLK_HZ / hz; 304 assert(src_clk_div - 1 < 4); 305 306 switch (clk_id) { 307 case PCLK_I2C0: 308 case PCLK_I2C1: 309 case PCLK_I2C2: 310 case PCLK_I2C3: 311 rk_setreg(&cru->cru_clksel_con[10], 312 ((src_clk_div - 1) << 12)); 313 break; 314 default: 315 printf("do not support this i2c bus\n"); 316 return -EINVAL; 317 } 318 319 return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div); 320 } 321 322 static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru) 323 { 324 u32 div, val; 325 326 val = readl(&cru->cru_clksel_con[24]); 327 div = bitfield_extract(val, SARADC_DIV_CON_SHIFT, 328 SARADC_DIV_CON_WIDTH); 329 330 return DIV_TO_RATE(OSC_HZ, div); 331 } 332 333 static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz) 334 { 335 int src_clk_div; 336 337 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; 338 assert(src_clk_div < 128); 339 340 rk_clrsetreg(&cru->cru_clksel_con[24], 341 SARADC_DIV_CON_MASK, 342 src_clk_div << SARADC_DIV_CON_SHIFT); 343 344 return rk3128_saradc_get_clk(cru); 345 } 346 347 static ulong rk3128_clk_get_rate(struct clk *clk) 348 { 349 struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); 350 351 switch (clk->id) { 352 case 0 ... 63: 353 return rkclk_pll_get_rate(priv->cru, clk->id); 354 case PCLK_I2C0: 355 case PCLK_I2C1: 356 case PCLK_I2C2: 357 case PCLK_I2C3: 358 return rk3128_i2c_get_clk(priv->cru, clk->id); 359 case SCLK_SARADC: 360 return rk3128_saradc_get_clk(priv->cru); 361 default: 362 return -ENOENT; 363 } 364 } 365 366 static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate) 367 { 368 struct rk3128_clk_priv *priv = dev_get_priv(clk->dev); 369 ulong new_rate, gclk_rate; 370 371 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); 372 switch (clk->id) { 373 case 0 ... 63: 374 return 0; 375 case HCLK_EMMC: 376 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate, 377 clk->id, rate); 378 break; 379 case PCLK_I2C0: 380 case PCLK_I2C1: 381 case PCLK_I2C2: 382 case PCLK_I2C3: 383 new_rate = rk3128_i2c_set_clk(priv->cru, clk->id, rate); 384 break; 385 case SCLK_SARADC: 386 new_rate = rk3128_saradc_set_clk(priv->cru, rate); 387 break; 388 default: 389 return -ENOENT; 390 } 391 392 return new_rate; 393 } 394 395 static struct clk_ops rk3128_clk_ops = { 396 .get_rate = rk3128_clk_get_rate, 397 .set_rate = rk3128_clk_set_rate, 398 }; 399 400 static int rk3128_clk_probe(struct udevice *dev) 401 { 402 struct rk3128_clk_priv *priv = dev_get_priv(dev); 403 404 priv->cru = (struct rk3128_cru *)devfdt_get_addr(dev); 405 rkclk_init(priv->cru); 406 407 return 0; 408 } 409 410 static int rk3128_clk_bind(struct udevice *dev) 411 { 412 int ret; 413 414 /* The reset driver does not have a device node, so bind it here */ 415 ret = device_bind_driver(gd->dm_root, "rk3128_sysreset", "reset", &dev); 416 if (ret) 417 debug("Warning: No RK3128 reset driver: ret=%d\n", ret); 418 419 return 0; 420 } 421 422 static const struct udevice_id rk3128_clk_ids[] = { 423 { .compatible = "rockchip,rk3128-cru" }, 424 { } 425 }; 426 427 U_BOOT_DRIVER(rockchip_rk3128_cru) = { 428 .name = "clk_rk3128", 429 .id = UCLASS_CLK, 430 .of_match = rk3128_clk_ids, 431 .priv_auto_alloc_size = sizeof(struct rk3128_clk_priv), 432 .ops = &rk3128_clk_ops, 433 .bind = rk3128_clk_bind, 434 .probe = rk3128_clk_probe, 435 }; 436