| de94b80d | 24-Jun-2012 |
Lad, Prabhakar <prabhakar.lad@ti.com> |
da850/omap-l138: Fix NAND flash timings
Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm: setup the NAND flash timings) has configured the AEMIF timings, they are not exactly in s
da850/omap-l138: Fix NAND flash timings
Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm: setup the NAND flash timings) has configured the AEMIF timings, they are not exactly in sync with the timings used in Linux. Linux is configuring the timing register as 0x08222204, where as currently it configured to 0x00100084 in U-Boot. This issue was found out when support for NAND SPL is added in U-Boot. Without this patch U-Boot does not come up with SPL.
Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
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| 6652c62e | 24-Jun-2012 |
Rajashekhara, Sudhakar <sudhakar.raj@ti.com> |
da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When GP0[11] is low, the SD0 in
da850/omap-l138: modifications for Logic PD Rev.3 AM18xx EVM
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. When GP0[11] is high, SD0 will work but NOR flash will not.
Tested-by: Christian Riesch <christian.riesch@omicron.at> Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com> Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
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