1/* 2 * armboot - Startup Code for ARM1176 CPU-core 3 * 4 * Copyright (c) 2007 Samsung Electronics 5 * 6 * Copyright (C) 2008 7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com) 28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by 29 * jsgood (jsgood.yang@samsung.com) 30 * Base codes by scsuh (sc.suh) 31 */ 32 33#include <asm-offsets.h> 34#include <config.h> 35#include <version.h> 36#ifdef CONFIG_ENABLE_MMU 37#include <asm/proc/domain.h> 38#endif 39 40#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) 41#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE 42#endif 43 44/* 45 ************************************************************************* 46 * 47 * Jump vector table as in table 3.1 in [1] 48 * 49 ************************************************************************* 50 */ 51 52.globl _start 53_start: b reset 54#ifndef CONFIG_NAND_SPL 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: 64 .word undefined_instruction 65_software_interrupt: 66 .word software_interrupt 67_prefetch_abort: 68 .word prefetch_abort 69_data_abort: 70 .word data_abort 71_not_used: 72 .word not_used 73_irq: 74 .word irq 75_fiq: 76 .word fiq 77_pad: 78 .word 0x12345678 /* now 16*4=64 */ 79#else 80 . = _start + 64 81#endif 82 83.global _end_vect 84_end_vect: 85 .balignl 16,0xdeadbeef 86/* 87 ************************************************************************* 88 * 89 * Startup Code (reset vector) 90 * 91 * do important init only if we don't start from memory! 92 * setup Memory and board specific bits prior to relocation. 93 * relocate armboot to ram 94 * setup stack 95 * 96 ************************************************************************* 97 */ 98 99.globl _TEXT_BASE 100_TEXT_BASE: 101#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 102 .word CONFIG_SYS_TEXT_BASE 103#else 104#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 105 .word CONFIG_SPL_TEXT_BASE 106#else 107 .word CONFIG_SYS_TEXT_BASE 108#endif 109#endif 110 111/* 112 * Below variable is very important because we use MMU in U-Boot. 113 * Without it, we cannot run code correctly before MMU is ON. 114 * by scsuh. 115 */ 116_TEXT_PHY_BASE: 117 .word CONFIG_SYS_PHY_UBOOT_BASE 118 119/* 120 * These are defined in the board-specific linker script. 121 * Subtracting _start from them lets the linker put their 122 * relative position in the executable instead of leaving 123 * them null. 124 */ 125 126.globl _bss_start_ofs 127_bss_start_ofs: 128 .word __bss_start - _start 129 130.globl _image_copy_end_ofs 131_image_copy_end_ofs: 132 .word __image_copy_end - _start 133 134.globl _bss_end_ofs 135_bss_end_ofs: 136 .word __bss_end - _start 137 138.globl _end_ofs 139_end_ofs: 140 .word _end - _start 141 142/* IRQ stack memory (calculated at run-time) + 8 bytes */ 143.globl IRQ_STACK_START_IN 144IRQ_STACK_START_IN: 145 .word 0x0badc0de 146 147/* 148 * the actual reset code 149 */ 150 151reset: 152 /* 153 * set the cpu to SVC32 mode 154 */ 155 mrs r0, cpsr 156 bic r0, r0, #0x3f 157 orr r0, r0, #0xd3 158 msr cpsr, r0 159 160/* 161 ************************************************************************* 162 * 163 * CPU_init_critical registers 164 * 165 * setup important registers 166 * setup memory timing 167 * 168 ************************************************************************* 169 */ 170 /* 171 * we do sys-critical inits only at reboot, 172 * not when booting from ram! 173 */ 174cpu_init_crit: 175 /* 176 * When booting from NAND - it has definitely been a reset, so, no need 177 * to flush caches and disable the MMU 178 */ 179#ifndef CONFIG_NAND_SPL 180 /* 181 * flush v4 I/D caches 182 */ 183 mov r0, #0 184 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 185 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 186 187 /* 188 * disable MMU stuff and caches 189 */ 190 mrc p15, 0, r0, c1, c0, 0 191 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 192 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 193 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 194 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 195 196 /* Prepare to disable the MMU */ 197 adr r2, mmu_disable_phys 198 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE) 199 b mmu_disable 200 201 .align 5 202 /* Run in a single cache-line */ 203mmu_disable: 204 mcr p15, 0, r0, c1, c0, 0 205 nop 206 nop 207 mov pc, r2 208mmu_disable_phys: 209 210#ifdef CONFIG_DISABLE_TCM 211 /* 212 * Disable the TCMs 213 */ 214 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ 215 cmp r0, #0 216 beq skip_tcmdisable 217 mov r1, #0 218 mov r2, #1 219 tst r0, r2 220 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ 221 tst r0, r2, LSL #16 222 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ 223skip_tcmdisable: 224#endif 225#endif 226 227#ifdef CONFIG_PERIPORT_REMAP 228 /* Peri port setup */ 229 ldr r0, =CONFIG_PERIPORT_BASE 230 orr r0, r0, #CONFIG_PERIPORT_SIZE 231 mcr p15,0,r0,c15,c2,4 232#endif 233 234 /* 235 * Go setup Memory and board specific bits prior to relocation. 236 */ 237 bl lowlevel_init /* go setup pll,mux,memory */ 238 239 bl _main 240 241/*------------------------------------------------------------------------------*/ 242 243/* 244 * void relocate_code (addr_sp, gd, addr_moni) 245 * 246 * This function relocates the monitor code. 247 */ 248 .globl relocate_code 249relocate_code: 250 mov r4, r0 /* save addr_sp */ 251 mov r5, r1 /* save addr of gd */ 252 mov r6, r2 /* save addr of destination */ 253 254 adr r0, _start 255 subs r9, r6, r0 /* r9 <- relocation offset */ 256 beq relocate_done /* skip relocation */ 257 mov r1, r6 /* r1 <- scratch for copy_loop */ 258 ldr r3, _image_copy_end_ofs 259 add r2, r0, r3 /* r2 <- source end address */ 260 261copy_loop: 262 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 263 stmia r1!, {r10-r11} /* copy to target address [r1] */ 264 cmp r0, r2 /* until source end address [r2] */ 265 blo copy_loop 266 267#ifndef CONFIG_SPL_BUILD 268 /* 269 * fix .rel.dyn relocations 270 */ 271 ldr r0, _TEXT_BASE /* r0 <- Text base */ 272 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 273 add r10, r10, r0 /* r10 <- sym table in FLASH */ 274 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 275 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 276 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 277 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 278fixloop: 279 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 280 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 281 ldr r1, [r2, #4] 282 and r7, r1, #0xff 283 cmp r7, #23 /* relative fixup? */ 284 beq fixrel 285 cmp r7, #2 /* absolute fixup? */ 286 beq fixabs 287 /* ignore unknown type of fixup */ 288 b fixnext 289fixabs: 290 /* absolute fix: set location to (offset) symbol value */ 291 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 292 add r1, r10, r1 /* r1 <- address of symbol in table */ 293 ldr r1, [r1, #4] /* r1 <- symbol value */ 294 add r1, r1, r9 /* r1 <- relocated sym addr */ 295 b fixnext 296fixrel: 297 /* relative fix: increase location by offset */ 298 ldr r1, [r0] 299 add r1, r1, r9 300fixnext: 301 str r1, [r0] 302 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 303 cmp r2, r3 304 blo fixloop 305#endif 306 307#ifdef CONFIG_ENABLE_MMU 308enable_mmu: 309 /* enable domain access */ 310 ldr r5, =0x0000ffff 311 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ 312 313 /* Set the TTB register */ 314 ldr r0, _mmu_table_base 315 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE 316 ldr r2, =0xfff00000 317 bic r0, r0, r2 318 orr r1, r0, r1 319 mcr p15, 0, r1, c2, c0, 0 320 321 /* Enable the MMU */ 322 mrc p15, 0, r0, c1, c0, 0 323 orr r0, r0, #1 /* Set CR_M to enable MMU */ 324 325 /* Prepare to enable the MMU */ 326 adr r1, skip_hw_init 327 and r1, r1, #0x3fc 328 ldr r2, _TEXT_BASE 329 ldr r3, =0xfff00000 330 and r2, r2, r3 331 orr r2, r2, r1 332 b mmu_enable 333 334 .align 5 335 /* Run in a single cache-line */ 336mmu_enable: 337 338 mcr p15, 0, r0, c1, c0, 0 339 nop 340 nop 341 mov pc, r2 342skip_hw_init: 343#endif 344 345relocate_done: 346 347 bx lr 348 349_rel_dyn_start_ofs: 350 .word __rel_dyn_start - _start 351_rel_dyn_end_ofs: 352 .word __rel_dyn_end - _start 353_dynsym_start_ofs: 354 .word __dynsym_start - _start 355 356#ifdef CONFIG_ENABLE_MMU 357_mmu_table_base: 358 .word mmu_table 359#endif 360 361 .globl c_runtime_cpu_setup 362c_runtime_cpu_setup: 363 364 mov pc, lr 365 366#ifndef CONFIG_NAND_SPL 367/* 368 * we assume that cache operation is done before. (eg. cleanup_before_linux()) 369 * actually, we don't need to do anything about cache if not use d-cache in 370 * U-Boot. So, in this function we clean only MMU. by scsuh 371 * 372 * void theLastJump(void *kernel, int arch_num, uint boot_params); 373 */ 374#ifdef CONFIG_ENABLE_MMU 375 .globl theLastJump 376theLastJump: 377 mov r9, r0 378 ldr r3, =0xfff00000 379 ldr r4, _TEXT_PHY_BASE 380 adr r5, phy_last_jump 381 bic r5, r5, r3 382 orr r5, r5, r4 383 mov pc, r5 384phy_last_jump: 385 /* 386 * disable MMU stuff 387 */ 388 mrc p15, 0, r0, c1, c0, 0 389 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 390 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 391 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 392 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 393 mcr p15, 0, r0, c1, c0, 0 394 395 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 396 397 mov r0, #0 398 mov pc, r9 399#endif 400 401 402/* 403 ************************************************************************* 404 * 405 * Interrupt handling 406 * 407 ************************************************************************* 408 */ 409@ 410@ IRQ stack frame. 411@ 412#define S_FRAME_SIZE 72 413 414#define S_OLD_R0 68 415#define S_PSR 64 416#define S_PC 60 417#define S_LR 56 418#define S_SP 52 419 420#define S_IP 48 421#define S_FP 44 422#define S_R10 40 423#define S_R9 36 424#define S_R8 32 425#define S_R7 28 426#define S_R6 24 427#define S_R5 20 428#define S_R4 16 429#define S_R3 12 430#define S_R2 8 431#define S_R1 4 432#define S_R0 0 433 434#define MODE_SVC 0x13 435#define I_BIT 0x80 436 437/* 438 * use bad_save_user_regs for abort/prefetch/undef/swi ... 439 */ 440 441 .macro bad_save_user_regs 442 /* carve out a frame on current user stack */ 443 sub sp, sp, #S_FRAME_SIZE 444 /* Save user registers (now in svc mode) r0-r12 */ 445 stmia sp, {r0 - r12} 446 447 ldr r2, IRQ_STACK_START_IN 448 /* get values for "aborted" pc and cpsr (into parm regs) */ 449 ldmia r2, {r2 - r3} 450 /* grab pointer to old stack */ 451 add r0, sp, #S_FRAME_SIZE 452 453 add r5, sp, #S_SP 454 mov r1, lr 455 /* save sp_SVC, lr_SVC, pc, cpsr */ 456 stmia r5, {r0 - r3} 457 /* save current stack into r0 (param register) */ 458 mov r0, sp 459 .endm 460 461 .macro get_bad_stack 462 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 463 464 /* save caller lr in position 0 of saved stack */ 465 str lr, [r13] 466 /* get the spsr */ 467 mrs lr, spsr 468 /* save spsr in position 1 of saved stack */ 469 str lr, [r13, #4] 470 471 /* prepare SVC-Mode */ 472 mov r13, #MODE_SVC 473 @ msr spsr_c, r13 474 /* switch modes, make sure moves will execute */ 475 msr spsr, r13 476 /* capture return pc */ 477 mov lr, pc 478 /* jump to next instruction & switch modes. */ 479 movs pc, lr 480 .endm 481 482 .macro get_bad_stack_swi 483 /* space on current stack for scratch reg. */ 484 sub r13, r13, #4 485 /* save R0's value. */ 486 str r0, [r13] 487 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 488 /* save caller lr in position 0 of saved stack */ 489 str lr, [r0] 490 /* get the spsr */ 491 mrs r0, spsr 492 /* save spsr in position 1 of saved stack */ 493 str lr, [r0, #4] 494 /* restore r0 */ 495 ldr r0, [r13] 496 /* pop stack entry */ 497 add r13, r13, #4 498 .endm 499 500/* 501 * exception handlers 502 */ 503 .align 5 504undefined_instruction: 505 get_bad_stack 506 bad_save_user_regs 507 bl do_undefined_instruction 508 509 .align 5 510software_interrupt: 511 get_bad_stack_swi 512 bad_save_user_regs 513 bl do_software_interrupt 514 515 .align 5 516prefetch_abort: 517 get_bad_stack 518 bad_save_user_regs 519 bl do_prefetch_abort 520 521 .align 5 522data_abort: 523 get_bad_stack 524 bad_save_user_regs 525 bl do_data_abort 526 527 .align 5 528not_used: 529 get_bad_stack 530 bad_save_user_regs 531 bl do_not_used 532 533 .align 5 534irq: 535 get_bad_stack 536 bad_save_user_regs 537 bl do_irq 538 539 .align 5 540fiq: 541 get_bad_stack 542 bad_save_user_regs 543 bl do_fiq 544#endif /* CONFIG_NAND_SPL */ 545