1/* 2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core 3 * 4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com> 5 * 6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 10 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31#include <asm-offsets.h> 32#include <config.h> 33#include <version.h> 34.globl _start 35_start: b reset 36#ifdef CONFIG_SPL_BUILD 37 ldr pc, _hang 38 ldr pc, _hang 39 ldr pc, _hang 40 ldr pc, _hang 41 ldr pc, _hang 42 ldr pc, _hang 43 ldr pc, _hang 44 45_hang: 46 .word do_hang 47 .word 0x12345678 48 .word 0x12345678 49 .word 0x12345678 50 .word 0x12345678 51 .word 0x12345678 52 .word 0x12345678 53 .word 0x12345678 /* now 16*4=64 */ 54#else 55 ldr pc, _undefined_instruction 56 ldr pc, _software_interrupt 57 ldr pc, _prefetch_abort 58 ldr pc, _data_abort 59 ldr pc, _not_used 60 ldr pc, _irq 61 ldr pc, _fiq 62 63_undefined_instruction: .word undefined_instruction 64_software_interrupt: .word software_interrupt 65_prefetch_abort: .word prefetch_abort 66_data_abort: .word data_abort 67_not_used: .word not_used 68_irq: .word irq 69_fiq: .word fiq 70_pad: .word 0x12345678 /* now 16*4=64 */ 71#endif /* CONFIG_SPL_BUILD */ 72.global _end_vect 73_end_vect: 74 75 .balignl 16,0xdeadbeef 76/* 77 ************************************************************************* 78 * 79 * Startup Code (reset vector) 80 * 81 * do important init only if we don't start from memory! 82 * setup Memory and board specific bits prior to relocation. 83 * relocate armboot to ram 84 * setup stack 85 * 86 ************************************************************************* 87 */ 88 89.globl _TEXT_BASE 90_TEXT_BASE: 91#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 92 .word CONFIG_SPL_TEXT_BASE 93#else 94 .word CONFIG_SYS_TEXT_BASE 95#endif 96 97/* 98 * These are defined in the board-specific linker script. 99 * Subtracting _start from them lets the linker put their 100 * relative position in the executable instead of leaving 101 * them null. 102 */ 103.globl _bss_start_ofs 104_bss_start_ofs: 105 .word __bss_start - _start 106 107.globl _image_copy_end_ofs 108_image_copy_end_ofs: 109 .word __image_copy_end - _start 110 111.globl _bss_end_ofs 112_bss_end_ofs: 113 .word __bss_end - _start 114 115.globl _end_ofs 116_end_ofs: 117 .word _end - _start 118 119#ifdef CONFIG_USE_IRQ 120/* IRQ stack memory (calculated at run-time) */ 121.globl IRQ_STACK_START 122IRQ_STACK_START: 123 .word 0x0badc0de 124 125/* IRQ stack memory (calculated at run-time) */ 126.globl FIQ_STACK_START 127FIQ_STACK_START: 128 .word 0x0badc0de 129#endif 130 131/* IRQ stack memory (calculated at run-time) + 8 bytes */ 132.globl IRQ_STACK_START_IN 133IRQ_STACK_START_IN: 134 .word 0x0badc0de 135 136/* 137 * the actual reset code 138 */ 139 140reset: 141 /* 142 * set the cpu to SVC32 mode 143 */ 144 mrs r0,cpsr 145 bic r0,r0,#0x1f 146 orr r0,r0,#0xd3 147 msr cpsr,r0 148 149#ifdef CONFIG_OMAP2420H4 150 /* Copy vectors to mask ROM indirect addr */ 151 adr r0, _start /* r0 <- current position of code */ 152 add r0, r0, #4 /* skip reset vector */ 153 mov r2, #64 /* r2 <- size to copy */ 154 add r2, r0, r2 /* r2 <- source end address */ 155 mov r1, #SRAM_OFFSET0 /* build vect addr */ 156 mov r3, #SRAM_OFFSET1 157 add r1, r1, r3 158 mov r3, #SRAM_OFFSET2 159 add r1, r1, r3 160next: 161 ldmia r0!, {r3-r10} /* copy from source address [r0] */ 162 stmia r1!, {r3-r10} /* copy to target address [r1] */ 163 cmp r0, r2 /* until source end address [r2] */ 164 bne next /* loop until equal */ 165 bl cpy_clk_code /* put dpll adjust code behind vectors */ 166#endif 167 /* the mask ROM code should have PLL and others stable */ 168#ifndef CONFIG_SKIP_LOWLEVEL_INIT 169 bl cpu_init_crit 170#endif 171 172 bl _main 173 174/*------------------------------------------------------------------------------*/ 175 176/* 177 * void relocate_code (addr_sp, gd, addr_moni) 178 * 179 * This function relocates the monitor code. 180 */ 181 .globl relocate_code 182relocate_code: 183 mov r4, r0 /* save addr_sp */ 184 mov r5, r1 /* save addr of gd */ 185 mov r6, r2 /* save addr of destination */ 186 187 adr r0, _start 188 subs r9, r6, r0 /* r9 <- relocation offset */ 189 beq relocate_done /* skip relocation */ 190 mov r1, r6 /* r1 <- scratch for copy_loop */ 191 ldr r3, _image_copy_end_ofs 192 add r2, r0, r3 /* r2 <- source end address */ 193 194copy_loop: 195 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 196 stmia r1!, {r10-r11} /* copy to target address [r1] */ 197 cmp r0, r2 /* until source end address [r2] */ 198 blo copy_loop 199 200#ifndef CONFIG_SPL_BUILD 201 /* 202 * fix .rel.dyn relocations 203 */ 204 ldr r0, _TEXT_BASE /* r0 <- Text base */ 205 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 206 add r10, r10, r0 /* r10 <- sym table in FLASH */ 207 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 208 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 209 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 210 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 211fixloop: 212 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 213 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 214 ldr r1, [r2, #4] 215 and r7, r1, #0xff 216 cmp r7, #23 /* relative fixup? */ 217 beq fixrel 218 cmp r7, #2 /* absolute fixup? */ 219 beq fixabs 220 /* ignore unknown type of fixup */ 221 b fixnext 222fixabs: 223 /* absolute fix: set location to (offset) symbol value */ 224 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 225 add r1, r10, r1 /* r1 <- address of symbol in table */ 226 ldr r1, [r1, #4] /* r1 <- symbol value */ 227 add r1, r1, r9 /* r1 <- relocated sym addr */ 228 b fixnext 229fixrel: 230 /* relative fix: increase location by offset */ 231 ldr r1, [r0] 232 add r1, r1, r9 233fixnext: 234 str r1, [r0] 235 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 236 cmp r2, r3 237 blo fixloop 238#endif 239 240relocate_done: 241 242 bx lr 243 244#ifndef CONFIG_SPL_BUILD 245 246_rel_dyn_start_ofs: 247 .word __rel_dyn_start - _start 248_rel_dyn_end_ofs: 249 .word __rel_dyn_end - _start 250_dynsym_start_ofs: 251 .word __dynsym_start - _start 252 253#endif 254 255 .globl c_runtime_cpu_setup 256c_runtime_cpu_setup: 257 258 bx lr 259 260/* 261 ************************************************************************* 262 * 263 * CPU_init_critical registers 264 * 265 * setup important registers 266 * setup memory timing 267 * 268 ************************************************************************* 269 */ 270#ifndef CONFIG_SKIP_LOWLEVEL_INIT 271cpu_init_crit: 272 /* 273 * flush v4 I/D caches 274 */ 275 mov r0, #0 276 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 277 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 278 279 /* 280 * disable MMU stuff and caches 281 */ 282 mrc p15, 0, r0, c1, c0, 0 283 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 284 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 285 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 286 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 287 mcr p15, 0, r0, c1, c0, 0 288 289 /* 290 * Jump to board specific initialization... The Mask ROM will have already initialized 291 * basic memory. Go here to bump up clock rate and handle wake up conditions. 292 */ 293 mov ip, lr /* persevere link reg across call */ 294 bl lowlevel_init /* go setup pll,mux,memory */ 295 mov lr, ip /* restore link */ 296 mov pc, lr /* back to my caller */ 297#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 298 299#ifndef CONFIG_SPL_BUILD 300/* 301 ************************************************************************* 302 * 303 * Interrupt handling 304 * 305 ************************************************************************* 306 */ 307@ 308@ IRQ stack frame. 309@ 310#define S_FRAME_SIZE 72 311 312#define S_OLD_R0 68 313#define S_PSR 64 314#define S_PC 60 315#define S_LR 56 316#define S_SP 52 317 318#define S_IP 48 319#define S_FP 44 320#define S_R10 40 321#define S_R9 36 322#define S_R8 32 323#define S_R7 28 324#define S_R6 24 325#define S_R5 20 326#define S_R4 16 327#define S_R3 12 328#define S_R2 8 329#define S_R1 4 330#define S_R0 0 331 332#define MODE_SVC 0x13 333#define I_BIT 0x80 334 335/* 336 * use bad_save_user_regs for abort/prefetch/undef/swi ... 337 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 338 */ 339 340 .macro bad_save_user_regs 341 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 342 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 343 344 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 345 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 346 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 347 348 add r5, sp, #S_SP 349 mov r1, lr 350 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 351 mov r0, sp @ save current stack into r0 (param register) 352 .endm 353 354 .macro irq_save_user_regs 355 sub sp, sp, #S_FRAME_SIZE 356 stmia sp, {r0 - r12} @ Calling r0-r12 357 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 358 stmdb r8, {sp, lr}^ @ Calling SP, LR 359 str lr, [r8, #0] @ Save calling PC 360 mrs r6, spsr 361 str r6, [r8, #4] @ Save CPSR 362 str r0, [r8, #8] @ Save OLD_R0 363 mov r0, sp 364 .endm 365 366 .macro irq_restore_user_regs 367 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 368 mov r0, r0 369 ldr lr, [sp, #S_PC] @ Get PC 370 add sp, sp, #S_FRAME_SIZE 371 subs pc, lr, #4 @ return & move spsr_svc into cpsr 372 .endm 373 374 .macro get_bad_stack 375 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 376 377 str lr, [r13] @ save caller lr in position 0 of saved stack 378 mrs lr, spsr @ get the spsr 379 str lr, [r13, #4] @ save spsr in position 1 of saved stack 380 381 mov r13, #MODE_SVC @ prepare SVC-Mode 382 @ msr spsr_c, r13 383 msr spsr, r13 @ switch modes, make sure moves will execute 384 mov lr, pc @ capture return pc 385 movs pc, lr @ jump to next instruction & switch modes. 386 .endm 387 388 .macro get_bad_stack_swi 389 sub r13, r13, #4 @ space on current stack for scratch reg. 390 str r0, [r13] @ save R0's value. 391 ldr r0, IRQ_STACK_START_IN @ get data regions start 392 str lr, [r0] @ save caller lr in position 0 of saved stack 393 mrs r0, spsr @ get the spsr 394 str lr, [r0, #4] @ save spsr in position 1 of saved stack 395 ldr r0, [r13] @ restore r0 396 add r13, r13, #4 @ pop stack entry 397 .endm 398 399 .macro get_irq_stack @ setup IRQ stack 400 ldr sp, IRQ_STACK_START 401 .endm 402 403 .macro get_fiq_stack @ setup FIQ stack 404 ldr sp, FIQ_STACK_START 405 .endm 406#endif /* CONFIG_SPL_BUILD */ 407 408/* 409 * exception handlers 410 */ 411#ifdef CONFIG_SPL_BUILD 412 .align 5 413do_hang: 414 ldr sp, _TEXT_BASE /* use 32 words about stack */ 415 bl hang /* hang and never return */ 416#else /* !CONFIG_SPL_BUILD */ 417 .align 5 418undefined_instruction: 419 get_bad_stack 420 bad_save_user_regs 421 bl do_undefined_instruction 422 423 .align 5 424software_interrupt: 425 get_bad_stack_swi 426 bad_save_user_regs 427 bl do_software_interrupt 428 429 .align 5 430prefetch_abort: 431 get_bad_stack 432 bad_save_user_regs 433 bl do_prefetch_abort 434 435 .align 5 436data_abort: 437 get_bad_stack 438 bad_save_user_regs 439 bl do_data_abort 440 441 .align 5 442not_used: 443 get_bad_stack 444 bad_save_user_regs 445 bl do_not_used 446 447#ifdef CONFIG_USE_IRQ 448 449 .align 5 450irq: 451 get_irq_stack 452 irq_save_user_regs 453 bl do_irq 454 irq_restore_user_regs 455 456 .align 5 457fiq: 458 get_fiq_stack 459 /* someone ought to write a more effiction fiq_save_user_regs */ 460 irq_save_user_regs 461 bl do_fiq 462 irq_restore_user_regs 463 464#else 465 466 .align 5 467irq: 468 get_bad_stack 469 bad_save_user_regs 470 bl do_irq 471 472 .align 5 473fiq: 474 get_bad_stack 475 bad_save_user_regs 476 bl do_fiq 477 478#endif 479 .align 5 480.global arm1136_cache_flush 481arm1136_cache_flush: 482#if !defined(CONFIG_SYS_ICACHE_OFF) 483 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 484#endif 485#if !defined(CONFIG_SYS_DCACHE_OFF) 486 mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache 487#endif 488 mov pc, lr @ back to caller 489#endif /* CONFIG_SPL_BUILD */ 490