1/* 2 * armboot - Startup Code for ARM926EJS CPU-core 3 * 4 * Copyright (c) 2003 Texas Instruments 5 * 6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ 7 * 8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> 9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> 10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com> 12 * Copyright (c) 2003 Kshitij <kshitij@ti.com> 13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net> 14 * 15 * See file CREDITS for list of people who contributed to this 16 * project. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 */ 33 34#include <asm-offsets.h> 35#include <config.h> 36#include <common.h> 37#include <version.h> 38 39/* 40 ************************************************************************* 41 * 42 * Jump vector table as in table 3.1 in [1] 43 * 44 ************************************************************************* 45 */ 46 47 48#ifdef CONFIG_SYS_DV_NOR_BOOT_CFG 49.globl _start 50_start: 51.globl _NOR_BOOT_CFG 52_NOR_BOOT_CFG: 53 .word CONFIG_SYS_DV_NOR_BOOT_CFG 54 b reset 55#else 56.globl _start 57_start: 58 b reset 59#endif 60#ifdef CONFIG_SPL_BUILD 61/* No exception handlers in preloader */ 62 ldr pc, _hang 63 ldr pc, _hang 64 ldr pc, _hang 65 ldr pc, _hang 66 ldr pc, _hang 67 ldr pc, _hang 68 ldr pc, _hang 69 70_hang: 71 .word do_hang 72/* pad to 64 byte boundary */ 73 .word 0x12345678 74 .word 0x12345678 75 .word 0x12345678 76 .word 0x12345678 77 .word 0x12345678 78 .word 0x12345678 79 .word 0x12345678 80#else 81 ldr pc, _undefined_instruction 82 ldr pc, _software_interrupt 83 ldr pc, _prefetch_abort 84 ldr pc, _data_abort 85 ldr pc, _not_used 86 ldr pc, _irq 87 ldr pc, _fiq 88 89_undefined_instruction: 90 .word undefined_instruction 91_software_interrupt: 92 .word software_interrupt 93_prefetch_abort: 94 .word prefetch_abort 95_data_abort: 96 .word data_abort 97_not_used: 98 .word not_used 99_irq: 100 .word irq 101_fiq: 102 .word fiq 103 104#endif /* CONFIG_SPL_BUILD */ 105 .balignl 16,0xdeadbeef 106 107 108/* 109 ************************************************************************* 110 * 111 * Startup Code (reset vector) 112 * 113 * do important init only if we don't start from memory! 114 * setup Memory and board specific bits prior to relocation. 115 * relocate armboot to ram 116 * setup stack 117 * 118 ************************************************************************* 119 */ 120 121.globl _TEXT_BASE 122_TEXT_BASE: 123#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ 124 .word CONFIG_SYS_TEXT_BASE 125#else 126#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 127 .word CONFIG_SPL_TEXT_BASE 128#else 129 .word CONFIG_SYS_TEXT_BASE 130#endif 131#endif 132 133/* 134 * These are defined in the board-specific linker script. 135 * Subtracting _start from them lets the linker put their 136 * relative position in the executable instead of leaving 137 * them null. 138 */ 139.globl _bss_start_ofs 140_bss_start_ofs: 141 .word __bss_start - _start 142 143.globl _image_copy_end_ofs 144_image_copy_end_ofs: 145 .word __image_copy_end - _start 146 147.globl _bss_end_ofs 148_bss_end_ofs: 149 .word __bss_end - _start 150 151.globl _end_ofs 152_end_ofs: 153 .word _end - _start 154 155#ifdef CONFIG_NAND_U_BOOT 156.globl _end 157_end: 158 .word __bss_end 159#endif 160 161#ifdef CONFIG_USE_IRQ 162/* IRQ stack memory (calculated at run-time) */ 163.globl IRQ_STACK_START 164IRQ_STACK_START: 165 .word 0x0badc0de 166 167/* IRQ stack memory (calculated at run-time) */ 168.globl FIQ_STACK_START 169FIQ_STACK_START: 170 .word 0x0badc0de 171#endif 172 173/* IRQ stack memory (calculated at run-time) + 8 bytes */ 174.globl IRQ_STACK_START_IN 175IRQ_STACK_START_IN: 176 .word 0x0badc0de 177 178/* 179 * the actual reset code 180 */ 181 182reset: 183 /* 184 * set the cpu to SVC32 mode 185 */ 186 mrs r0,cpsr 187 bic r0,r0,#0x1f 188 orr r0,r0,#0xd3 189 msr cpsr,r0 190 191 /* 192 * we do sys-critical inits only at reboot, 193 * not when booting from ram! 194 */ 195#ifndef CONFIG_SKIP_LOWLEVEL_INIT 196 bl cpu_init_crit 197#endif 198 199 bl _main 200 201/*------------------------------------------------------------------------------*/ 202 203#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL) 204/* 205 * void relocate_code (addr_sp, gd, addr_moni) 206 * 207 * This function relocates the monitor code. 208 */ 209 .globl relocate_code 210relocate_code: 211 mov r4, r0 /* save addr_sp */ 212 mov r5, r1 /* save addr of gd */ 213 mov r6, r2 /* save addr of destination */ 214 215 adr r0, _start 216 subs r9, r6, r0 /* r9 <- relocation offset */ 217 beq relocate_done /* skip relocation */ 218 mov r1, r6 /* r1 <- scratch for copy loop */ 219 ldr r3, _image_copy_end_ofs 220 add r2, r0, r3 /* r2 <- source end address */ 221 222copy_loop: 223 ldmia r0!, {r10-r11} /* copy from source address [r0] */ 224 stmia r1!, {r10-r11} /* copy to target address [r1] */ 225 cmp r0, r2 /* until source end address [r2] */ 226 blo copy_loop 227 228#ifndef CONFIG_SPL_BUILD 229 /* 230 * fix .rel.dyn relocations 231 */ 232 ldr r0, _TEXT_BASE /* r0 <- Text base */ 233 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 234 add r10, r10, r0 /* r10 <- sym table in FLASH */ 235 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 236 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 237 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 238 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 239fixloop: 240 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 241 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 242 ldr r1, [r2, #4] 243 and r7, r1, #0xff 244 cmp r7, #23 /* relative fixup? */ 245 beq fixrel 246 cmp r7, #2 /* absolute fixup? */ 247 beq fixabs 248 /* ignore unknown type of fixup */ 249 b fixnext 250fixabs: 251 /* absolute fix: set location to (offset) symbol value */ 252 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 253 add r1, r10, r1 /* r1 <- address of symbol in table */ 254 ldr r1, [r1, #4] /* r1 <- symbol value */ 255 add r1, r1, r9 /* r1 <- relocated sym addr */ 256 b fixnext 257fixrel: 258 /* relative fix: increase location by offset */ 259 ldr r1, [r0] 260 add r1, r1, r9 261fixnext: 262 str r1, [r0] 263 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 264 cmp r2, r3 265 blo fixloop 266#endif 267 268relocate_done: 269 270 bx lr 271 272_rel_dyn_start_ofs: 273 .word __rel_dyn_start - _start 274_rel_dyn_end_ofs: 275 .word __rel_dyn_end - _start 276_dynsym_start_ofs: 277 .word __dynsym_start - _start 278 279#endif 280 281 .globl c_runtime_cpu_setup 282c_runtime_cpu_setup: 283 284 bx lr 285 286/* 287 ************************************************************************* 288 * 289 * CPU_init_critical registers 290 * 291 * setup important registers 292 * setup memory timing 293 * 294 ************************************************************************* 295 */ 296#ifndef CONFIG_SKIP_LOWLEVEL_INIT 297cpu_init_crit: 298 /* 299 * flush D cache before disabling it 300 */ 301 mov r0, #0 302flush_dcache: 303 mrc p15, 0, r15, c7, c10, 3 304 bne flush_dcache 305 306 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */ 307 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */ 308 309 /* 310 * disable MMU and D cache 311 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined 312 */ 313 mrc p15, 0, r0, c1, c0, 0 314 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ 315 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ 316#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH 317 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */ 318#else 319 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ 320#endif 321 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ 322#ifndef CONFIG_SYS_ICACHE_OFF 323 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ 324#endif 325 mcr p15, 0, r0, c1, c0, 0 326 327 /* 328 * Go setup Memory and board specific bits prior to relocation. 329 */ 330 mov ip, lr /* perserve link reg across call */ 331 bl lowlevel_init /* go setup pll,mux,memory */ 332 mov lr, ip /* restore link */ 333 mov pc, lr /* back to my caller */ 334#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ 335 336#ifndef CONFIG_SPL_BUILD 337/* 338 ************************************************************************* 339 * 340 * Interrupt handling 341 * 342 ************************************************************************* 343 */ 344 345@ 346@ IRQ stack frame. 347@ 348#define S_FRAME_SIZE 72 349 350#define S_OLD_R0 68 351#define S_PSR 64 352#define S_PC 60 353#define S_LR 56 354#define S_SP 52 355 356#define S_IP 48 357#define S_FP 44 358#define S_R10 40 359#define S_R9 36 360#define S_R8 32 361#define S_R7 28 362#define S_R6 24 363#define S_R5 20 364#define S_R4 16 365#define S_R3 12 366#define S_R2 8 367#define S_R1 4 368#define S_R0 0 369 370#define MODE_SVC 0x13 371#define I_BIT 0x80 372 373/* 374 * use bad_save_user_regs for abort/prefetch/undef/swi ... 375 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 376 */ 377 378 .macro bad_save_user_regs 379 @ carve out a frame on current user stack 380 sub sp, sp, #S_FRAME_SIZE 381 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 382 ldr r2, IRQ_STACK_START_IN 383 @ get values for "aborted" pc and cpsr (into parm regs) 384 ldmia r2, {r2 - r3} 385 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 386 add r5, sp, #S_SP 387 mov r1, lr 388 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 389 mov r0, sp @ save current stack into r0 (param register) 390 .endm 391 392 .macro irq_save_user_regs 393 sub sp, sp, #S_FRAME_SIZE 394 stmia sp, {r0 - r12} @ Calling r0-r12 395 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 396 add r8, sp, #S_PC 397 stmdb r8, {sp, lr}^ @ Calling SP, LR 398 str lr, [r8, #0] @ Save calling PC 399 mrs r6, spsr 400 str r6, [r8, #4] @ Save CPSR 401 str r0, [r8, #8] @ Save OLD_R0 402 mov r0, sp 403 .endm 404 405 .macro irq_restore_user_regs 406 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 407 mov r0, r0 408 ldr lr, [sp, #S_PC] @ Get PC 409 add sp, sp, #S_FRAME_SIZE 410 subs pc, lr, #4 @ return & move spsr_svc into cpsr 411 .endm 412 413 .macro get_bad_stack 414 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 415 416 str lr, [r13] @ save caller lr in position 0 of saved stack 417 mrs lr, spsr @ get the spsr 418 str lr, [r13, #4] @ save spsr in position 1 of saved stack 419 mov r13, #MODE_SVC @ prepare SVC-Mode 420 @ msr spsr_c, r13 421 msr spsr, r13 @ switch modes, make sure moves will execute 422 mov lr, pc @ capture return pc 423 movs pc, lr @ jump to next instruction & switch modes. 424 .endm 425 426 .macro get_irq_stack @ setup IRQ stack 427 ldr sp, IRQ_STACK_START 428 .endm 429 430 .macro get_fiq_stack @ setup FIQ stack 431 ldr sp, FIQ_STACK_START 432 .endm 433#endif /* CONFIG_SPL_BUILD */ 434 435/* 436 * exception handlers 437 */ 438#ifdef CONFIG_SPL_BUILD 439 .align 5 440do_hang: 441 ldr sp, _TEXT_BASE /* switch to abort stack */ 4421: 443 bl 1b /* hang and never return */ 444#else /* !CONFIG_SPL_BUILD */ 445 .align 5 446undefined_instruction: 447 get_bad_stack 448 bad_save_user_regs 449 bl do_undefined_instruction 450 451 .align 5 452software_interrupt: 453 get_bad_stack 454 bad_save_user_regs 455 bl do_software_interrupt 456 457 .align 5 458prefetch_abort: 459 get_bad_stack 460 bad_save_user_regs 461 bl do_prefetch_abort 462 463 .align 5 464data_abort: 465 get_bad_stack 466 bad_save_user_regs 467 bl do_data_abort 468 469 .align 5 470not_used: 471 get_bad_stack 472 bad_save_user_regs 473 bl do_not_used 474 475#ifdef CONFIG_USE_IRQ 476 477 .align 5 478irq: 479 get_irq_stack 480 irq_save_user_regs 481 bl do_irq 482 irq_restore_user_regs 483 484 .align 5 485fiq: 486 get_fiq_stack 487 /* someone ought to write a more effiction fiq_save_user_regs */ 488 irq_save_user_regs 489 bl do_fiq 490 irq_restore_user_regs 491 492#else 493 494 .align 5 495irq: 496 get_bad_stack 497 bad_save_user_regs 498 bl do_irq 499 500 .align 5 501fiq: 502 get_bad_stack 503 bad_save_user_regs 504 bl do_fiq 505 506#endif 507#endif /* CONFIG_SPL_BUILD */ 508