clk: rockchip: rk3308: Add support to set and get pll rate

Change-Id: Idfbe59c3f1d12d0e9adcb253e3d6db9e994bc44c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: clk: rv1108: Add some frequency setting interfaces

support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.

Change-Id: I894552c1e1bb1bd

rockchip: clk: rv1108: Add some frequency setting interfaces

support PLL freq setting,
support bus and peri clk freq setting,
support aclk vio and dclk vop freq setting.

Change-Id: I894552c1e1bb1bd13a143e200edf289234a53c1d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

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clk: rockchip: rk3308: Move pll rate into clk private data

Change-Id: I424259266a4c76031192bf07d52c29cd3e48ec0a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: support alternative kernel dtb depends on adc/gpio

1. support adc value recognize;
2. support gpio value recognize;

Change-Id: I8bcbdd914405184d46029c4995c09b09e36c7ea3
Signed-off-by: Jos

rockchip: support alternative kernel dtb depends on adc/gpio

1. support adc value recognize;
2. support gpio value recognize;

Change-Id: I8bcbdd914405184d46029c4995c09b09e36c7ea3
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rockchip: sdram: updata ddr config to v1.08

1.Add more ddr rows support,such as 12 rows and 17 rows.
2.Support different column for different cs.

Change-Id: Iacb9b8545433c7172ff3f1090987f7d1d569938

rockchip: sdram: updata ddr config to v1.08

1.Add more ddr rows support,such as 12 rows and 17 rows.
2.Support different column for different cs.

Change-Id: Iacb9b8545433c7172ff3f1090987f7d1d5699381
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

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clk: rockchip: rk3308: Add support to set dclk_vop rate

Change-Id: Ib7b5d35d4a65167d660f254600e0673bebd70432
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

config: Add CONFIG_TINY_TPL to disable SPL framework at TPL

Some devices cann't use SPL framework at TPL stage, but the
CONFIG_SPL_FRAMEWORK is still defined at TPL stage, so need
to separate them w

config: Add CONFIG_TINY_TPL to disable SPL framework at TPL

Some devices cann't use SPL framework at TPL stage, but the
CONFIG_SPL_FRAMEWORK is still defined at TPL stage, so need
to separate them with CONFIG_TINY_TPL.

If the SPL framewrok was used both at TPL and SPL stage,
CONFIG_TINY_TPL is not defined.
If the SPL framewrok was used at SPL stage, but not use at
TPL, need to define CONFIG_TINY_TPL.

Change-Id: Iabb7e0377ee00311ca468cb8ff7544c96bd999d6
Signed-off-by: David Wu <david.wu@rock-chips.com>

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rockchip: clk: rk3036: Add power down and power up for pll set

If power down and power up were not done, there was an error during
pll setting again.

Change-Id: Iaa5ef558c2bff270614f08d96a70e5c847c

rockchip: clk: rk3036: Add power down and power up for pll set

If power down and power up were not done, there was an error during
pll setting again.

Change-Id: Iaa5ef558c2bff270614f08d96a70e5c847ce927c
Signed-off-by: David Wu <david.wu@rock-chips.com>

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clk: rockchip: add clk driver for rk3308

Add basic clock for px30 which including cpu, bus, emmc, i2c,
spi, pwm, saradc clock init.

Change-Id: Idd8542d7833e4997378bce99e0a464d5d16890fd
Signed-off-b

clk: rockchip: add clk driver for rk3308

Add basic clock for px30 which including cpu, bus, emmc, i2c,
spi, pwm, saradc clock init.

Change-Id: Idd8542d7833e4997378bce99e0a464d5d16890fd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

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arm: rockchip: add RK3308 SOC support

RK3308 is a Soc from Rockchip, which embedded with quad
ARM Cortex-A35 and highly integrated audio interfaces.

Change-Id: I93958481f2e9f0f8d8c40bbfaaa3899cd82e

arm: rockchip: add RK3308 SOC support

RK3308 is a Soc from Rockchip, which embedded with quad
ARM Cortex-A35 and highly integrated audio interfaces.

Change-Id: I93958481f2e9f0f8d8c40bbfaaa3899cd82ec43d
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

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pwm: rockchip: Update PWM driver to support all Rockchip Socs

The new PWM driver support PWM polarity, lock, voppwm and more
functions. In most cases, the PWM requires the same configuration
as kern

pwm: rockchip: Update PWM driver to support all Rockchip Socs

The new PWM driver support PWM polarity, lock, voppwm and more
functions. In most cases, the PWM requires the same configuration
as kernel to reduce the intermediate state between uboot and kernel,
so we sync the code with driver.

Change-Id: Ife5b8470f72eed197dd48e949bcf7da95b9de34c
Signed-off-by: David Wu <david.wu@rock-chips.com>

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rockchip: clk: px30: only do one time clk init

We may get into clk_probe more than one time from TPL/SPL/U-Boot,
and we only need to init bus clock one time.

Change-Id: Iab0434c66d344ff57c1edd30679

rockchip: clk: px30: only do one time clk init

We may get into clk_probe more than one time from TPL/SPL/U-Boot,
and we only need to init bus clock one time.

Change-Id: Iab0434c66d344ff57c1edd30679c3ab3bb8f2b17
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

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clk: rockchip: rk3399: refactor configure cpu clock function

some board request enable cpu big core clock in uboot,
refactor rk3399_configure_cpu() function, so that the little
core and big core can

clk: rockchip: rk3399: refactor configure cpu clock function

some board request enable cpu big core clock in uboot,
refactor rk3399_configure_cpu() function, so that the little
core and big core can reuse this function to set clock.

Change-Id: I0390d22179faf91307b22348f6f9329a58f00143
Signed-off-by: Lin Huang <hl@rock-chips.com>

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clk: rockchip: rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ

This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock

clk: rockchip: rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ

This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock to always run at
the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our
previous tests and validation with this bug, we should probably increase
the value of the constant (that had not actually been used) to the value
that we had been incorrectly using instead.

Change-Id: I8e1725f71ea0dbacd01929b8e8a80b91dc4f17cc
Signed-off-by: Lin Huang <hl@rock-chips.com>

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arm: Bump COMMAND_LINE_SIZE to 2048

The current limit is small for avb Boot args.

Change-Id: I381fc1a09a533036427a3ed29395eae2f18208d1
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>

rockchip: smccc: add psci_cpu_on function

With this function, we can up other cpu in Uboot.

Change-Id: I968b5e05ce42a1bf799dbae7e8d4dfcc3fd958f1
Signed-off-by: Lin Huang <hl@rock-chips.com>

clk: rockchip: px30: Add support to set and get rate for vopb

Change-Id: I5105c4823ffd6632c29a8faa80b995f7ef0decaa
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: px30: Modify gpll to 1200MHz

Change-Id: Ia853acdc1d6c7085712379680b6fb1ed6a5802d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

clk: rockchip: px30: Move pll mode operation into rkclk_set_pll

Change-Id: I55bc3f9eedd41c40b8e424b482ad620b248262b1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

rockchip: recoganize boot devtype dynamicly

currently support: emmc and rknand.

Change-Id: I8b0e2623256ed3357de2acbee0d2455162228ab5
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb

clk: rockchip: clk_rk3368: Implement "assign-clock-parent"

Implement the setting parent for gmac clock, and add internal
pll div set for mac clk.

Change-Id: I4f75d0c1e35bbe7ff0af07d05dbb42f4732d5eb7
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefini

rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

Clean the iomux definitions at grf_rk322x.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.
After that, define the uart2 iomux at rk322x-board file.

Change-Id: If409e90706650de9fbe75b5c5fa47498cbbc79fe
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver

Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefini

rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver

Clean the iomux definitions at grf_rk3328.h, and move them into
pinctrl-driver for resolving the compiling error of redefinition.

Change-Id: I6297fa72bff03a0d0620982b2f8745cd1dbe2e8e
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver

If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitio

rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver

If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the
conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h,
and move them into pinctrl-driver.

Change-Id: Ie47ccd77963de909acf3494ad7e3ce20b3c560a6
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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rockchip: grf_rv1108.h: Fix the grf offsets

The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.

Change-Id: I4bbc7e8fcd04321d5ebcfb2c1a288ea49c0eddfc
Signed-off-by: Davi

rockchip: grf_rv1108.h: Fix the grf offsets

The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.

Change-Id: I4bbc7e8fcd04321d5ebcfb2c1a288ea49c0eddfc
Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

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