1 /* 2 * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Rockchip GMAC ethernet IP driver for U-Boot 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <clk.h> 12 #include <phy.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/grf_rk3288.h> 19 #include <asm/arch/grf_rk3328.h> 20 #include <asm/arch/grf_rk3368.h> 21 #include <asm/arch/grf_rk3399.h> 22 #include <asm/arch/grf_rv1108.h> 23 #include <dm/pinctrl.h> 24 #include <dt-bindings/clock/rk3288-cru.h> 25 #include "designware.h" 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 /* 30 * Platform data for the gmac 31 * 32 * dw_eth_pdata: Required platform data for designware driver (must be first) 33 */ 34 struct gmac_rockchip_platdata { 35 struct dw_eth_pdata dw_eth_pdata; 36 bool clock_input; 37 int tx_delay; 38 int rx_delay; 39 }; 40 41 struct rk_gmac_ops { 42 int (*fix_mac_speed)(struct dw_eth_dev *priv); 43 void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); 44 void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); 45 }; 46 47 void gmac_set_rgmii(struct udevice *dev, u32 tx_delay, u32 rx_delay) 48 { 49 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 50 struct rk_gmac_ops *ops = 51 (struct rk_gmac_ops *)dev_get_driver_data(dev); 52 53 pdata->tx_delay = tx_delay; 54 pdata->rx_delay = rx_delay; 55 56 ops->set_to_rgmii(pdata); 57 } 58 59 static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) 60 { 61 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 62 const char *string; 63 64 string = dev_read_string(dev, "clock_in_out"); 65 if (!strcmp(string, "input")) 66 pdata->clock_input = true; 67 else 68 pdata->clock_input = false; 69 70 /* Check the new naming-style first... */ 71 pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); 72 pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); 73 74 /* ... and fall back to the old naming style or default, if necessary */ 75 if (pdata->tx_delay == -ENOENT) 76 pdata->tx_delay = dev_read_u32_default(dev, "tx-delay", 0x30); 77 if (pdata->rx_delay == -ENOENT) 78 pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10); 79 80 return designware_eth_ofdata_to_platdata(dev); 81 } 82 83 static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) 84 { 85 struct rk3288_grf *grf; 86 int clk; 87 88 switch (priv->phydev->speed) { 89 case 10: 90 clk = RK3288_GMAC_CLK_SEL_2_5M; 91 break; 92 case 100: 93 clk = RK3288_GMAC_CLK_SEL_25M; 94 break; 95 case 1000: 96 clk = RK3288_GMAC_CLK_SEL_125M; 97 break; 98 default: 99 debug("Unknown phy speed: %d\n", priv->phydev->speed); 100 return -EINVAL; 101 } 102 103 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 104 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); 105 106 return 0; 107 } 108 109 static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) 110 { 111 struct rk3328_grf_regs *grf; 112 int clk; 113 enum { 114 RK3328_GMAC_CLK_SEL_SHIFT = 11, 115 RK3328_GMAC_CLK_SEL_MASK = GENMASK(12, 11), 116 RK3328_GMAC_CLK_SEL_125M = 0 << 11, 117 RK3328_GMAC_CLK_SEL_25M = 3 << 11, 118 RK3328_GMAC_CLK_SEL_2_5M = 2 << 11, 119 }; 120 121 switch (priv->phydev->speed) { 122 case 10: 123 clk = RK3328_GMAC_CLK_SEL_2_5M; 124 break; 125 case 100: 126 clk = RK3328_GMAC_CLK_SEL_25M; 127 break; 128 case 1000: 129 clk = RK3328_GMAC_CLK_SEL_125M; 130 break; 131 default: 132 debug("Unknown phy speed: %d\n", priv->phydev->speed); 133 return -EINVAL; 134 } 135 136 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 137 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); 138 139 return 0; 140 } 141 142 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) 143 { 144 struct rk3368_grf *grf; 145 int clk; 146 enum { 147 RK3368_GMAC_CLK_SEL_2_5M = 2 << 4, 148 RK3368_GMAC_CLK_SEL_25M = 3 << 4, 149 RK3368_GMAC_CLK_SEL_125M = 0 << 4, 150 RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4), 151 }; 152 153 switch (priv->phydev->speed) { 154 case 10: 155 clk = RK3368_GMAC_CLK_SEL_2_5M; 156 break; 157 case 100: 158 clk = RK3368_GMAC_CLK_SEL_25M; 159 break; 160 case 1000: 161 clk = RK3368_GMAC_CLK_SEL_125M; 162 break; 163 default: 164 debug("Unknown phy speed: %d\n", priv->phydev->speed); 165 return -EINVAL; 166 } 167 168 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 169 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); 170 171 return 0; 172 } 173 174 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) 175 { 176 struct rk3399_grf_regs *grf; 177 int clk; 178 179 switch (priv->phydev->speed) { 180 case 10: 181 clk = RK3399_GMAC_CLK_SEL_2_5M; 182 break; 183 case 100: 184 clk = RK3399_GMAC_CLK_SEL_25M; 185 break; 186 case 1000: 187 clk = RK3399_GMAC_CLK_SEL_125M; 188 break; 189 default: 190 debug("Unknown phy speed: %d\n", priv->phydev->speed); 191 return -EINVAL; 192 } 193 194 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 195 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); 196 197 return 0; 198 } 199 200 static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) 201 { 202 struct rv1108_grf *grf; 203 int clk, speed; 204 enum { 205 RV1108_GMAC_SPEED_MASK = BIT(2), 206 RV1108_GMAC_SPEED_10M = 0 << 2, 207 RV1108_GMAC_SPEED_100M = 1 << 2, 208 RV1108_GMAC_CLK_SEL_MASK = BIT(7), 209 RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, 210 RV1108_GMAC_CLK_SEL_25M = 1 << 7, 211 }; 212 213 switch (priv->phydev->speed) { 214 case 10: 215 clk = RV1108_GMAC_CLK_SEL_2_5M; 216 speed = RV1108_GMAC_SPEED_10M; 217 break; 218 case 100: 219 clk = RV1108_GMAC_CLK_SEL_25M; 220 speed = RV1108_GMAC_SPEED_100M; 221 break; 222 default: 223 debug("Unknown phy speed: %d\n", priv->phydev->speed); 224 return -EINVAL; 225 } 226 227 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 228 rk_clrsetreg(&grf->gmac_con0, 229 RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, 230 clk | speed); 231 232 return 0; 233 } 234 235 static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 236 { 237 struct rk3288_grf *grf; 238 239 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 240 rk_clrsetreg(&grf->soc_con1, 241 RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, 242 RK3288_GMAC_PHY_INTF_SEL_RGMII); 243 244 rk_clrsetreg(&grf->soc_con3, 245 RK3288_RXCLK_DLY_ENA_GMAC_MASK | 246 RK3288_TXCLK_DLY_ENA_GMAC_MASK | 247 RK3288_CLK_RX_DL_CFG_GMAC_MASK | 248 RK3288_CLK_TX_DL_CFG_GMAC_MASK, 249 RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | 250 RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | 251 pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | 252 pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); 253 } 254 255 static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 256 { 257 struct rk3328_grf_regs *grf; 258 enum { 259 RK3328_RMII_MODE_SHIFT = 9, 260 RK3328_RMII_MODE_MASK = BIT(9), 261 262 RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4, 263 RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 264 RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4), 265 266 RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1), 267 RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 268 RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1), 269 270 RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0), 271 RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 272 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0), 273 }; 274 enum { 275 RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, 276 RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7), 277 278 RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, 279 RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 280 }; 281 282 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 283 rk_clrsetreg(&grf->mac_con[1], 284 RK3328_RMII_MODE_MASK | 285 RK3328_GMAC_PHY_INTF_SEL_MASK | 286 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 287 RK3328_TXCLK_DLY_ENA_GMAC_MASK, 288 RK3328_GMAC_PHY_INTF_SEL_RGMII | 289 RK3328_RXCLK_DLY_ENA_GMAC_MASK | 290 RK3328_TXCLK_DLY_ENA_GMAC_ENABLE); 291 292 rk_clrsetreg(&grf->mac_con[0], 293 RK3328_CLK_RX_DL_CFG_GMAC_MASK | 294 RK3328_CLK_TX_DL_CFG_GMAC_MASK, 295 pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT | 296 pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT); 297 } 298 299 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 300 { 301 struct rk3368_grf *grf; 302 enum { 303 RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9, 304 RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9), 305 RK3368_RMII_MODE_MASK = BIT(6), 306 RK3368_RMII_MODE = BIT(6), 307 }; 308 enum { 309 RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15), 310 RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0, 311 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15), 312 RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7), 313 RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0, 314 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7), 315 RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8, 316 RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8), 317 RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0, 318 RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0), 319 }; 320 321 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 322 rk_clrsetreg(&grf->soc_con15, 323 RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK, 324 RK3368_GMAC_PHY_INTF_SEL_RGMII); 325 326 rk_clrsetreg(&grf->soc_con16, 327 RK3368_RXCLK_DLY_ENA_GMAC_MASK | 328 RK3368_TXCLK_DLY_ENA_GMAC_MASK | 329 RK3368_CLK_RX_DL_CFG_GMAC_MASK | 330 RK3368_CLK_TX_DL_CFG_GMAC_MASK, 331 RK3368_RXCLK_DLY_ENA_GMAC_ENABLE | 332 RK3368_TXCLK_DLY_ENA_GMAC_ENABLE | 333 pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT | 334 pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT); 335 } 336 337 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) 338 { 339 struct rk3399_grf_regs *grf; 340 341 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 342 343 rk_clrsetreg(&grf->soc_con5, 344 RK3399_GMAC_PHY_INTF_SEL_MASK, 345 RK3399_GMAC_PHY_INTF_SEL_RGMII); 346 347 rk_clrsetreg(&grf->soc_con6, 348 RK3399_RXCLK_DLY_ENA_GMAC_MASK | 349 RK3399_TXCLK_DLY_ENA_GMAC_MASK | 350 RK3399_CLK_RX_DL_CFG_GMAC_MASK | 351 RK3399_CLK_TX_DL_CFG_GMAC_MASK, 352 RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | 353 RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | 354 pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | 355 pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); 356 } 357 358 static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) 359 { 360 struct rv1108_grf *grf; 361 362 enum { 363 RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), 364 RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, 365 }; 366 367 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 368 rk_clrsetreg(&grf->gmac_con0, 369 RV1108_GMAC_PHY_INTF_SEL_MASK, 370 RV1108_GMAC_PHY_INTF_SEL_RMII); 371 } 372 373 static int gmac_rockchip_probe(struct udevice *dev) 374 { 375 struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); 376 struct rk_gmac_ops *ops = 377 (struct rk_gmac_ops *)dev_get_driver_data(dev); 378 struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); 379 struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; 380 struct clk clk; 381 ulong rate; 382 int ret; 383 384 ret = clk_get_by_index(dev, 0, &clk); 385 if (ret) 386 return ret; 387 388 switch (eth_pdata->phy_interface) { 389 case PHY_INTERFACE_MODE_RGMII: 390 /* 391 * If the gmac clock is from internal pll, need to set and 392 * check the return value for gmac clock at RGMII mode. If 393 * the gmac clock is from external source, the clock rate 394 * is not set, because of it is bypassed. 395 */ 396 if (!pdata->clock_input) { 397 rate = clk_set_rate(&clk, 125000000); 398 if (rate != 125000000) 399 return -EINVAL; 400 } 401 402 /* Set to RGMII mode */ 403 if (ops->set_to_rgmii) 404 ops->set_to_rgmii(pdata); 405 else 406 return -EPERM; 407 408 break; 409 case PHY_INTERFACE_MODE_RMII: 410 /* The commet is the same as RGMII mode */ 411 if (!pdata->clock_input) { 412 rate = clk_set_rate(&clk, 50000000); 413 if (rate != 50000000) 414 return -EINVAL; 415 } 416 417 /* Set to RMII mode */ 418 if (ops->set_to_rmii) 419 ops->set_to_rmii(pdata); 420 else 421 return -EPERM; 422 423 break; 424 default: 425 debug("NO interface defined!\n"); 426 return -ENXIO; 427 } 428 429 return designware_eth_probe(dev); 430 } 431 432 static int gmac_rockchip_eth_start(struct udevice *dev) 433 { 434 struct eth_pdata *pdata = dev_get_platdata(dev); 435 struct dw_eth_dev *priv = dev_get_priv(dev); 436 struct rk_gmac_ops *ops = 437 (struct rk_gmac_ops *)dev_get_driver_data(dev); 438 int ret; 439 440 ret = designware_eth_init(priv, pdata->enetaddr); 441 if (ret) 442 return ret; 443 ret = ops->fix_mac_speed(priv); 444 if (ret) 445 return ret; 446 ret = designware_eth_enable(priv); 447 if (ret) 448 return ret; 449 450 return 0; 451 } 452 453 const struct eth_ops gmac_rockchip_eth_ops = { 454 .start = gmac_rockchip_eth_start, 455 .send = designware_eth_send, 456 .recv = designware_eth_recv, 457 .free_pkt = designware_eth_free_pkt, 458 .stop = designware_eth_stop, 459 .write_hwaddr = designware_eth_write_hwaddr, 460 }; 461 462 const struct rk_gmac_ops rk3288_gmac_ops = { 463 .fix_mac_speed = rk3288_gmac_fix_mac_speed, 464 .set_to_rgmii = rk3288_gmac_set_to_rgmii, 465 }; 466 467 const struct rk_gmac_ops rk3328_gmac_ops = { 468 .fix_mac_speed = rk3328_gmac_fix_mac_speed, 469 .set_to_rgmii = rk3328_gmac_set_to_rgmii, 470 }; 471 472 const struct rk_gmac_ops rk3368_gmac_ops = { 473 .fix_mac_speed = rk3368_gmac_fix_mac_speed, 474 .set_to_rgmii = rk3368_gmac_set_to_rgmii, 475 }; 476 477 const struct rk_gmac_ops rk3399_gmac_ops = { 478 .fix_mac_speed = rk3399_gmac_fix_mac_speed, 479 .set_to_rgmii = rk3399_gmac_set_to_rgmii, 480 }; 481 482 const struct rk_gmac_ops rv1108_gmac_ops = { 483 .fix_mac_speed = rv1108_set_rmii_speed, 484 .set_to_rmii = rv1108_gmac_set_to_rmii, 485 }; 486 487 static const struct udevice_id rockchip_gmac_ids[] = { 488 { .compatible = "rockchip,rk3288-gmac", 489 .data = (ulong)&rk3288_gmac_ops }, 490 { .compatible = "rockchip,rk3328-gmac", 491 .data = (ulong)&rk3328_gmac_ops }, 492 { .compatible = "rockchip,rk3368-gmac", 493 .data = (ulong)&rk3368_gmac_ops }, 494 { .compatible = "rockchip,rk3399-gmac", 495 .data = (ulong)&rk3399_gmac_ops }, 496 { .compatible = "rockchip,rv1108-gmac", 497 .data = (ulong)&rv1108_gmac_ops }, 498 { } 499 }; 500 501 U_BOOT_DRIVER(eth_gmac_rockchip) = { 502 .name = "gmac_rockchip", 503 .id = UCLASS_ETH, 504 .of_match = rockchip_gmac_ids, 505 .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, 506 .probe = gmac_rockchip_probe, 507 .ops = &gmac_rockchip_eth_ops, 508 .priv_auto_alloc_size = sizeof(struct dw_eth_dev), 509 .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), 510 .flags = DM_FLAG_ALLOC_PRIV_DMA, 511 }; 512