1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 14 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 15 #define RK_FUNC_GPIO 0 16 #define MAX_ROCKCHIP_PINS_ENTRIES 30 17 18 enum rockchip_pinctrl_type { 19 PX30, 20 RV1108, 21 RK2928, 22 RK3066B, 23 RK3128, 24 RK3188, 25 RK3288, 26 RK3308, 27 RK3368, 28 RK3399, 29 }; 30 31 /** 32 * Encode variants of iomux registers into a type variable 33 */ 34 #define IOMUX_GPIO_ONLY BIT(0) 35 #define IOMUX_WIDTH_4BIT BIT(1) 36 #define IOMUX_SOURCE_PMU BIT(2) 37 #define IOMUX_UNROUTED BIT(3) 38 #define IOMUX_WIDTH_3BIT BIT(4) 39 #define IOMUX_8WIDTH_2BIT BIT(5) 40 #define IOMUX_UNMASKED BIT(6) 41 42 /** 43 * @type: iomux variant using IOMUX_* constants 44 * @offset: if initialized to -1 it will be autocalculated, by specifying 45 * an initial offset value the relevant source offset can be reset 46 * to a new value for autocalculating the following iomux registers. 47 */ 48 struct rockchip_iomux { 49 int type; 50 int offset; 51 }; 52 53 /** 54 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 55 */ 56 enum rockchip_pin_drv_type { 57 DRV_TYPE_IO_DEFAULT = 0, 58 DRV_TYPE_IO_1V8_OR_3V0, 59 DRV_TYPE_IO_1V8_ONLY, 60 DRV_TYPE_IO_1V8_3V0_AUTO, 61 DRV_TYPE_IO_3V3_ONLY, 62 DRV_TYPE_MAX 63 }; 64 65 /** 66 * enum type index corresponding to rockchip_pull_list arrays index. 67 */ 68 enum rockchip_pin_pull_type { 69 PULL_TYPE_IO_DEFAULT = 0, 70 PULL_TYPE_IO_1V8_ONLY, 71 PULL_TYPE_MAX 72 }; 73 74 /** 75 * @drv_type: drive strength variant using rockchip_perpin_drv_type 76 * @offset: if initialized to -1 it will be autocalculated, by specifying 77 * an initial offset value the relevant source offset can be reset 78 * to a new value for autocalculating the following drive strength 79 * registers. if used chips own cal_drv func instead to calculate 80 * registers offset, the variant could be ignored. 81 */ 82 struct rockchip_drv { 83 enum rockchip_pin_drv_type drv_type; 84 int offset; 85 }; 86 87 /** 88 * @priv: common pinctrl private basedata 89 * @pin_base: first pin number 90 * @nr_pins: number of pins in this bank 91 * @name: name of the bank 92 * @bank_num: number of the bank, to account for holes 93 * @iomux: array describing the 4 iomux sources of the bank 94 * @drv: array describing the 4 drive strength sources of the bank 95 * @pull_type: array describing the 4 pull type sources of the bank 96 * @recalced_mask: bits describing the mux recalced pins of per bank 97 * @route_mask: bits describing the routing pins of per bank 98 */ 99 struct rockchip_pin_bank { 100 struct rockchip_pinctrl_priv *priv; 101 u32 pin_base; 102 u8 nr_pins; 103 char *name; 104 u8 bank_num; 105 struct rockchip_iomux iomux[4]; 106 struct rockchip_drv drv[4]; 107 enum rockchip_pin_pull_type pull_type[4]; 108 u32 recalced_mask; 109 u32 route_mask; 110 }; 111 112 #define PIN_BANK(id, pins, label) \ 113 { \ 114 .bank_num = id, \ 115 .nr_pins = pins, \ 116 .name = label, \ 117 .iomux = { \ 118 { .offset = -1 }, \ 119 { .offset = -1 }, \ 120 { .offset = -1 }, \ 121 { .offset = -1 }, \ 122 }, \ 123 } 124 125 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 126 { \ 127 .bank_num = id, \ 128 .nr_pins = pins, \ 129 .name = label, \ 130 .iomux = { \ 131 { .type = iom0, .offset = -1 }, \ 132 { .type = iom1, .offset = -1 }, \ 133 { .type = iom2, .offset = -1 }, \ 134 { .type = iom3, .offset = -1 }, \ 135 }, \ 136 } 137 138 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 139 { \ 140 .bank_num = id, \ 141 .nr_pins = pins, \ 142 .name = label, \ 143 .iomux = { \ 144 { .offset = -1 }, \ 145 { .offset = -1 }, \ 146 { .offset = -1 }, \ 147 { .offset = -1 }, \ 148 }, \ 149 .drv = { \ 150 { .drv_type = type0, .offset = -1 }, \ 151 { .drv_type = type1, .offset = -1 }, \ 152 { .drv_type = type2, .offset = -1 }, \ 153 { .drv_type = type3, .offset = -1 }, \ 154 }, \ 155 } 156 157 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 158 drv2, drv3, pull0, pull1, \ 159 pull2, pull3) \ 160 { \ 161 .bank_num = id, \ 162 .nr_pins = pins, \ 163 .name = label, \ 164 .iomux = { \ 165 { .offset = -1 }, \ 166 { .offset = -1 }, \ 167 { .offset = -1 }, \ 168 { .offset = -1 }, \ 169 }, \ 170 .drv = { \ 171 { .drv_type = drv0, .offset = -1 }, \ 172 { .drv_type = drv1, .offset = -1 }, \ 173 { .drv_type = drv2, .offset = -1 }, \ 174 { .drv_type = drv3, .offset = -1 }, \ 175 }, \ 176 .pull_type[0] = pull0, \ 177 .pull_type[1] = pull1, \ 178 .pull_type[2] = pull2, \ 179 .pull_type[3] = pull3, \ 180 } 181 182 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 183 iom2, iom3, drv0, drv1, drv2, \ 184 drv3, offset0, offset1, \ 185 offset2, offset3) \ 186 { \ 187 .bank_num = id, \ 188 .nr_pins = pins, \ 189 .name = label, \ 190 .iomux = { \ 191 { .type = iom0, .offset = -1 }, \ 192 { .type = iom1, .offset = -1 }, \ 193 { .type = iom2, .offset = -1 }, \ 194 { .type = iom3, .offset = -1 }, \ 195 }, \ 196 .drv = { \ 197 { .drv_type = drv0, .offset = offset0 }, \ 198 { .drv_type = drv1, .offset = offset1 }, \ 199 { .drv_type = drv2, .offset = offset2 }, \ 200 { .drv_type = drv3, .offset = offset3 }, \ 201 }, \ 202 } 203 204 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 205 label, iom0, iom1, iom2, \ 206 iom3, drv0, drv1, drv2, \ 207 drv3, offset0, offset1, \ 208 offset2, offset3, pull0, \ 209 pull1, pull2, pull3) \ 210 { \ 211 .bank_num = id, \ 212 .nr_pins = pins, \ 213 .name = label, \ 214 .iomux = { \ 215 { .type = iom0, .offset = -1 }, \ 216 { .type = iom1, .offset = -1 }, \ 217 { .type = iom2, .offset = -1 }, \ 218 { .type = iom3, .offset = -1 }, \ 219 }, \ 220 .drv = { \ 221 { .drv_type = drv0, .offset = offset0 }, \ 222 { .drv_type = drv1, .offset = offset1 }, \ 223 { .drv_type = drv2, .offset = offset2 }, \ 224 { .drv_type = drv3, .offset = offset3 }, \ 225 }, \ 226 .pull_type[0] = pull0, \ 227 .pull_type[1] = pull1, \ 228 .pull_type[2] = pull2, \ 229 .pull_type[3] = pull3, \ 230 } 231 232 /** 233 * struct rockchip_mux_recalced_data: represent a pin iomux data. 234 * @num: bank number. 235 * @pin: pin number. 236 * @bit: index at register. 237 * @reg: register offset. 238 * @mask: mask bit 239 */ 240 struct rockchip_mux_recalced_data { 241 u8 num; 242 u8 pin; 243 u32 reg; 244 u8 bit; 245 u8 mask; 246 }; 247 248 /** 249 * struct rockchip_mux_recalced_data: represent a pin iomux data. 250 * @bank_num: bank number. 251 * @pin: index at register or used to calc index. 252 * @func: the min pin. 253 * @route_offset: the max pin. 254 * @route_val: the register offset. 255 */ 256 struct rockchip_mux_route_data { 257 u8 bank_num; 258 u8 pin; 259 u8 func; 260 u32 route_offset; 261 u32 route_val; 262 }; 263 264 /** 265 */ 266 struct rockchip_pin_ctrl { 267 struct rockchip_pin_bank *pin_banks; 268 u32 nr_banks; 269 u32 nr_pins; 270 char *label; 271 enum rockchip_pinctrl_type type; 272 int grf_mux_offset; 273 int pmu_mux_offset; 274 int grf_drv_offset; 275 int pmu_drv_offset; 276 struct rockchip_mux_recalced_data *iomux_recalced; 277 u32 niomux_recalced; 278 struct rockchip_mux_route_data *iomux_routes; 279 u32 niomux_routes; 280 281 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 282 int pin_num, struct regmap **regmap, 283 int *reg, u8 *bit); 284 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 285 int pin_num, struct regmap **regmap, 286 int *reg, u8 *bit); 287 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 288 int pin_num, struct regmap **regmap, 289 int *reg, u8 *bit); 290 }; 291 292 /** 293 */ 294 struct rockchip_pinctrl_priv { 295 struct rockchip_pin_ctrl *ctrl; 296 struct regmap *regmap_base; 297 struct regmap *regmap_pmu; 298 299 }; 300 301 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 302 { 303 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 304 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 305 306 if (bank >= ctrl->nr_banks) { 307 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 308 return -EINVAL; 309 } 310 311 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 312 debug("pin conf pin %d >= %d\n", pin, 313 MAX_ROCKCHIP_GPIO_PER_BANK); 314 return -EINVAL; 315 } 316 317 return 0; 318 } 319 320 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 321 { 322 .num = 1, 323 .pin = 0, 324 .reg = 0x418, 325 .bit = 0, 326 .mask = 0x3 327 }, { 328 .num = 1, 329 .pin = 1, 330 .reg = 0x418, 331 .bit = 2, 332 .mask = 0x3 333 }, { 334 .num = 1, 335 .pin = 2, 336 .reg = 0x418, 337 .bit = 4, 338 .mask = 0x3 339 }, { 340 .num = 1, 341 .pin = 3, 342 .reg = 0x418, 343 .bit = 6, 344 .mask = 0x3 345 }, { 346 .num = 1, 347 .pin = 4, 348 .reg = 0x418, 349 .bit = 8, 350 .mask = 0x3 351 }, { 352 .num = 1, 353 .pin = 5, 354 .reg = 0x418, 355 .bit = 10, 356 .mask = 0x3 357 }, { 358 .num = 1, 359 .pin = 6, 360 .reg = 0x418, 361 .bit = 12, 362 .mask = 0x3 363 }, { 364 .num = 1, 365 .pin = 7, 366 .reg = 0x418, 367 .bit = 14, 368 .mask = 0x3 369 }, { 370 .num = 1, 371 .pin = 8, 372 .reg = 0x41c, 373 .bit = 0, 374 .mask = 0x3 375 }, { 376 .num = 1, 377 .pin = 9, 378 .reg = 0x41c, 379 .bit = 2, 380 .mask = 0x3 381 }, 382 }; 383 384 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 385 { 386 .num = 2, 387 .pin = 20, 388 .reg = 0xe8, 389 .bit = 0, 390 .mask = 0x7 391 }, { 392 .num = 2, 393 .pin = 21, 394 .reg = 0xe8, 395 .bit = 4, 396 .mask = 0x7 397 }, { 398 .num = 2, 399 .pin = 22, 400 .reg = 0xe8, 401 .bit = 8, 402 .mask = 0x7 403 }, { 404 .num = 2, 405 .pin = 23, 406 .reg = 0xe8, 407 .bit = 12, 408 .mask = 0x7 409 }, { 410 .num = 2, 411 .pin = 24, 412 .reg = 0xd4, 413 .bit = 12, 414 .mask = 0x7 415 }, 416 }; 417 418 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 419 { 420 .num = 1, 421 .pin = 14, 422 .reg = 0x28, 423 .bit = 12, 424 .mask = 0x7 425 }, { 426 .num = 1, 427 .pin = 15, 428 .reg = 0x2c, 429 .bit = 0, 430 .mask = 0x3 431 }, { 432 .num = 1, 433 .pin = 18, 434 .reg = 0x30, 435 .bit = 4, 436 .mask = 0x7 437 }, { 438 .num = 1, 439 .pin = 19, 440 .reg = 0x30, 441 .bit = 8, 442 .mask = 0x7 443 }, { 444 .num = 1, 445 .pin = 20, 446 .reg = 0x30, 447 .bit = 12, 448 .mask = 0x7 449 }, { 450 .num = 1, 451 .pin = 21, 452 .reg = 0x34, 453 .bit = 0, 454 .mask = 0x7 455 }, { 456 .num = 1, 457 .pin = 22, 458 .reg = 0x34, 459 .bit = 4, 460 .mask = 0x7 461 }, { 462 .num = 1, 463 .pin = 23, 464 .reg = 0x34, 465 .bit = 8, 466 .mask = 0x7 467 }, { 468 .num = 3, 469 .pin = 12, 470 .reg = 0x68, 471 .bit = 8, 472 .mask = 0x7 473 }, { 474 .num = 3, 475 .pin = 13, 476 .reg = 0x68, 477 .bit = 12, 478 .mask = 0x7 479 }, 480 }; 481 482 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 483 { 484 .num = 2, 485 .pin = 12, 486 .reg = 0x24, 487 .bit = 8, 488 .mask = 0x3 489 }, { 490 .num = 2, 491 .pin = 15, 492 .reg = 0x28, 493 .bit = 0, 494 .mask = 0x7 495 }, { 496 .num = 2, 497 .pin = 23, 498 .reg = 0x30, 499 .bit = 14, 500 .mask = 0x3 501 }, 502 }; 503 504 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 505 int *reg, u8 *bit, int *mask) 506 { 507 struct rockchip_pinctrl_priv *priv = bank->priv; 508 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 509 struct rockchip_mux_recalced_data *data; 510 int i; 511 512 for (i = 0; i < ctrl->niomux_recalced; i++) { 513 data = &ctrl->iomux_recalced[i]; 514 if (data->num == bank->bank_num && 515 data->pin == pin) 516 break; 517 } 518 519 if (i >= ctrl->niomux_recalced) 520 return; 521 522 *reg = data->reg; 523 *mask = data->mask; 524 *bit = data->bit; 525 } 526 527 static struct rockchip_mux_route_data px30_mux_route_data[] = { 528 { 529 /* cif-d2m0 */ 530 .bank_num = 2, 531 .pin = 0, 532 .func = 1, 533 .route_offset = 0x184, 534 .route_val = BIT(16 + 7), 535 }, { 536 /* cif-d2m1 */ 537 .bank_num = 3, 538 .pin = 3, 539 .func = 3, 540 .route_offset = 0x184, 541 .route_val = BIT(16 + 7) | BIT(7), 542 }, { 543 /* pdm-m0 */ 544 .bank_num = 3, 545 .pin = 22, 546 .func = 2, 547 .route_offset = 0x184, 548 .route_val = BIT(16 + 8), 549 }, { 550 /* pdm-m1 */ 551 .bank_num = 2, 552 .pin = 22, 553 .func = 1, 554 .route_offset = 0x184, 555 .route_val = BIT(16 + 8) | BIT(8), 556 }, { 557 /* uart2-rxm0 */ 558 .bank_num = 1, 559 .pin = 27, 560 .func = 2, 561 .route_offset = 0x184, 562 .route_val = BIT(16 + 10), 563 }, { 564 /* uart2-rxm1 */ 565 .bank_num = 2, 566 .pin = 14, 567 .func = 2, 568 .route_offset = 0x184, 569 .route_val = BIT(16 + 10) | BIT(10), 570 }, { 571 /* uart3-rxm0 */ 572 .bank_num = 0, 573 .pin = 17, 574 .func = 2, 575 .route_offset = 0x184, 576 .route_val = BIT(16 + 9), 577 }, { 578 /* uart3-rxm1 */ 579 .bank_num = 1, 580 .pin = 15, 581 .func = 2, 582 .route_offset = 0x184, 583 .route_val = BIT(16 + 9) | BIT(9), 584 }, 585 }; 586 587 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 588 { 589 /* spi-0 */ 590 .bank_num = 1, 591 .pin = 10, 592 .func = 1, 593 .route_offset = 0x144, 594 .route_val = BIT(16 + 3) | BIT(16 + 4), 595 }, { 596 /* spi-1 */ 597 .bank_num = 1, 598 .pin = 27, 599 .func = 3, 600 .route_offset = 0x144, 601 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 602 }, { 603 /* spi-2 */ 604 .bank_num = 0, 605 .pin = 13, 606 .func = 2, 607 .route_offset = 0x144, 608 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 609 }, { 610 /* i2s-0 */ 611 .bank_num = 1, 612 .pin = 5, 613 .func = 1, 614 .route_offset = 0x144, 615 .route_val = BIT(16 + 5), 616 }, { 617 /* i2s-1 */ 618 .bank_num = 0, 619 .pin = 14, 620 .func = 1, 621 .route_offset = 0x144, 622 .route_val = BIT(16 + 5) | BIT(5), 623 }, { 624 /* emmc-0 */ 625 .bank_num = 1, 626 .pin = 22, 627 .func = 2, 628 .route_offset = 0x144, 629 .route_val = BIT(16 + 6), 630 }, { 631 /* emmc-1 */ 632 .bank_num = 2, 633 .pin = 4, 634 .func = 2, 635 .route_offset = 0x144, 636 .route_val = BIT(16 + 6) | BIT(6), 637 }, 638 }; 639 640 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 641 { 642 /* pwm0-0 */ 643 .bank_num = 0, 644 .pin = 26, 645 .func = 1, 646 .route_offset = 0x50, 647 .route_val = BIT(16), 648 }, { 649 /* pwm0-1 */ 650 .bank_num = 3, 651 .pin = 21, 652 .func = 1, 653 .route_offset = 0x50, 654 .route_val = BIT(16) | BIT(0), 655 }, { 656 /* pwm1-0 */ 657 .bank_num = 0, 658 .pin = 27, 659 .func = 1, 660 .route_offset = 0x50, 661 .route_val = BIT(16 + 1), 662 }, { 663 /* pwm1-1 */ 664 .bank_num = 0, 665 .pin = 30, 666 .func = 2, 667 .route_offset = 0x50, 668 .route_val = BIT(16 + 1) | BIT(1), 669 }, { 670 /* pwm2-0 */ 671 .bank_num = 0, 672 .pin = 28, 673 .func = 1, 674 .route_offset = 0x50, 675 .route_val = BIT(16 + 2), 676 }, { 677 /* pwm2-1 */ 678 .bank_num = 1, 679 .pin = 12, 680 .func = 2, 681 .route_offset = 0x50, 682 .route_val = BIT(16 + 2) | BIT(2), 683 }, { 684 /* pwm3-0 */ 685 .bank_num = 3, 686 .pin = 26, 687 .func = 1, 688 .route_offset = 0x50, 689 .route_val = BIT(16 + 3), 690 }, { 691 /* pwm3-1 */ 692 .bank_num = 1, 693 .pin = 11, 694 .func = 2, 695 .route_offset = 0x50, 696 .route_val = BIT(16 + 3) | BIT(3), 697 }, { 698 /* sdio-0_d0 */ 699 .bank_num = 1, 700 .pin = 1, 701 .func = 1, 702 .route_offset = 0x50, 703 .route_val = BIT(16 + 4), 704 }, { 705 /* sdio-1_d0 */ 706 .bank_num = 3, 707 .pin = 2, 708 .func = 1, 709 .route_offset = 0x50, 710 .route_val = BIT(16 + 4) | BIT(4), 711 }, { 712 /* spi-0_rx */ 713 .bank_num = 0, 714 .pin = 13, 715 .func = 2, 716 .route_offset = 0x50, 717 .route_val = BIT(16 + 5), 718 }, { 719 /* spi-1_rx */ 720 .bank_num = 2, 721 .pin = 0, 722 .func = 2, 723 .route_offset = 0x50, 724 .route_val = BIT(16 + 5) | BIT(5), 725 }, { 726 /* emmc-0_cmd */ 727 .bank_num = 1, 728 .pin = 22, 729 .func = 2, 730 .route_offset = 0x50, 731 .route_val = BIT(16 + 7), 732 }, { 733 /* emmc-1_cmd */ 734 .bank_num = 2, 735 .pin = 4, 736 .func = 2, 737 .route_offset = 0x50, 738 .route_val = BIT(16 + 7) | BIT(7), 739 }, { 740 /* uart2-0_rx */ 741 .bank_num = 1, 742 .pin = 19, 743 .func = 2, 744 .route_offset = 0x50, 745 .route_val = BIT(16 + 8), 746 }, { 747 /* uart2-1_rx */ 748 .bank_num = 1, 749 .pin = 10, 750 .func = 2, 751 .route_offset = 0x50, 752 .route_val = BIT(16 + 8) | BIT(8), 753 }, { 754 /* uart1-0_rx */ 755 .bank_num = 1, 756 .pin = 10, 757 .func = 1, 758 .route_offset = 0x50, 759 .route_val = BIT(16 + 11), 760 }, { 761 /* uart1-1_rx */ 762 .bank_num = 3, 763 .pin = 13, 764 .func = 1, 765 .route_offset = 0x50, 766 .route_val = BIT(16 + 11) | BIT(11), 767 }, 768 }; 769 770 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 771 { 772 /* edphdmi_cecinoutt1 */ 773 .bank_num = 7, 774 .pin = 16, 775 .func = 2, 776 .route_offset = 0x264, 777 .route_val = BIT(16 + 12) | BIT(12), 778 }, { 779 /* edphdmi_cecinout */ 780 .bank_num = 7, 781 .pin = 23, 782 .func = 4, 783 .route_offset = 0x264, 784 .route_val = BIT(16 + 12), 785 }, 786 }; 787 788 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 789 { 790 /* uart2_rxm0 */ 791 .bank_num = 1, 792 .pin = 22, 793 .func = 2, 794 .route_offset = 0x314, 795 .route_val = BIT(16 + 2) | BIT(16 + 3), 796 }, { 797 /* uart2_rxm1 */ 798 .bank_num = 4, 799 .pin = 26, 800 .func = 2, 801 .route_offset = 0x314, 802 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 803 }, { 804 /* i2c3_sdam0 */ 805 .bank_num = 0, 806 .pin = 23, 807 .func = 2, 808 .route_offset = 0x314, 809 .route_val = BIT(16 + 4), 810 }, { 811 /* i2c3_sdam1 */ 812 .bank_num = 3, 813 .pin = 12, 814 .func = 2, 815 .route_offset = 0x314, 816 .route_val = BIT(16 + 4) | BIT(4), 817 }, 818 }; 819 820 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 821 { 822 /* uart2dbg_rxm0 */ 823 .bank_num = 1, 824 .pin = 1, 825 .func = 2, 826 .route_offset = 0x50, 827 .route_val = BIT(16) | BIT(16 + 1), 828 }, { 829 /* uart2dbg_rxm1 */ 830 .bank_num = 2, 831 .pin = 1, 832 .func = 1, 833 .route_offset = 0x50, 834 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 835 }, { 836 /* gmac-m1_rxd0 */ 837 .bank_num = 1, 838 .pin = 11, 839 .func = 2, 840 .route_offset = 0x50, 841 .route_val = BIT(16 + 2) | BIT(2), 842 }, { 843 /* gmac-m1-optimized_rxd3 */ 844 .bank_num = 1, 845 .pin = 14, 846 .func = 2, 847 .route_offset = 0x50, 848 .route_val = BIT(16 + 10) | BIT(10), 849 }, { 850 /* pdm_sdi0m0 */ 851 .bank_num = 2, 852 .pin = 19, 853 .func = 2, 854 .route_offset = 0x50, 855 .route_val = BIT(16 + 3), 856 }, { 857 /* pdm_sdi0m1 */ 858 .bank_num = 1, 859 .pin = 23, 860 .func = 3, 861 .route_offset = 0x50, 862 .route_val = BIT(16 + 3) | BIT(3), 863 }, { 864 /* spi_rxdm2 */ 865 .bank_num = 3, 866 .pin = 2, 867 .func = 4, 868 .route_offset = 0x50, 869 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 870 }, { 871 /* i2s2_sdim0 */ 872 .bank_num = 1, 873 .pin = 24, 874 .func = 1, 875 .route_offset = 0x50, 876 .route_val = BIT(16 + 6), 877 }, { 878 /* i2s2_sdim1 */ 879 .bank_num = 3, 880 .pin = 2, 881 .func = 6, 882 .route_offset = 0x50, 883 .route_val = BIT(16 + 6) | BIT(6), 884 }, { 885 /* card_iom1 */ 886 .bank_num = 2, 887 .pin = 22, 888 .func = 3, 889 .route_offset = 0x50, 890 .route_val = BIT(16 + 7) | BIT(7), 891 }, { 892 /* tsp_d5m1 */ 893 .bank_num = 2, 894 .pin = 16, 895 .func = 3, 896 .route_offset = 0x50, 897 .route_val = BIT(16 + 8) | BIT(8), 898 }, { 899 /* cif_data5m1 */ 900 .bank_num = 2, 901 .pin = 16, 902 .func = 4, 903 .route_offset = 0x50, 904 .route_val = BIT(16 + 9) | BIT(9), 905 }, 906 }; 907 908 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 909 { 910 /* uart2dbga_rx */ 911 .bank_num = 4, 912 .pin = 8, 913 .func = 2, 914 .route_offset = 0xe21c, 915 .route_val = BIT(16 + 10) | BIT(16 + 11), 916 }, { 917 /* uart2dbgb_rx */ 918 .bank_num = 4, 919 .pin = 16, 920 .func = 2, 921 .route_offset = 0xe21c, 922 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 923 }, { 924 /* uart2dbgc_rx */ 925 .bank_num = 4, 926 .pin = 19, 927 .func = 1, 928 .route_offset = 0xe21c, 929 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 930 }, { 931 /* pcie_clkreqn */ 932 .bank_num = 2, 933 .pin = 26, 934 .func = 2, 935 .route_offset = 0xe21c, 936 .route_val = BIT(16 + 14), 937 }, { 938 /* pcie_clkreqnb */ 939 .bank_num = 4, 940 .pin = 24, 941 .func = 1, 942 .route_offset = 0xe21c, 943 .route_val = BIT(16 + 14) | BIT(14), 944 }, 945 }; 946 947 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 948 int mux, u32 *reg, u32 *value) 949 { 950 struct rockchip_pinctrl_priv *priv = bank->priv; 951 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 952 struct rockchip_mux_route_data *data; 953 int i; 954 955 for (i = 0; i < ctrl->niomux_routes; i++) { 956 data = &ctrl->iomux_routes[i]; 957 if ((data->bank_num == bank->bank_num) && 958 (data->pin == pin) && (data->func == mux)) 959 break; 960 } 961 962 if (i >= ctrl->niomux_routes) 963 return false; 964 965 *reg = data->route_offset; 966 *value = data->route_val; 967 968 return true; 969 } 970 971 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 972 { 973 struct rockchip_pinctrl_priv *priv = bank->priv; 974 int iomux_num = (pin / 8); 975 struct regmap *regmap; 976 unsigned int val; 977 int reg, ret, mask, mux_type; 978 u8 bit; 979 980 if (iomux_num > 3) 981 return -EINVAL; 982 983 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 984 debug("pin %d is unrouted\n", pin); 985 return -EINVAL; 986 } 987 988 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 989 return RK_FUNC_GPIO; 990 991 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 992 ? priv->regmap_pmu : priv->regmap_base; 993 994 /* get basic quadrupel of mux registers and the correct reg inside */ 995 mux_type = bank->iomux[iomux_num].type; 996 reg = bank->iomux[iomux_num].offset; 997 if (mux_type & IOMUX_WIDTH_4BIT) { 998 if ((pin % 8) >= 4) 999 reg += 0x4; 1000 bit = (pin % 4) * 4; 1001 mask = 0xf; 1002 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1003 if ((pin % 8) >= 5) 1004 reg += 0x4; 1005 bit = (pin % 8 % 5) * 3; 1006 mask = 0x7; 1007 } else { 1008 bit = (pin % 8) * 2; 1009 mask = 0x3; 1010 } 1011 1012 if (bank->recalced_mask & BIT(pin)) 1013 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1014 1015 ret = regmap_read(regmap, reg, &val); 1016 if (ret) 1017 return ret; 1018 1019 return ((val >> bit) & mask); 1020 } 1021 1022 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1023 int index) 1024 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1025 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1026 1027 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1028 } 1029 1030 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1031 int pin, int mux) 1032 { 1033 int iomux_num = (pin / 8); 1034 1035 if (iomux_num > 3) 1036 return -EINVAL; 1037 1038 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1039 debug("pin %d is unrouted\n", pin); 1040 return -EINVAL; 1041 } 1042 1043 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1044 if (mux != IOMUX_GPIO_ONLY) { 1045 debug("pin %d only supports a gpio mux\n", pin); 1046 return -ENOTSUPP; 1047 } 1048 } 1049 1050 return 0; 1051 } 1052 1053 /* 1054 * Set a new mux function for a pin. 1055 * 1056 * The register is divided into the upper and lower 16 bit. When changing 1057 * a value, the previous register value is not read and changed. Instead 1058 * it seems the changed bits are marked in the upper 16 bit, while the 1059 * changed value gets set in the same offset in the lower 16 bit. 1060 * All pin settings seem to be 2 bit wide in both the upper and lower 1061 * parts. 1062 * @bank: pin bank to change 1063 * @pin: pin to change 1064 * @mux: new mux function to set 1065 */ 1066 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1067 { 1068 struct rockchip_pinctrl_priv *priv = bank->priv; 1069 int iomux_num = (pin / 8); 1070 struct regmap *regmap; 1071 int reg, ret, mask, mux_type; 1072 u8 bit; 1073 u32 data, route_reg, route_val; 1074 1075 ret = rockchip_verify_mux(bank, pin, mux); 1076 if (ret < 0) 1077 return ret; 1078 1079 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1080 return 0; 1081 1082 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1083 1084 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1085 ? priv->regmap_pmu : priv->regmap_base; 1086 1087 /* get basic quadrupel of mux registers and the correct reg inside */ 1088 mux_type = bank->iomux[iomux_num].type; 1089 reg = bank->iomux[iomux_num].offset; 1090 if (mux_type & IOMUX_WIDTH_4BIT) { 1091 if ((pin % 8) >= 4) 1092 reg += 0x4; 1093 bit = (pin % 4) * 4; 1094 mask = 0xf; 1095 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1096 if ((pin % 8) >= 5) 1097 reg += 0x4; 1098 bit = (pin % 8 % 5) * 3; 1099 mask = 0x7; 1100 } else { 1101 bit = (pin % 8) * 2; 1102 mask = 0x3; 1103 } 1104 1105 if (bank->recalced_mask & BIT(pin)) 1106 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1107 1108 if (bank->route_mask & BIT(pin)) { 1109 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1110 &route_val)) { 1111 ret = regmap_write(regmap, route_reg, route_val); 1112 if (ret) 1113 return ret; 1114 } 1115 } 1116 1117 if (mux_type & IOMUX_UNMASKED) 1118 regmap_read(regmap, reg, &data); 1119 else 1120 data = (mask << (bit + 16)); 1121 1122 data |= (mux & mask) << bit; 1123 ret = regmap_write(regmap, reg, data); 1124 1125 return ret; 1126 } 1127 1128 #define PX30_PULL_PMU_OFFSET 0x10 1129 #define PX30_PULL_GRF_OFFSET 0x60 1130 #define PX30_PULL_BITS_PER_PIN 2 1131 #define PX30_PULL_PINS_PER_REG 8 1132 #define PX30_PULL_BANK_STRIDE 16 1133 1134 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1135 int pin_num, struct regmap **regmap, 1136 int *reg, u8 *bit) 1137 { 1138 struct rockchip_pinctrl_priv *priv = bank->priv; 1139 1140 /* The first 32 pins of the first bank are located in PMU */ 1141 if (bank->bank_num == 0) { 1142 *regmap = priv->regmap_pmu; 1143 *reg = PX30_PULL_PMU_OFFSET; 1144 } else { 1145 *regmap = priv->regmap_base; 1146 *reg = PX30_PULL_GRF_OFFSET; 1147 1148 /* correct the offset, as we're starting with the 2nd bank */ 1149 *reg -= 0x10; 1150 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1151 } 1152 1153 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1154 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1155 *bit *= PX30_PULL_BITS_PER_PIN; 1156 } 1157 1158 #define PX30_DRV_PMU_OFFSET 0x20 1159 #define PX30_DRV_GRF_OFFSET 0xf0 1160 #define PX30_DRV_BITS_PER_PIN 2 1161 #define PX30_DRV_PINS_PER_REG 8 1162 #define PX30_DRV_BANK_STRIDE 16 1163 1164 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1165 int pin_num, struct regmap **regmap, 1166 int *reg, u8 *bit) 1167 { 1168 struct rockchip_pinctrl_priv *priv = bank->priv; 1169 1170 /* The first 32 pins of the first bank are located in PMU */ 1171 if (bank->bank_num == 0) { 1172 *regmap = priv->regmap_pmu; 1173 *reg = PX30_DRV_PMU_OFFSET; 1174 } else { 1175 *regmap = priv->regmap_base; 1176 *reg = PX30_DRV_GRF_OFFSET; 1177 1178 /* correct the offset, as we're starting with the 2nd bank */ 1179 *reg -= 0x10; 1180 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1181 } 1182 1183 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1184 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1185 *bit *= PX30_DRV_BITS_PER_PIN; 1186 } 1187 1188 #define PX30_SCHMITT_PMU_OFFSET 0x38 1189 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1190 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1191 #define PX30_SCHMITT_BANK_STRIDE 16 1192 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1193 1194 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1195 int pin_num, 1196 struct regmap **regmap, 1197 int *reg, u8 *bit) 1198 { 1199 struct rockchip_pinctrl_priv *priv = bank->priv; 1200 int pins_per_reg; 1201 1202 if (bank->bank_num == 0) { 1203 *regmap = priv->regmap_pmu; 1204 *reg = PX30_SCHMITT_PMU_OFFSET; 1205 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1206 } else { 1207 *regmap = priv->regmap_base; 1208 *reg = PX30_SCHMITT_GRF_OFFSET; 1209 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1210 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1211 } 1212 *reg += ((pin_num / pins_per_reg) * 4); 1213 *bit = pin_num % pins_per_reg; 1214 1215 return 0; 1216 } 1217 1218 #define RV1108_PULL_PMU_OFFSET 0x10 1219 #define RV1108_PULL_OFFSET 0x110 1220 #define RV1108_PULL_PINS_PER_REG 8 1221 #define RV1108_PULL_BITS_PER_PIN 2 1222 #define RV1108_PULL_BANK_STRIDE 16 1223 1224 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1225 int pin_num, struct regmap **regmap, 1226 int *reg, u8 *bit) 1227 { 1228 struct rockchip_pinctrl_priv *priv = bank->priv; 1229 1230 /* The first 24 pins of the first bank are located in PMU */ 1231 if (bank->bank_num == 0) { 1232 *regmap = priv->regmap_pmu; 1233 *reg = RV1108_PULL_PMU_OFFSET; 1234 } else { 1235 *reg = RV1108_PULL_OFFSET; 1236 *regmap = priv->regmap_base; 1237 /* correct the offset, as we're starting with the 2nd bank */ 1238 *reg -= 0x10; 1239 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1240 } 1241 1242 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1243 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1244 *bit *= RV1108_PULL_BITS_PER_PIN; 1245 } 1246 1247 #define RV1108_DRV_PMU_OFFSET 0x20 1248 #define RV1108_DRV_GRF_OFFSET 0x210 1249 #define RV1108_DRV_BITS_PER_PIN 2 1250 #define RV1108_DRV_PINS_PER_REG 8 1251 #define RV1108_DRV_BANK_STRIDE 16 1252 1253 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1254 int pin_num, struct regmap **regmap, 1255 int *reg, u8 *bit) 1256 { 1257 struct rockchip_pinctrl_priv *priv = bank->priv; 1258 1259 /* The first 24 pins of the first bank are located in PMU */ 1260 if (bank->bank_num == 0) { 1261 *regmap = priv->regmap_pmu; 1262 *reg = RV1108_DRV_PMU_OFFSET; 1263 } else { 1264 *regmap = priv->regmap_base; 1265 *reg = RV1108_DRV_GRF_OFFSET; 1266 1267 /* correct the offset, as we're starting with the 2nd bank */ 1268 *reg -= 0x10; 1269 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1270 } 1271 1272 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1273 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1274 *bit *= RV1108_DRV_BITS_PER_PIN; 1275 } 1276 1277 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1278 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1279 #define RV1108_SCHMITT_BANK_STRIDE 8 1280 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1281 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1282 1283 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1284 int pin_num, 1285 struct regmap **regmap, 1286 int *reg, u8 *bit) 1287 { 1288 struct rockchip_pinctrl_priv *priv = bank->priv; 1289 int pins_per_reg; 1290 1291 if (bank->bank_num == 0) { 1292 *regmap = priv->regmap_pmu; 1293 *reg = RV1108_SCHMITT_PMU_OFFSET; 1294 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1295 } else { 1296 *regmap = priv->regmap_base; 1297 *reg = RV1108_SCHMITT_GRF_OFFSET; 1298 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1299 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1300 } 1301 *reg += ((pin_num / pins_per_reg) * 4); 1302 *bit = pin_num % pins_per_reg; 1303 1304 return 0; 1305 } 1306 1307 #define RK2928_PULL_OFFSET 0x118 1308 #define RK2928_PULL_PINS_PER_REG 16 1309 #define RK2928_PULL_BANK_STRIDE 8 1310 1311 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1312 int pin_num, struct regmap **regmap, 1313 int *reg, u8 *bit) 1314 { 1315 struct rockchip_pinctrl_priv *priv = bank->priv; 1316 1317 *regmap = priv->regmap_base; 1318 *reg = RK2928_PULL_OFFSET; 1319 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1320 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1321 1322 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1323 }; 1324 1325 #define RK3128_PULL_OFFSET 0x118 1326 1327 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1328 int pin_num, struct regmap **regmap, 1329 int *reg, u8 *bit) 1330 { 1331 struct rockchip_pinctrl_priv *priv = bank->priv; 1332 1333 *regmap = priv->regmap_base; 1334 *reg = RK3128_PULL_OFFSET; 1335 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1336 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1337 1338 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1339 } 1340 1341 #define RK3188_PULL_OFFSET 0x164 1342 #define RK3188_PULL_BITS_PER_PIN 2 1343 #define RK3188_PULL_PINS_PER_REG 8 1344 #define RK3188_PULL_BANK_STRIDE 16 1345 #define RK3188_PULL_PMU_OFFSET 0x64 1346 1347 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1348 int pin_num, struct regmap **regmap, 1349 int *reg, u8 *bit) 1350 { 1351 struct rockchip_pinctrl_priv *priv = bank->priv; 1352 1353 /* The first 12 pins of the first bank are located elsewhere */ 1354 if (bank->bank_num == 0 && pin_num < 12) { 1355 *regmap = priv->regmap_pmu; 1356 *reg = RK3188_PULL_PMU_OFFSET; 1357 1358 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1359 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1360 *bit *= RK3188_PULL_BITS_PER_PIN; 1361 } else { 1362 *regmap = priv->regmap_base; 1363 *reg = RK3188_PULL_OFFSET; 1364 1365 /* correct the offset, as it is the 2nd pull register */ 1366 *reg -= 4; 1367 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1368 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1369 1370 /* 1371 * The bits in these registers have an inverse ordering 1372 * with the lowest pin being in bits 15:14 and the highest 1373 * pin in bits 1:0 1374 */ 1375 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1376 *bit *= RK3188_PULL_BITS_PER_PIN; 1377 } 1378 } 1379 1380 #define RK3288_PULL_OFFSET 0x140 1381 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1382 int pin_num, struct regmap **regmap, 1383 int *reg, u8 *bit) 1384 { 1385 struct rockchip_pinctrl_priv *priv = bank->priv; 1386 1387 /* The first 24 pins of the first bank are located in PMU */ 1388 if (bank->bank_num == 0) { 1389 *regmap = priv->regmap_pmu; 1390 *reg = RK3188_PULL_PMU_OFFSET; 1391 1392 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1393 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1394 *bit *= RK3188_PULL_BITS_PER_PIN; 1395 } else { 1396 *regmap = priv->regmap_base; 1397 *reg = RK3288_PULL_OFFSET; 1398 1399 /* correct the offset, as we're starting with the 2nd bank */ 1400 *reg -= 0x10; 1401 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1402 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1403 1404 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1405 *bit *= RK3188_PULL_BITS_PER_PIN; 1406 } 1407 } 1408 1409 #define RK3288_DRV_PMU_OFFSET 0x70 1410 #define RK3288_DRV_GRF_OFFSET 0x1c0 1411 #define RK3288_DRV_BITS_PER_PIN 2 1412 #define RK3288_DRV_PINS_PER_REG 8 1413 #define RK3288_DRV_BANK_STRIDE 16 1414 1415 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1416 int pin_num, struct regmap **regmap, 1417 int *reg, u8 *bit) 1418 { 1419 struct rockchip_pinctrl_priv *priv = bank->priv; 1420 1421 /* The first 24 pins of the first bank are located in PMU */ 1422 if (bank->bank_num == 0) { 1423 *regmap = priv->regmap_pmu; 1424 *reg = RK3288_DRV_PMU_OFFSET; 1425 1426 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1427 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1428 *bit *= RK3288_DRV_BITS_PER_PIN; 1429 } else { 1430 *regmap = priv->regmap_base; 1431 *reg = RK3288_DRV_GRF_OFFSET; 1432 1433 /* correct the offset, as we're starting with the 2nd bank */ 1434 *reg -= 0x10; 1435 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1436 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1437 1438 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1439 *bit *= RK3288_DRV_BITS_PER_PIN; 1440 } 1441 } 1442 1443 #define RK3228_PULL_OFFSET 0x100 1444 1445 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1446 int pin_num, struct regmap **regmap, 1447 int *reg, u8 *bit) 1448 { 1449 struct rockchip_pinctrl_priv *priv = bank->priv; 1450 1451 *regmap = priv->regmap_base; 1452 *reg = RK3228_PULL_OFFSET; 1453 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1454 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1455 1456 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1457 *bit *= RK3188_PULL_BITS_PER_PIN; 1458 } 1459 1460 #define RK3228_DRV_GRF_OFFSET 0x200 1461 1462 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1463 int pin_num, struct regmap **regmap, 1464 int *reg, u8 *bit) 1465 { 1466 struct rockchip_pinctrl_priv *priv = bank->priv; 1467 1468 *regmap = priv->regmap_base; 1469 *reg = RK3228_DRV_GRF_OFFSET; 1470 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1471 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1472 1473 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1474 *bit *= RK3288_DRV_BITS_PER_PIN; 1475 } 1476 1477 #define RK3308_PULL_OFFSET 0xa0 1478 1479 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1480 int pin_num, struct regmap **regmap, 1481 int *reg, u8 *bit) 1482 { 1483 struct rockchip_pinctrl_priv *priv = bank->priv; 1484 1485 *regmap = priv->regmap_base; 1486 *reg = RK3308_PULL_OFFSET; 1487 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1488 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1489 1490 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1491 *bit *= RK3188_PULL_BITS_PER_PIN; 1492 } 1493 1494 #define RK3308_DRV_GRF_OFFSET 0x100 1495 1496 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1497 int pin_num, struct regmap **regmap, 1498 int *reg, u8 *bit) 1499 { 1500 struct rockchip_pinctrl_priv *priv = bank->priv; 1501 1502 *regmap = priv->regmap_base; 1503 *reg = RK3308_DRV_GRF_OFFSET; 1504 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1505 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1506 1507 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1508 *bit *= RK3288_DRV_BITS_PER_PIN; 1509 } 1510 1511 #define RK3308_SCHMITT_PINS_PER_REG 8 1512 #define RK3308_SCHMITT_BANK_STRIDE 16 1513 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1514 1515 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1516 int pin_num, 1517 struct regmap **regmap, 1518 int *reg, u8 *bit) 1519 { 1520 struct rockchip_pinctrl_priv *priv = bank->priv; 1521 1522 *regmap = priv->regmap_base; 1523 *reg = RK3308_SCHMITT_GRF_OFFSET; 1524 1525 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1526 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1527 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1528 1529 return 0; 1530 } 1531 1532 #define RK3368_PULL_GRF_OFFSET 0x100 1533 #define RK3368_PULL_PMU_OFFSET 0x10 1534 1535 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1536 int pin_num, struct regmap **regmap, 1537 int *reg, u8 *bit) 1538 { 1539 struct rockchip_pinctrl_priv *priv = bank->priv; 1540 1541 /* The first 32 pins of the first bank are located in PMU */ 1542 if (bank->bank_num == 0) { 1543 *regmap = priv->regmap_pmu; 1544 *reg = RK3368_PULL_PMU_OFFSET; 1545 1546 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1547 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1548 *bit *= RK3188_PULL_BITS_PER_PIN; 1549 } else { 1550 *regmap = priv->regmap_base; 1551 *reg = RK3368_PULL_GRF_OFFSET; 1552 1553 /* correct the offset, as we're starting with the 2nd bank */ 1554 *reg -= 0x10; 1555 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1556 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1557 1558 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1559 *bit *= RK3188_PULL_BITS_PER_PIN; 1560 } 1561 } 1562 1563 #define RK3368_DRV_PMU_OFFSET 0x20 1564 #define RK3368_DRV_GRF_OFFSET 0x200 1565 1566 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1567 int pin_num, struct regmap **regmap, 1568 int *reg, u8 *bit) 1569 { 1570 struct rockchip_pinctrl_priv *priv = bank->priv; 1571 1572 /* The first 32 pins of the first bank are located in PMU */ 1573 if (bank->bank_num == 0) { 1574 *regmap = priv->regmap_pmu; 1575 *reg = RK3368_DRV_PMU_OFFSET; 1576 1577 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1578 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1579 *bit *= RK3288_DRV_BITS_PER_PIN; 1580 } else { 1581 *regmap = priv->regmap_base; 1582 *reg = RK3368_DRV_GRF_OFFSET; 1583 1584 /* correct the offset, as we're starting with the 2nd bank */ 1585 *reg -= 0x10; 1586 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1587 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1588 1589 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1590 *bit *= RK3288_DRV_BITS_PER_PIN; 1591 } 1592 } 1593 1594 #define RK3399_PULL_GRF_OFFSET 0xe040 1595 #define RK3399_PULL_PMU_OFFSET 0x40 1596 #define RK3399_DRV_3BITS_PER_PIN 3 1597 1598 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1599 int pin_num, struct regmap **regmap, 1600 int *reg, u8 *bit) 1601 { 1602 struct rockchip_pinctrl_priv *priv = bank->priv; 1603 1604 /* The bank0:16 and bank1:32 pins are located in PMU */ 1605 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1606 *regmap = priv->regmap_pmu; 1607 *reg = RK3399_PULL_PMU_OFFSET; 1608 1609 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1610 1611 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1612 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1613 *bit *= RK3188_PULL_BITS_PER_PIN; 1614 } else { 1615 *regmap = priv->regmap_base; 1616 *reg = RK3399_PULL_GRF_OFFSET; 1617 1618 /* correct the offset, as we're starting with the 3rd bank */ 1619 *reg -= 0x20; 1620 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1621 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1622 1623 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1624 *bit *= RK3188_PULL_BITS_PER_PIN; 1625 } 1626 } 1627 1628 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1629 int pin_num, struct regmap **regmap, 1630 int *reg, u8 *bit) 1631 { 1632 struct rockchip_pinctrl_priv *priv = bank->priv; 1633 int drv_num = (pin_num / 8); 1634 1635 /* The bank0:16 and bank1:32 pins are located in PMU */ 1636 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1637 *regmap = priv->regmap_pmu; 1638 else 1639 *regmap = priv->regmap_base; 1640 1641 *reg = bank->drv[drv_num].offset; 1642 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1643 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1644 *bit = (pin_num % 8) * 3; 1645 else 1646 *bit = (pin_num % 8) * 2; 1647 } 1648 1649 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1650 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1651 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1652 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1653 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1654 { 4, 7, 10, 13, 16, 19, 22, 26 } 1655 }; 1656 1657 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1658 int pin_num, int strength) 1659 { 1660 struct rockchip_pinctrl_priv *priv = bank->priv; 1661 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1662 struct regmap *regmap; 1663 int reg, ret, i; 1664 u32 data, rmask_bits, temp; 1665 u8 bit; 1666 int drv_type = bank->drv[pin_num / 8].drv_type; 1667 1668 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1669 pin_num, strength); 1670 1671 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1672 1673 ret = -EINVAL; 1674 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1675 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1676 ret = i; 1677 break; 1678 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1679 ret = rockchip_perpin_drv_list[drv_type][i]; 1680 break; 1681 } 1682 } 1683 1684 if (ret < 0) { 1685 debug("unsupported driver strength %d\n", strength); 1686 return ret; 1687 } 1688 1689 switch (drv_type) { 1690 case DRV_TYPE_IO_1V8_3V0_AUTO: 1691 case DRV_TYPE_IO_3V3_ONLY: 1692 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1693 switch (bit) { 1694 case 0 ... 12: 1695 /* regular case, nothing to do */ 1696 break; 1697 case 15: 1698 /* 1699 * drive-strength offset is special, as it is spread 1700 * over 2 registers, the bit data[15] contains bit 0 1701 * of the value while temp[1:0] contains bits 2 and 1 1702 */ 1703 data = (ret & 0x1) << 15; 1704 temp = (ret >> 0x1) & 0x3; 1705 1706 data |= BIT(31); 1707 ret = regmap_write(regmap, reg, data); 1708 if (ret) 1709 return ret; 1710 1711 temp |= (0x3 << 16); 1712 reg += 0x4; 1713 ret = regmap_write(regmap, reg, temp); 1714 1715 return ret; 1716 case 18 ... 21: 1717 /* setting fully enclosed in the second register */ 1718 reg += 4; 1719 bit -= 16; 1720 break; 1721 default: 1722 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1723 bit, drv_type); 1724 return -EINVAL; 1725 } 1726 break; 1727 case DRV_TYPE_IO_DEFAULT: 1728 case DRV_TYPE_IO_1V8_OR_3V0: 1729 case DRV_TYPE_IO_1V8_ONLY: 1730 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1731 break; 1732 default: 1733 debug("unsupported pinctrl drive type: %d\n", 1734 drv_type); 1735 return -EINVAL; 1736 } 1737 1738 /* enable the write to the equivalent lower bits */ 1739 data = ((1 << rmask_bits) - 1) << (bit + 16); 1740 data |= (ret << bit); 1741 1742 ret = regmap_write(regmap, reg, data); 1743 return ret; 1744 } 1745 1746 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1747 { 1748 PIN_CONFIG_BIAS_DISABLE, 1749 PIN_CONFIG_BIAS_PULL_UP, 1750 PIN_CONFIG_BIAS_PULL_DOWN, 1751 PIN_CONFIG_BIAS_BUS_HOLD 1752 }, 1753 { 1754 PIN_CONFIG_BIAS_DISABLE, 1755 PIN_CONFIG_BIAS_PULL_DOWN, 1756 PIN_CONFIG_BIAS_DISABLE, 1757 PIN_CONFIG_BIAS_PULL_UP 1758 }, 1759 }; 1760 1761 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1762 int pin_num, int pull) 1763 { 1764 struct rockchip_pinctrl_priv *priv = bank->priv; 1765 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1766 struct regmap *regmap; 1767 int reg, ret, i, pull_type; 1768 u8 bit; 1769 u32 data; 1770 1771 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1772 pin_num, pull); 1773 1774 /* rk3066b does support any pulls */ 1775 if (ctrl->type == RK3066B) 1776 return pull ? -EINVAL : 0; 1777 1778 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1779 1780 switch (ctrl->type) { 1781 case RK2928: 1782 case RK3128: 1783 data = BIT(bit + 16); 1784 if (pull == PIN_CONFIG_BIAS_DISABLE) 1785 data |= BIT(bit); 1786 ret = regmap_write(regmap, reg, data); 1787 break; 1788 case PX30: 1789 case RV1108: 1790 case RK3188: 1791 case RK3288: 1792 case RK3308: 1793 case RK3368: 1794 case RK3399: 1795 pull_type = bank->pull_type[pin_num / 8]; 1796 ret = -EINVAL; 1797 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1798 i++) { 1799 if (rockchip_pull_list[pull_type][i] == pull) { 1800 ret = i; 1801 break; 1802 } 1803 } 1804 1805 if (ret < 0) { 1806 debug("unsupported pull setting %d\n", pull); 1807 return ret; 1808 } 1809 1810 /* enable the write to the equivalent lower bits */ 1811 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1812 data |= (ret << bit); 1813 1814 ret = regmap_write(regmap, reg, data); 1815 break; 1816 default: 1817 debug("unsupported pinctrl type\n"); 1818 return -EINVAL; 1819 } 1820 1821 return ret; 1822 } 1823 1824 #define RK3328_SCHMITT_BITS_PER_PIN 1 1825 #define RK3328_SCHMITT_PINS_PER_REG 16 1826 #define RK3328_SCHMITT_BANK_STRIDE 8 1827 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1828 1829 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1830 int pin_num, 1831 struct regmap **regmap, 1832 int *reg, u8 *bit) 1833 { 1834 struct rockchip_pinctrl_priv *priv = bank->priv; 1835 1836 *regmap = priv->regmap_base; 1837 *reg = RK3328_SCHMITT_GRF_OFFSET; 1838 1839 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1840 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1841 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1842 1843 return 0; 1844 } 1845 1846 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1847 int pin_num, int enable) 1848 { 1849 struct rockchip_pinctrl_priv *priv = bank->priv; 1850 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1851 struct regmap *regmap; 1852 int reg, ret; 1853 u8 bit; 1854 u32 data; 1855 1856 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 1857 pin_num, enable); 1858 1859 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1860 if (ret) 1861 return ret; 1862 1863 /* enable the write to the equivalent lower bits */ 1864 data = BIT(bit + 16) | (enable << bit); 1865 1866 return regmap_write(regmap, reg, data); 1867 } 1868 1869 /* 1870 * Pinconf_ops handling 1871 */ 1872 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1873 unsigned int pull) 1874 { 1875 switch (ctrl->type) { 1876 case RK2928: 1877 case RK3128: 1878 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1879 pull == PIN_CONFIG_BIAS_DISABLE); 1880 case RK3066B: 1881 return pull ? false : true; 1882 case PX30: 1883 case RV1108: 1884 case RK3188: 1885 case RK3288: 1886 case RK3308: 1887 case RK3368: 1888 case RK3399: 1889 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1890 } 1891 1892 return false; 1893 } 1894 1895 /* set the pin config settings for a specified pin */ 1896 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 1897 u32 pin, u32 param, u32 arg) 1898 { 1899 struct rockchip_pinctrl_priv *priv = bank->priv; 1900 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1901 int rc; 1902 1903 switch (param) { 1904 case PIN_CONFIG_BIAS_DISABLE: 1905 rc = rockchip_set_pull(bank, pin, param); 1906 if (rc) 1907 return rc; 1908 break; 1909 1910 case PIN_CONFIG_BIAS_PULL_UP: 1911 case PIN_CONFIG_BIAS_PULL_DOWN: 1912 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1913 case PIN_CONFIG_BIAS_BUS_HOLD: 1914 if (!rockchip_pinconf_pull_valid(ctrl, param)) 1915 return -ENOTSUPP; 1916 1917 if (!arg) 1918 return -EINVAL; 1919 1920 rc = rockchip_set_pull(bank, pin, param); 1921 if (rc) 1922 return rc; 1923 break; 1924 1925 case PIN_CONFIG_DRIVE_STRENGTH: 1926 if (!ctrl->drv_calc_reg) 1927 return -ENOTSUPP; 1928 1929 rc = rockchip_set_drive_perpin(bank, pin, arg); 1930 if (rc < 0) 1931 return rc; 1932 break; 1933 1934 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1935 if (!ctrl->schmitt_calc_reg) 1936 return -ENOTSUPP; 1937 1938 rc = rockchip_set_schmitt(bank, pin, arg); 1939 if (rc < 0) 1940 return rc; 1941 break; 1942 1943 default: 1944 break; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static const struct pinconf_param rockchip_conf_params[] = { 1951 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 1952 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 1953 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 1954 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 1955 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 1956 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 1957 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 1958 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 1959 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 1960 }; 1961 1962 static int rockchip_pinconf_prop_name_to_param(const char *property, 1963 u32 *default_value) 1964 { 1965 const struct pinconf_param *p, *end; 1966 1967 p = rockchip_conf_params; 1968 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 1969 1970 /* See if this pctldev supports this parameter */ 1971 for (; p < end; p++) { 1972 if (!strcmp(property, p->property)) { 1973 *default_value = p->default_value; 1974 return p->param; 1975 } 1976 } 1977 1978 *default_value = 0; 1979 return -EPERM; 1980 } 1981 1982 static int rockchip_pinctrl_set_state(struct udevice *dev, 1983 struct udevice *config) 1984 { 1985 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1986 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1987 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 1988 u32 bank, pin, mux, conf, arg, default_val; 1989 int ret, count, i; 1990 const char *prop_name; 1991 const void *value; 1992 int prop_len, param; 1993 const u32 *data; 1994 ofnode node; 1995 #ifdef CONFIG_OF_LIVE 1996 const struct device_node *np; 1997 struct property *pp; 1998 #else 1999 int property_offset, pcfg_node; 2000 const void *blob = gd->fdt_blob; 2001 #endif 2002 data = dev_read_prop(config, "rockchip,pins", &count); 2003 if (count < 0) { 2004 debug("%s: bad array size %d\n", __func__, count); 2005 return -EINVAL; 2006 } 2007 2008 count /= sizeof(u32); 2009 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2010 debug("%s: unsupported pins array count %d\n", 2011 __func__, count); 2012 return -EINVAL; 2013 } 2014 2015 for (i = 0; i < count; i++) 2016 cells[i] = fdt32_to_cpu(data[i]); 2017 2018 for (i = 0; i < (count >> 2); i++) { 2019 bank = cells[4 * i + 0]; 2020 pin = cells[4 * i + 1]; 2021 mux = cells[4 * i + 2]; 2022 conf = cells[4 * i + 3]; 2023 2024 ret = rockchip_verify_config(dev, bank, pin); 2025 if (ret) 2026 return ret; 2027 2028 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2029 if (ret) 2030 return ret; 2031 2032 node = ofnode_get_by_phandle(conf); 2033 if (!ofnode_valid(node)) 2034 return -ENODEV; 2035 #ifdef CONFIG_OF_LIVE 2036 np = ofnode_to_np(node); 2037 for (pp = np->properties; pp; pp = pp->next) { 2038 prop_name = pp->name; 2039 prop_len = pp->length; 2040 value = pp->value; 2041 #else 2042 pcfg_node = ofnode_to_offset(node); 2043 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2044 value = fdt_getprop_by_offset(blob, property_offset, 2045 &prop_name, &prop_len); 2046 if (!value) 2047 return -ENOENT; 2048 #endif 2049 param = rockchip_pinconf_prop_name_to_param(prop_name, 2050 &default_val); 2051 if (param < 0) 2052 break; 2053 2054 if (prop_len >= sizeof(fdt32_t)) 2055 arg = fdt32_to_cpu(*(fdt32_t *)value); 2056 else 2057 arg = default_val; 2058 2059 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2060 param, arg); 2061 if (ret) { 2062 debug("%s: rockchip_pinconf_set fail: %d\n", 2063 __func__, ret); 2064 return ret; 2065 } 2066 } 2067 } 2068 2069 return 0; 2070 } 2071 2072 static struct pinctrl_ops rockchip_pinctrl_ops = { 2073 .set_state = rockchip_pinctrl_set_state, 2074 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2075 }; 2076 2077 /* retrieve the soc specific data */ 2078 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2079 { 2080 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2081 struct rockchip_pin_ctrl *ctrl = 2082 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2083 struct rockchip_pin_bank *bank; 2084 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2085 2086 grf_offs = ctrl->grf_mux_offset; 2087 pmu_offs = ctrl->pmu_mux_offset; 2088 drv_pmu_offs = ctrl->pmu_drv_offset; 2089 drv_grf_offs = ctrl->grf_drv_offset; 2090 bank = ctrl->pin_banks; 2091 2092 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2093 int bank_pins = 0; 2094 2095 bank->priv = priv; 2096 bank->pin_base = ctrl->nr_pins; 2097 ctrl->nr_pins += bank->nr_pins; 2098 2099 /* calculate iomux and drv offsets */ 2100 for (j = 0; j < 4; j++) { 2101 struct rockchip_iomux *iom = &bank->iomux[j]; 2102 struct rockchip_drv *drv = &bank->drv[j]; 2103 int inc; 2104 2105 if (bank_pins >= bank->nr_pins) 2106 break; 2107 2108 /* preset iomux offset value, set new start value */ 2109 if (iom->offset >= 0) { 2110 if (iom->type & IOMUX_SOURCE_PMU) 2111 pmu_offs = iom->offset; 2112 else 2113 grf_offs = iom->offset; 2114 } else { /* set current iomux offset */ 2115 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2116 pmu_offs : grf_offs; 2117 } 2118 2119 /* preset drv offset value, set new start value */ 2120 if (drv->offset >= 0) { 2121 if (iom->type & IOMUX_SOURCE_PMU) 2122 drv_pmu_offs = drv->offset; 2123 else 2124 drv_grf_offs = drv->offset; 2125 } else { /* set current drv offset */ 2126 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2127 drv_pmu_offs : drv_grf_offs; 2128 } 2129 2130 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2131 i, j, iom->offset, drv->offset); 2132 2133 /* 2134 * Increase offset according to iomux width. 2135 * 4bit iomux'es are spread over two registers. 2136 */ 2137 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2138 IOMUX_WIDTH_3BIT | 2139 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2140 if (iom->type & IOMUX_SOURCE_PMU) 2141 pmu_offs += inc; 2142 else 2143 grf_offs += inc; 2144 2145 /* 2146 * Increase offset according to drv width. 2147 * 3bit drive-strenth'es are spread over two registers. 2148 */ 2149 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2150 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2151 inc = 8; 2152 else 2153 inc = 4; 2154 2155 if (iom->type & IOMUX_SOURCE_PMU) 2156 drv_pmu_offs += inc; 2157 else 2158 drv_grf_offs += inc; 2159 2160 bank_pins += 8; 2161 } 2162 2163 /* calculate the per-bank recalced_mask */ 2164 for (j = 0; j < ctrl->niomux_recalced; j++) { 2165 int pin = 0; 2166 2167 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2168 pin = ctrl->iomux_recalced[j].pin; 2169 bank->recalced_mask |= BIT(pin); 2170 } 2171 } 2172 2173 /* calculate the per-bank route_mask */ 2174 for (j = 0; j < ctrl->niomux_routes; j++) { 2175 int pin = 0; 2176 2177 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2178 pin = ctrl->iomux_routes[j].pin; 2179 bank->route_mask |= BIT(pin); 2180 } 2181 } 2182 } 2183 2184 return ctrl; 2185 } 2186 2187 static int rockchip_pinctrl_probe(struct udevice *dev) 2188 { 2189 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2190 struct rockchip_pin_ctrl *ctrl; 2191 struct udevice *syscon; 2192 struct regmap *regmap; 2193 int ret = 0; 2194 2195 /* get rockchip grf syscon phandle */ 2196 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2197 &syscon); 2198 if (ret) { 2199 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2200 return ret; 2201 } 2202 2203 /* get grf-reg base address */ 2204 regmap = syscon_get_regmap(syscon); 2205 if (!regmap) { 2206 debug("unable to find rockchip grf regmap\n"); 2207 return -ENODEV; 2208 } 2209 priv->regmap_base = regmap; 2210 2211 /* option: get pmu-reg base address */ 2212 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2213 &syscon); 2214 if (!ret) { 2215 /* get pmugrf-reg base address */ 2216 regmap = syscon_get_regmap(syscon); 2217 if (!regmap) { 2218 debug("unable to find rockchip pmu regmap\n"); 2219 return -ENODEV; 2220 } 2221 priv->regmap_pmu = regmap; 2222 } 2223 2224 ctrl = rockchip_pinctrl_get_soc_data(dev); 2225 if (!ctrl) { 2226 debug("driver data not available\n"); 2227 return -EINVAL; 2228 } 2229 2230 priv->ctrl = ctrl; 2231 return 0; 2232 } 2233 2234 static struct rockchip_pin_bank px30_pin_banks[] = { 2235 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2236 IOMUX_SOURCE_PMU, 2237 IOMUX_SOURCE_PMU, 2238 IOMUX_SOURCE_PMU 2239 ), 2240 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2241 IOMUX_WIDTH_4BIT, 2242 IOMUX_WIDTH_4BIT, 2243 IOMUX_WIDTH_4BIT 2244 ), 2245 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2246 IOMUX_WIDTH_4BIT, 2247 IOMUX_WIDTH_4BIT, 2248 IOMUX_WIDTH_4BIT 2249 ), 2250 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2251 IOMUX_WIDTH_4BIT, 2252 IOMUX_WIDTH_4BIT, 2253 IOMUX_WIDTH_4BIT 2254 ), 2255 }; 2256 2257 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2258 .pin_banks = px30_pin_banks, 2259 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2260 .label = "PX30-GPIO", 2261 .type = PX30, 2262 .grf_mux_offset = 0x0, 2263 .pmu_mux_offset = 0x0, 2264 .iomux_routes = px30_mux_route_data, 2265 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2266 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2267 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2268 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2269 }; 2270 2271 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2272 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2273 IOMUX_SOURCE_PMU, 2274 IOMUX_SOURCE_PMU, 2275 IOMUX_SOURCE_PMU), 2276 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2277 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2278 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2279 }; 2280 2281 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2282 .pin_banks = rv1108_pin_banks, 2283 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2284 .label = "RV1108-GPIO", 2285 .type = RV1108, 2286 .grf_mux_offset = 0x10, 2287 .pmu_mux_offset = 0x0, 2288 .iomux_recalced = rv1108_mux_recalced_data, 2289 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2290 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2291 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2292 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2293 }; 2294 2295 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2296 PIN_BANK(0, 32, "gpio0"), 2297 PIN_BANK(1, 32, "gpio1"), 2298 PIN_BANK(2, 32, "gpio2"), 2299 PIN_BANK(3, 32, "gpio3"), 2300 }; 2301 2302 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2303 .pin_banks = rk2928_pin_banks, 2304 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2305 .label = "RK2928-GPIO", 2306 .type = RK2928, 2307 .grf_mux_offset = 0xa8, 2308 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2309 }; 2310 2311 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2312 PIN_BANK(0, 32, "gpio0"), 2313 PIN_BANK(1, 32, "gpio1"), 2314 PIN_BANK(2, 32, "gpio2"), 2315 }; 2316 2317 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2318 .pin_banks = rk3036_pin_banks, 2319 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2320 .label = "RK3036-GPIO", 2321 .type = RK2928, 2322 .grf_mux_offset = 0xa8, 2323 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2324 }; 2325 2326 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2327 PIN_BANK(0, 32, "gpio0"), 2328 PIN_BANK(1, 32, "gpio1"), 2329 PIN_BANK(2, 32, "gpio2"), 2330 PIN_BANK(3, 32, "gpio3"), 2331 PIN_BANK(4, 32, "gpio4"), 2332 PIN_BANK(6, 16, "gpio6"), 2333 }; 2334 2335 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2336 .pin_banks = rk3066a_pin_banks, 2337 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2338 .label = "RK3066a-GPIO", 2339 .type = RK2928, 2340 .grf_mux_offset = 0xa8, 2341 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2342 }; 2343 2344 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2345 PIN_BANK(0, 32, "gpio0"), 2346 PIN_BANK(1, 32, "gpio1"), 2347 PIN_BANK(2, 32, "gpio2"), 2348 PIN_BANK(3, 32, "gpio3"), 2349 }; 2350 2351 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2352 .pin_banks = rk3066b_pin_banks, 2353 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2354 .label = "RK3066b-GPIO", 2355 .type = RK3066B, 2356 .grf_mux_offset = 0x60, 2357 }; 2358 2359 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2360 PIN_BANK(0, 32, "gpio0"), 2361 PIN_BANK(1, 32, "gpio1"), 2362 PIN_BANK(2, 32, "gpio2"), 2363 PIN_BANK(3, 32, "gpio3"), 2364 }; 2365 2366 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2367 .pin_banks = rk3128_pin_banks, 2368 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2369 .label = "RK3128-GPIO", 2370 .type = RK3128, 2371 .grf_mux_offset = 0xa8, 2372 .iomux_recalced = rk3128_mux_recalced_data, 2373 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2374 .iomux_routes = rk3128_mux_route_data, 2375 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2376 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2377 }; 2378 2379 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2380 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2381 PIN_BANK(1, 32, "gpio1"), 2382 PIN_BANK(2, 32, "gpio2"), 2383 PIN_BANK(3, 32, "gpio3"), 2384 }; 2385 2386 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2387 .pin_banks = rk3188_pin_banks, 2388 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2389 .label = "RK3188-GPIO", 2390 .type = RK3188, 2391 .grf_mux_offset = 0x60, 2392 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2393 }; 2394 2395 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2396 PIN_BANK(0, 32, "gpio0"), 2397 PIN_BANK(1, 32, "gpio1"), 2398 PIN_BANK(2, 32, "gpio2"), 2399 PIN_BANK(3, 32, "gpio3"), 2400 }; 2401 2402 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2403 .pin_banks = rk3228_pin_banks, 2404 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2405 .label = "RK3228-GPIO", 2406 .type = RK3288, 2407 .grf_mux_offset = 0x0, 2408 .iomux_routes = rk3228_mux_route_data, 2409 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2410 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2411 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2412 }; 2413 2414 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2415 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU | IOMUX_UNMASKED, 2416 IOMUX_SOURCE_PMU | IOMUX_UNMASKED, 2417 IOMUX_SOURCE_PMU | IOMUX_UNMASKED, 2418 IOMUX_UNROUTED 2419 ), 2420 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2421 IOMUX_UNROUTED, 2422 IOMUX_UNROUTED, 2423 0 2424 ), 2425 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2426 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2427 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2428 IOMUX_WIDTH_4BIT, 2429 0, 2430 0 2431 ), 2432 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2433 0, 2434 0, 2435 IOMUX_UNROUTED 2436 ), 2437 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2438 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2439 0, 2440 IOMUX_WIDTH_4BIT, 2441 IOMUX_UNROUTED 2442 ), 2443 PIN_BANK(8, 16, "gpio8"), 2444 }; 2445 2446 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2447 .pin_banks = rk3288_pin_banks, 2448 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2449 .label = "RK3288-GPIO", 2450 .type = RK3288, 2451 .grf_mux_offset = 0x0, 2452 .pmu_mux_offset = 0x84, 2453 .iomux_routes = rk3288_mux_route_data, 2454 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2455 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2456 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2457 }; 2458 2459 static struct rockchip_pin_bank rk3308_pin_banks[] = { 2460 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 2461 IOMUX_8WIDTH_2BIT, 2462 IOMUX_8WIDTH_2BIT, 2463 IOMUX_8WIDTH_2BIT), 2464 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 2465 IOMUX_8WIDTH_2BIT, 2466 IOMUX_8WIDTH_2BIT, 2467 IOMUX_8WIDTH_2BIT), 2468 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 2469 IOMUX_8WIDTH_2BIT, 2470 IOMUX_8WIDTH_2BIT, 2471 IOMUX_8WIDTH_2BIT), 2472 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 2473 IOMUX_8WIDTH_2BIT, 2474 IOMUX_8WIDTH_2BIT, 2475 IOMUX_8WIDTH_2BIT), 2476 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 2477 IOMUX_8WIDTH_2BIT, 2478 IOMUX_8WIDTH_2BIT, 2479 IOMUX_8WIDTH_2BIT), 2480 }; 2481 2482 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 2483 .pin_banks = rk3308_pin_banks, 2484 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 2485 .label = "RK3308-GPIO", 2486 .type = RK3308, 2487 .grf_mux_offset = 0x0, 2488 .iomux_recalced = rk3308_mux_recalced_data, 2489 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 2490 .iomux_routes = rk3308_mux_route_data, 2491 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 2492 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 2493 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 2494 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 2495 }; 2496 2497 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2498 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2499 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2500 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2501 IOMUX_WIDTH_3BIT, 2502 IOMUX_WIDTH_3BIT, 2503 0), 2504 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2505 IOMUX_WIDTH_3BIT, 2506 IOMUX_WIDTH_3BIT, 2507 0, 2508 0), 2509 }; 2510 2511 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2512 .pin_banks = rk3328_pin_banks, 2513 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2514 .label = "RK3328-GPIO", 2515 .type = RK3288, 2516 .grf_mux_offset = 0x0, 2517 .iomux_recalced = rk3328_mux_recalced_data, 2518 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2519 .iomux_routes = rk3328_mux_route_data, 2520 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2521 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2522 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2523 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2524 }; 2525 2526 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2527 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2528 IOMUX_SOURCE_PMU, 2529 IOMUX_SOURCE_PMU, 2530 IOMUX_SOURCE_PMU 2531 ), 2532 PIN_BANK(1, 32, "gpio1"), 2533 PIN_BANK(2, 32, "gpio2"), 2534 PIN_BANK(3, 32, "gpio3"), 2535 }; 2536 2537 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2538 .pin_banks = rk3368_pin_banks, 2539 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2540 .label = "RK3368-GPIO", 2541 .type = RK3368, 2542 .grf_mux_offset = 0x0, 2543 .pmu_mux_offset = 0x0, 2544 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2545 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2546 }; 2547 2548 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2549 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2550 IOMUX_SOURCE_PMU, 2551 IOMUX_SOURCE_PMU, 2552 IOMUX_SOURCE_PMU, 2553 IOMUX_SOURCE_PMU, 2554 DRV_TYPE_IO_1V8_ONLY, 2555 DRV_TYPE_IO_1V8_ONLY, 2556 DRV_TYPE_IO_DEFAULT, 2557 DRV_TYPE_IO_DEFAULT, 2558 0x80, 2559 0x88, 2560 -1, 2561 -1, 2562 PULL_TYPE_IO_1V8_ONLY, 2563 PULL_TYPE_IO_1V8_ONLY, 2564 PULL_TYPE_IO_DEFAULT, 2565 PULL_TYPE_IO_DEFAULT 2566 ), 2567 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2568 IOMUX_SOURCE_PMU, 2569 IOMUX_SOURCE_PMU, 2570 IOMUX_SOURCE_PMU, 2571 DRV_TYPE_IO_1V8_OR_3V0, 2572 DRV_TYPE_IO_1V8_OR_3V0, 2573 DRV_TYPE_IO_1V8_OR_3V0, 2574 DRV_TYPE_IO_1V8_OR_3V0, 2575 0xa0, 2576 0xa8, 2577 0xb0, 2578 0xb8 2579 ), 2580 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2581 DRV_TYPE_IO_1V8_OR_3V0, 2582 DRV_TYPE_IO_1V8_ONLY, 2583 DRV_TYPE_IO_1V8_ONLY, 2584 PULL_TYPE_IO_DEFAULT, 2585 PULL_TYPE_IO_DEFAULT, 2586 PULL_TYPE_IO_1V8_ONLY, 2587 PULL_TYPE_IO_1V8_ONLY 2588 ), 2589 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2590 DRV_TYPE_IO_3V3_ONLY, 2591 DRV_TYPE_IO_3V3_ONLY, 2592 DRV_TYPE_IO_1V8_OR_3V0 2593 ), 2594 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2595 DRV_TYPE_IO_1V8_3V0_AUTO, 2596 DRV_TYPE_IO_1V8_OR_3V0, 2597 DRV_TYPE_IO_1V8_OR_3V0 2598 ), 2599 }; 2600 2601 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2602 .pin_banks = rk3399_pin_banks, 2603 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2604 .label = "RK3399-GPIO", 2605 .type = RK3399, 2606 .grf_mux_offset = 0xe000, 2607 .pmu_mux_offset = 0x0, 2608 .grf_drv_offset = 0xe100, 2609 .pmu_drv_offset = 0x80, 2610 .iomux_routes = rk3399_mux_route_data, 2611 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2612 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2613 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2614 }; 2615 2616 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2617 { .compatible = "rockchip,px30-pinctrl", 2618 .data = (ulong)&px30_pin_ctrl }, 2619 { .compatible = "rockchip,rv1108-pinctrl", 2620 .data = (ulong)&rv1108_pin_ctrl }, 2621 { .compatible = "rockchip,rk2928-pinctrl", 2622 .data = (ulong)&rk2928_pin_ctrl }, 2623 { .compatible = "rockchip,rk3036-pinctrl", 2624 .data = (ulong)&rk3036_pin_ctrl }, 2625 { .compatible = "rockchip,rk3066a-pinctrl", 2626 .data = (ulong)&rk3066a_pin_ctrl }, 2627 { .compatible = "rockchip,rk3066b-pinctrl", 2628 .data = (ulong)&rk3066b_pin_ctrl }, 2629 { .compatible = "rockchip,rk3128-pinctrl", 2630 .data = (ulong)&rk3128_pin_ctrl }, 2631 { .compatible = "rockchip,rk3188-pinctrl", 2632 .data = (ulong)&rk3188_pin_ctrl }, 2633 { .compatible = "rockchip,rk3228-pinctrl", 2634 .data = (ulong)&rk3228_pin_ctrl }, 2635 { .compatible = "rockchip,rk3288-pinctrl", 2636 .data = (ulong)&rk3288_pin_ctrl }, 2637 { .compatible = "rockchip,rk3308-pinctrl", 2638 .data = (ulong)&rk3308_pin_ctrl }, 2639 { .compatible = "rockchip,rk3328-pinctrl", 2640 .data = (ulong)&rk3328_pin_ctrl }, 2641 { .compatible = "rockchip,rk3368-pinctrl", 2642 .data = (ulong)&rk3368_pin_ctrl }, 2643 { .compatible = "rockchip,rk3399-pinctrl", 2644 .data = (ulong)&rk3399_pin_ctrl }, 2645 {}, 2646 }; 2647 2648 U_BOOT_DRIVER(pinctrl_rockchip) = { 2649 .name = "rockchip_pinctrl", 2650 .id = UCLASS_PINCTRL, 2651 .of_match = rockchip_pinctrl_dt_match, 2652 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2653 .ops = &rockchip_pinctrl_ops, 2654 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2655 .bind = dm_scan_fdt_dev, 2656 #endif 2657 .probe = rockchip_pinctrl_probe, 2658 }; 2659