1 /* 2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <dm.h> 9 #include <dm/pinctrl.h> 10 #include <dm/ofnode.h> 11 #include <regmap.h> 12 #include <syscon.h> 13 14 #define MAX_ROCKCHIP_GPIO_PER_BANK 32 15 #define RK_FUNC_GPIO 0 16 #define MAX_ROCKCHIP_PINS_ENTRIES 30 17 18 enum rockchip_pinctrl_type { 19 PX30, 20 RV1108, 21 RK2928, 22 RK3066B, 23 RK3128, 24 RK3188, 25 RK3288, 26 RK3308, 27 RK3368, 28 RK3399, 29 }; 30 31 /** 32 * Encode variants of iomux registers into a type variable 33 */ 34 #define IOMUX_GPIO_ONLY BIT(0) 35 #define IOMUX_WIDTH_4BIT BIT(1) 36 #define IOMUX_SOURCE_PMU BIT(2) 37 #define IOMUX_UNROUTED BIT(3) 38 #define IOMUX_WIDTH_3BIT BIT(4) 39 #define IOMUX_8WIDTH_2BIT BIT(5) 40 41 /** 42 * @type: iomux variant using IOMUX_* constants 43 * @offset: if initialized to -1 it will be autocalculated, by specifying 44 * an initial offset value the relevant source offset can be reset 45 * to a new value for autocalculating the following iomux registers. 46 */ 47 struct rockchip_iomux { 48 int type; 49 int offset; 50 }; 51 52 /** 53 * enum type index corresponding to rockchip_perpin_drv_list arrays index. 54 */ 55 enum rockchip_pin_drv_type { 56 DRV_TYPE_IO_DEFAULT = 0, 57 DRV_TYPE_IO_1V8_OR_3V0, 58 DRV_TYPE_IO_1V8_ONLY, 59 DRV_TYPE_IO_1V8_3V0_AUTO, 60 DRV_TYPE_IO_3V3_ONLY, 61 DRV_TYPE_MAX 62 }; 63 64 /** 65 * enum type index corresponding to rockchip_pull_list arrays index. 66 */ 67 enum rockchip_pin_pull_type { 68 PULL_TYPE_IO_DEFAULT = 0, 69 PULL_TYPE_IO_1V8_ONLY, 70 PULL_TYPE_MAX 71 }; 72 73 /** 74 * @drv_type: drive strength variant using rockchip_perpin_drv_type 75 * @offset: if initialized to -1 it will be autocalculated, by specifying 76 * an initial offset value the relevant source offset can be reset 77 * to a new value for autocalculating the following drive strength 78 * registers. if used chips own cal_drv func instead to calculate 79 * registers offset, the variant could be ignored. 80 */ 81 struct rockchip_drv { 82 enum rockchip_pin_drv_type drv_type; 83 int offset; 84 }; 85 86 /** 87 * @priv: common pinctrl private basedata 88 * @pin_base: first pin number 89 * @nr_pins: number of pins in this bank 90 * @name: name of the bank 91 * @bank_num: number of the bank, to account for holes 92 * @iomux: array describing the 4 iomux sources of the bank 93 * @drv: array describing the 4 drive strength sources of the bank 94 * @pull_type: array describing the 4 pull type sources of the bank 95 * @recalced_mask: bits describing the mux recalced pins of per bank 96 * @route_mask: bits describing the routing pins of per bank 97 */ 98 struct rockchip_pin_bank { 99 struct rockchip_pinctrl_priv *priv; 100 u32 pin_base; 101 u8 nr_pins; 102 char *name; 103 u8 bank_num; 104 struct rockchip_iomux iomux[4]; 105 struct rockchip_drv drv[4]; 106 enum rockchip_pin_pull_type pull_type[4]; 107 u32 recalced_mask; 108 u32 route_mask; 109 }; 110 111 #define PIN_BANK(id, pins, label) \ 112 { \ 113 .bank_num = id, \ 114 .nr_pins = pins, \ 115 .name = label, \ 116 .iomux = { \ 117 { .offset = -1 }, \ 118 { .offset = -1 }, \ 119 { .offset = -1 }, \ 120 { .offset = -1 }, \ 121 }, \ 122 } 123 124 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ 125 { \ 126 .bank_num = id, \ 127 .nr_pins = pins, \ 128 .name = label, \ 129 .iomux = { \ 130 { .type = iom0, .offset = -1 }, \ 131 { .type = iom1, .offset = -1 }, \ 132 { .type = iom2, .offset = -1 }, \ 133 { .type = iom3, .offset = -1 }, \ 134 }, \ 135 } 136 137 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ 138 { \ 139 .bank_num = id, \ 140 .nr_pins = pins, \ 141 .name = label, \ 142 .iomux = { \ 143 { .offset = -1 }, \ 144 { .offset = -1 }, \ 145 { .offset = -1 }, \ 146 { .offset = -1 }, \ 147 }, \ 148 .drv = { \ 149 { .drv_type = type0, .offset = -1 }, \ 150 { .drv_type = type1, .offset = -1 }, \ 151 { .drv_type = type2, .offset = -1 }, \ 152 { .drv_type = type3, .offset = -1 }, \ 153 }, \ 154 } 155 156 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ 157 drv2, drv3, pull0, pull1, \ 158 pull2, pull3) \ 159 { \ 160 .bank_num = id, \ 161 .nr_pins = pins, \ 162 .name = label, \ 163 .iomux = { \ 164 { .offset = -1 }, \ 165 { .offset = -1 }, \ 166 { .offset = -1 }, \ 167 { .offset = -1 }, \ 168 }, \ 169 .drv = { \ 170 { .drv_type = drv0, .offset = -1 }, \ 171 { .drv_type = drv1, .offset = -1 }, \ 172 { .drv_type = drv2, .offset = -1 }, \ 173 { .drv_type = drv3, .offset = -1 }, \ 174 }, \ 175 .pull_type[0] = pull0, \ 176 .pull_type[1] = pull1, \ 177 .pull_type[2] = pull2, \ 178 .pull_type[3] = pull3, \ 179 } 180 181 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ 182 iom2, iom3, drv0, drv1, drv2, \ 183 drv3, offset0, offset1, \ 184 offset2, offset3) \ 185 { \ 186 .bank_num = id, \ 187 .nr_pins = pins, \ 188 .name = label, \ 189 .iomux = { \ 190 { .type = iom0, .offset = -1 }, \ 191 { .type = iom1, .offset = -1 }, \ 192 { .type = iom2, .offset = -1 }, \ 193 { .type = iom3, .offset = -1 }, \ 194 }, \ 195 .drv = { \ 196 { .drv_type = drv0, .offset = offset0 }, \ 197 { .drv_type = drv1, .offset = offset1 }, \ 198 { .drv_type = drv2, .offset = offset2 }, \ 199 { .drv_type = drv3, .offset = offset3 }, \ 200 }, \ 201 } 202 203 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ 204 label, iom0, iom1, iom2, \ 205 iom3, drv0, drv1, drv2, \ 206 drv3, offset0, offset1, \ 207 offset2, offset3, pull0, \ 208 pull1, pull2, pull3) \ 209 { \ 210 .bank_num = id, \ 211 .nr_pins = pins, \ 212 .name = label, \ 213 .iomux = { \ 214 { .type = iom0, .offset = -1 }, \ 215 { .type = iom1, .offset = -1 }, \ 216 { .type = iom2, .offset = -1 }, \ 217 { .type = iom3, .offset = -1 }, \ 218 }, \ 219 .drv = { \ 220 { .drv_type = drv0, .offset = offset0 }, \ 221 { .drv_type = drv1, .offset = offset1 }, \ 222 { .drv_type = drv2, .offset = offset2 }, \ 223 { .drv_type = drv3, .offset = offset3 }, \ 224 }, \ 225 .pull_type[0] = pull0, \ 226 .pull_type[1] = pull1, \ 227 .pull_type[2] = pull2, \ 228 .pull_type[3] = pull3, \ 229 } 230 231 /** 232 * struct rockchip_mux_recalced_data: represent a pin iomux data. 233 * @num: bank number. 234 * @pin: pin number. 235 * @bit: index at register. 236 * @reg: register offset. 237 * @mask: mask bit 238 */ 239 struct rockchip_mux_recalced_data { 240 u8 num; 241 u8 pin; 242 u32 reg; 243 u8 bit; 244 u8 mask; 245 }; 246 247 /** 248 * struct rockchip_mux_recalced_data: represent a pin iomux data. 249 * @bank_num: bank number. 250 * @pin: index at register or used to calc index. 251 * @func: the min pin. 252 * @route_offset: the max pin. 253 * @route_val: the register offset. 254 */ 255 struct rockchip_mux_route_data { 256 u8 bank_num; 257 u8 pin; 258 u8 func; 259 u32 route_offset; 260 u32 route_val; 261 }; 262 263 /** 264 */ 265 struct rockchip_pin_ctrl { 266 struct rockchip_pin_bank *pin_banks; 267 u32 nr_banks; 268 u32 nr_pins; 269 char *label; 270 enum rockchip_pinctrl_type type; 271 int grf_mux_offset; 272 int pmu_mux_offset; 273 int grf_drv_offset; 274 int pmu_drv_offset; 275 struct rockchip_mux_recalced_data *iomux_recalced; 276 u32 niomux_recalced; 277 struct rockchip_mux_route_data *iomux_routes; 278 u32 niomux_routes; 279 280 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, 281 int pin_num, struct regmap **regmap, 282 int *reg, u8 *bit); 283 void (*drv_calc_reg)(struct rockchip_pin_bank *bank, 284 int pin_num, struct regmap **regmap, 285 int *reg, u8 *bit); 286 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, 287 int pin_num, struct regmap **regmap, 288 int *reg, u8 *bit); 289 }; 290 291 /** 292 */ 293 struct rockchip_pinctrl_priv { 294 struct rockchip_pin_ctrl *ctrl; 295 struct regmap *regmap_base; 296 struct regmap *regmap_pmu; 297 298 }; 299 300 static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin) 301 { 302 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 303 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 304 305 if (bank >= ctrl->nr_banks) { 306 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); 307 return -EINVAL; 308 } 309 310 if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) { 311 debug("pin conf pin %d >= %d\n", pin, 312 MAX_ROCKCHIP_GPIO_PER_BANK); 313 return -EINVAL; 314 } 315 316 return 0; 317 } 318 319 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { 320 { 321 .num = 1, 322 .pin = 0, 323 .reg = 0x418, 324 .bit = 0, 325 .mask = 0x3 326 }, { 327 .num = 1, 328 .pin = 1, 329 .reg = 0x418, 330 .bit = 2, 331 .mask = 0x3 332 }, { 333 .num = 1, 334 .pin = 2, 335 .reg = 0x418, 336 .bit = 4, 337 .mask = 0x3 338 }, { 339 .num = 1, 340 .pin = 3, 341 .reg = 0x418, 342 .bit = 6, 343 .mask = 0x3 344 }, { 345 .num = 1, 346 .pin = 4, 347 .reg = 0x418, 348 .bit = 8, 349 .mask = 0x3 350 }, { 351 .num = 1, 352 .pin = 5, 353 .reg = 0x418, 354 .bit = 10, 355 .mask = 0x3 356 }, { 357 .num = 1, 358 .pin = 6, 359 .reg = 0x418, 360 .bit = 12, 361 .mask = 0x3 362 }, { 363 .num = 1, 364 .pin = 7, 365 .reg = 0x418, 366 .bit = 14, 367 .mask = 0x3 368 }, { 369 .num = 1, 370 .pin = 8, 371 .reg = 0x41c, 372 .bit = 0, 373 .mask = 0x3 374 }, { 375 .num = 1, 376 .pin = 9, 377 .reg = 0x41c, 378 .bit = 2, 379 .mask = 0x3 380 }, 381 }; 382 383 static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 384 { 385 .num = 2, 386 .pin = 20, 387 .reg = 0xe8, 388 .bit = 0, 389 .mask = 0x7 390 }, { 391 .num = 2, 392 .pin = 21, 393 .reg = 0xe8, 394 .bit = 4, 395 .mask = 0x7 396 }, { 397 .num = 2, 398 .pin = 22, 399 .reg = 0xe8, 400 .bit = 8, 401 .mask = 0x7 402 }, { 403 .num = 2, 404 .pin = 23, 405 .reg = 0xe8, 406 .bit = 12, 407 .mask = 0x7 408 }, { 409 .num = 2, 410 .pin = 24, 411 .reg = 0xd4, 412 .bit = 12, 413 .mask = 0x7 414 }, 415 }; 416 417 static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { 418 { 419 .num = 1, 420 .pin = 14, 421 .reg = 0x28, 422 .bit = 12, 423 .mask = 0x7 424 }, { 425 .num = 1, 426 .pin = 15, 427 .reg = 0x2c, 428 .bit = 0, 429 .mask = 0x3 430 }, { 431 .num = 1, 432 .pin = 18, 433 .reg = 0x30, 434 .bit = 4, 435 .mask = 0x7 436 }, { 437 .num = 1, 438 .pin = 19, 439 .reg = 0x30, 440 .bit = 8, 441 .mask = 0x7 442 }, { 443 .num = 1, 444 .pin = 20, 445 .reg = 0x30, 446 .bit = 12, 447 .mask = 0x7 448 }, { 449 .num = 1, 450 .pin = 21, 451 .reg = 0x34, 452 .bit = 0, 453 .mask = 0x7 454 }, { 455 .num = 1, 456 .pin = 22, 457 .reg = 0x34, 458 .bit = 4, 459 .mask = 0x7 460 }, { 461 .num = 1, 462 .pin = 23, 463 .reg = 0x34, 464 .bit = 8, 465 .mask = 0x7 466 }, { 467 .num = 3, 468 .pin = 12, 469 .reg = 0x68, 470 .bit = 8, 471 .mask = 0x7 472 }, { 473 .num = 3, 474 .pin = 13, 475 .reg = 0x68, 476 .bit = 12, 477 .mask = 0x7 478 }, 479 }; 480 481 static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { 482 { 483 .num = 2, 484 .pin = 12, 485 .reg = 0x24, 486 .bit = 8, 487 .mask = 0x3 488 }, { 489 .num = 2, 490 .pin = 15, 491 .reg = 0x28, 492 .bit = 0, 493 .mask = 0x7 494 }, { 495 .num = 2, 496 .pin = 23, 497 .reg = 0x30, 498 .bit = 14, 499 .mask = 0x3 500 }, 501 }; 502 503 static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, 504 int *reg, u8 *bit, int *mask) 505 { 506 struct rockchip_pinctrl_priv *priv = bank->priv; 507 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 508 struct rockchip_mux_recalced_data *data; 509 int i; 510 511 for (i = 0; i < ctrl->niomux_recalced; i++) { 512 data = &ctrl->iomux_recalced[i]; 513 if (data->num == bank->bank_num && 514 data->pin == pin) 515 break; 516 } 517 518 if (i >= ctrl->niomux_recalced) 519 return; 520 521 *reg = data->reg; 522 *mask = data->mask; 523 *bit = data->bit; 524 } 525 526 static struct rockchip_mux_route_data px30_mux_route_data[] = { 527 { 528 /* cif-d2m0 */ 529 .bank_num = 2, 530 .pin = 0, 531 .func = 1, 532 .route_offset = 0x184, 533 .route_val = BIT(16 + 7), 534 }, { 535 /* cif-d2m1 */ 536 .bank_num = 3, 537 .pin = 3, 538 .func = 3, 539 .route_offset = 0x184, 540 .route_val = BIT(16 + 7) | BIT(7), 541 }, { 542 /* pdm-m0 */ 543 .bank_num = 3, 544 .pin = 22, 545 .func = 2, 546 .route_offset = 0x184, 547 .route_val = BIT(16 + 8), 548 }, { 549 /* pdm-m1 */ 550 .bank_num = 2, 551 .pin = 22, 552 .func = 1, 553 .route_offset = 0x184, 554 .route_val = BIT(16 + 8) | BIT(8), 555 }, { 556 /* uart2-rxm0 */ 557 .bank_num = 1, 558 .pin = 27, 559 .func = 2, 560 .route_offset = 0x184, 561 .route_val = BIT(16 + 10), 562 }, { 563 /* uart2-rxm1 */ 564 .bank_num = 2, 565 .pin = 14, 566 .func = 2, 567 .route_offset = 0x184, 568 .route_val = BIT(16 + 10) | BIT(10), 569 }, { 570 /* uart3-rxm0 */ 571 .bank_num = 0, 572 .pin = 17, 573 .func = 2, 574 .route_offset = 0x184, 575 .route_val = BIT(16 + 9), 576 }, { 577 /* uart3-rxm1 */ 578 .bank_num = 1, 579 .pin = 15, 580 .func = 2, 581 .route_offset = 0x184, 582 .route_val = BIT(16 + 9) | BIT(9), 583 }, 584 }; 585 586 static struct rockchip_mux_route_data rk3128_mux_route_data[] = { 587 { 588 /* spi-0 */ 589 .bank_num = 1, 590 .pin = 10, 591 .func = 1, 592 .route_offset = 0x144, 593 .route_val = BIT(16 + 3) | BIT(16 + 4), 594 }, { 595 /* spi-1 */ 596 .bank_num = 1, 597 .pin = 27, 598 .func = 3, 599 .route_offset = 0x144, 600 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), 601 }, { 602 /* spi-2 */ 603 .bank_num = 0, 604 .pin = 13, 605 .func = 2, 606 .route_offset = 0x144, 607 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), 608 }, { 609 /* i2s-0 */ 610 .bank_num = 1, 611 .pin = 5, 612 .func = 1, 613 .route_offset = 0x144, 614 .route_val = BIT(16 + 5), 615 }, { 616 /* i2s-1 */ 617 .bank_num = 0, 618 .pin = 14, 619 .func = 1, 620 .route_offset = 0x144, 621 .route_val = BIT(16 + 5) | BIT(5), 622 }, { 623 /* emmc-0 */ 624 .bank_num = 1, 625 .pin = 22, 626 .func = 2, 627 .route_offset = 0x144, 628 .route_val = BIT(16 + 6), 629 }, { 630 /* emmc-1 */ 631 .bank_num = 2, 632 .pin = 4, 633 .func = 2, 634 .route_offset = 0x144, 635 .route_val = BIT(16 + 6) | BIT(6), 636 }, 637 }; 638 639 static struct rockchip_mux_route_data rk3228_mux_route_data[] = { 640 { 641 /* pwm0-0 */ 642 .bank_num = 0, 643 .pin = 26, 644 .func = 1, 645 .route_offset = 0x50, 646 .route_val = BIT(16), 647 }, { 648 /* pwm0-1 */ 649 .bank_num = 3, 650 .pin = 21, 651 .func = 1, 652 .route_offset = 0x50, 653 .route_val = BIT(16) | BIT(0), 654 }, { 655 /* pwm1-0 */ 656 .bank_num = 0, 657 .pin = 27, 658 .func = 1, 659 .route_offset = 0x50, 660 .route_val = BIT(16 + 1), 661 }, { 662 /* pwm1-1 */ 663 .bank_num = 0, 664 .pin = 30, 665 .func = 2, 666 .route_offset = 0x50, 667 .route_val = BIT(16 + 1) | BIT(1), 668 }, { 669 /* pwm2-0 */ 670 .bank_num = 0, 671 .pin = 28, 672 .func = 1, 673 .route_offset = 0x50, 674 .route_val = BIT(16 + 2), 675 }, { 676 /* pwm2-1 */ 677 .bank_num = 1, 678 .pin = 12, 679 .func = 2, 680 .route_offset = 0x50, 681 .route_val = BIT(16 + 2) | BIT(2), 682 }, { 683 /* pwm3-0 */ 684 .bank_num = 3, 685 .pin = 26, 686 .func = 1, 687 .route_offset = 0x50, 688 .route_val = BIT(16 + 3), 689 }, { 690 /* pwm3-1 */ 691 .bank_num = 1, 692 .pin = 11, 693 .func = 2, 694 .route_offset = 0x50, 695 .route_val = BIT(16 + 3) | BIT(3), 696 }, { 697 /* sdio-0_d0 */ 698 .bank_num = 1, 699 .pin = 1, 700 .func = 1, 701 .route_offset = 0x50, 702 .route_val = BIT(16 + 4), 703 }, { 704 /* sdio-1_d0 */ 705 .bank_num = 3, 706 .pin = 2, 707 .func = 1, 708 .route_offset = 0x50, 709 .route_val = BIT(16 + 4) | BIT(4), 710 }, { 711 /* spi-0_rx */ 712 .bank_num = 0, 713 .pin = 13, 714 .func = 2, 715 .route_offset = 0x50, 716 .route_val = BIT(16 + 5), 717 }, { 718 /* spi-1_rx */ 719 .bank_num = 2, 720 .pin = 0, 721 .func = 2, 722 .route_offset = 0x50, 723 .route_val = BIT(16 + 5) | BIT(5), 724 }, { 725 /* emmc-0_cmd */ 726 .bank_num = 1, 727 .pin = 22, 728 .func = 2, 729 .route_offset = 0x50, 730 .route_val = BIT(16 + 7), 731 }, { 732 /* emmc-1_cmd */ 733 .bank_num = 2, 734 .pin = 4, 735 .func = 2, 736 .route_offset = 0x50, 737 .route_val = BIT(16 + 7) | BIT(7), 738 }, { 739 /* uart2-0_rx */ 740 .bank_num = 1, 741 .pin = 19, 742 .func = 2, 743 .route_offset = 0x50, 744 .route_val = BIT(16 + 8), 745 }, { 746 /* uart2-1_rx */ 747 .bank_num = 1, 748 .pin = 10, 749 .func = 2, 750 .route_offset = 0x50, 751 .route_val = BIT(16 + 8) | BIT(8), 752 }, { 753 /* uart1-0_rx */ 754 .bank_num = 1, 755 .pin = 10, 756 .func = 1, 757 .route_offset = 0x50, 758 .route_val = BIT(16 + 11), 759 }, { 760 /* uart1-1_rx */ 761 .bank_num = 3, 762 .pin = 13, 763 .func = 1, 764 .route_offset = 0x50, 765 .route_val = BIT(16 + 11) | BIT(11), 766 }, 767 }; 768 769 static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 770 { 771 /* edphdmi_cecinoutt1 */ 772 .bank_num = 7, 773 .pin = 16, 774 .func = 2, 775 .route_offset = 0x264, 776 .route_val = BIT(16 + 12) | BIT(12), 777 }, { 778 /* edphdmi_cecinout */ 779 .bank_num = 7, 780 .pin = 23, 781 .func = 4, 782 .route_offset = 0x264, 783 .route_val = BIT(16 + 12), 784 }, 785 }; 786 787 static struct rockchip_mux_route_data rk3308_mux_route_data[] = { 788 { 789 /* uart2_rxm0 */ 790 .bank_num = 1, 791 .pin = 22, 792 .func = 2, 793 .route_offset = 0x314, 794 .route_val = BIT(16 + 2) | BIT(16 + 3), 795 }, { 796 /* uart2_rxm1 */ 797 .bank_num = 4, 798 .pin = 26, 799 .func = 2, 800 .route_offset = 0x314, 801 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), 802 }, { 803 /* i2c3_sdam0 */ 804 .bank_num = 0, 805 .pin = 23, 806 .func = 2, 807 .route_offset = 0x314, 808 .route_val = BIT(16 + 4), 809 }, { 810 /* i2c3_sdam1 */ 811 .bank_num = 3, 812 .pin = 12, 813 .func = 2, 814 .route_offset = 0x314, 815 .route_val = BIT(16 + 4) | BIT(4), 816 }, 817 }; 818 819 static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 820 { 821 /* uart2dbg_rxm0 */ 822 .bank_num = 1, 823 .pin = 1, 824 .func = 2, 825 .route_offset = 0x50, 826 .route_val = BIT(16) | BIT(16 + 1), 827 }, { 828 /* uart2dbg_rxm1 */ 829 .bank_num = 2, 830 .pin = 1, 831 .func = 1, 832 .route_offset = 0x50, 833 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 834 }, { 835 /* gmac-m1_rxd0 */ 836 .bank_num = 1, 837 .pin = 11, 838 .func = 2, 839 .route_offset = 0x50, 840 .route_val = BIT(16 + 2) | BIT(2), 841 }, { 842 /* gmac-m1-optimized_rxd3 */ 843 .bank_num = 1, 844 .pin = 14, 845 .func = 2, 846 .route_offset = 0x50, 847 .route_val = BIT(16 + 10) | BIT(10), 848 }, { 849 /* pdm_sdi0m0 */ 850 .bank_num = 2, 851 .pin = 19, 852 .func = 2, 853 .route_offset = 0x50, 854 .route_val = BIT(16 + 3), 855 }, { 856 /* pdm_sdi0m1 */ 857 .bank_num = 1, 858 .pin = 23, 859 .func = 3, 860 .route_offset = 0x50, 861 .route_val = BIT(16 + 3) | BIT(3), 862 }, { 863 /* spi_rxdm2 */ 864 .bank_num = 3, 865 .pin = 2, 866 .func = 4, 867 .route_offset = 0x50, 868 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), 869 }, { 870 /* i2s2_sdim0 */ 871 .bank_num = 1, 872 .pin = 24, 873 .func = 1, 874 .route_offset = 0x50, 875 .route_val = BIT(16 + 6), 876 }, { 877 /* i2s2_sdim1 */ 878 .bank_num = 3, 879 .pin = 2, 880 .func = 6, 881 .route_offset = 0x50, 882 .route_val = BIT(16 + 6) | BIT(6), 883 }, { 884 /* card_iom1 */ 885 .bank_num = 2, 886 .pin = 22, 887 .func = 3, 888 .route_offset = 0x50, 889 .route_val = BIT(16 + 7) | BIT(7), 890 }, { 891 /* tsp_d5m1 */ 892 .bank_num = 2, 893 .pin = 16, 894 .func = 3, 895 .route_offset = 0x50, 896 .route_val = BIT(16 + 8) | BIT(8), 897 }, { 898 /* cif_data5m1 */ 899 .bank_num = 2, 900 .pin = 16, 901 .func = 4, 902 .route_offset = 0x50, 903 .route_val = BIT(16 + 9) | BIT(9), 904 }, 905 }; 906 907 static struct rockchip_mux_route_data rk3399_mux_route_data[] = { 908 { 909 /* uart2dbga_rx */ 910 .bank_num = 4, 911 .pin = 8, 912 .func = 2, 913 .route_offset = 0xe21c, 914 .route_val = BIT(16 + 10) | BIT(16 + 11), 915 }, { 916 /* uart2dbgb_rx */ 917 .bank_num = 4, 918 .pin = 16, 919 .func = 2, 920 .route_offset = 0xe21c, 921 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), 922 }, { 923 /* uart2dbgc_rx */ 924 .bank_num = 4, 925 .pin = 19, 926 .func = 1, 927 .route_offset = 0xe21c, 928 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), 929 }, { 930 /* pcie_clkreqn */ 931 .bank_num = 2, 932 .pin = 26, 933 .func = 2, 934 .route_offset = 0xe21c, 935 .route_val = BIT(16 + 14), 936 }, { 937 /* pcie_clkreqnb */ 938 .bank_num = 4, 939 .pin = 24, 940 .func = 1, 941 .route_offset = 0xe21c, 942 .route_val = BIT(16 + 14) | BIT(14), 943 }, 944 }; 945 946 static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, 947 int mux, u32 *reg, u32 *value) 948 { 949 struct rockchip_pinctrl_priv *priv = bank->priv; 950 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 951 struct rockchip_mux_route_data *data; 952 int i; 953 954 for (i = 0; i < ctrl->niomux_routes; i++) { 955 data = &ctrl->iomux_routes[i]; 956 if ((data->bank_num == bank->bank_num) && 957 (data->pin == pin) && (data->func == mux)) 958 break; 959 } 960 961 if (i >= ctrl->niomux_routes) 962 return false; 963 964 *reg = data->route_offset; 965 *value = data->route_val; 966 967 return true; 968 } 969 970 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) 971 { 972 struct rockchip_pinctrl_priv *priv = bank->priv; 973 int iomux_num = (pin / 8); 974 struct regmap *regmap; 975 unsigned int val; 976 int reg, ret, mask, mux_type; 977 u8 bit; 978 979 if (iomux_num > 3) 980 return -EINVAL; 981 982 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 983 debug("pin %d is unrouted\n", pin); 984 return -EINVAL; 985 } 986 987 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 988 return RK_FUNC_GPIO; 989 990 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 991 ? priv->regmap_pmu : priv->regmap_base; 992 993 /* get basic quadrupel of mux registers and the correct reg inside */ 994 mux_type = bank->iomux[iomux_num].type; 995 reg = bank->iomux[iomux_num].offset; 996 if (mux_type & IOMUX_WIDTH_4BIT) { 997 if ((pin % 8) >= 4) 998 reg += 0x4; 999 bit = (pin % 4) * 4; 1000 mask = 0xf; 1001 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1002 if ((pin % 8) >= 5) 1003 reg += 0x4; 1004 bit = (pin % 8 % 5) * 3; 1005 mask = 0x7; 1006 } else { 1007 bit = (pin % 8) * 2; 1008 mask = 0x3; 1009 } 1010 1011 if (bank->recalced_mask & BIT(pin)) 1012 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1013 1014 ret = regmap_read(regmap, reg, &val); 1015 if (ret) 1016 return ret; 1017 1018 return ((val >> bit) & mask); 1019 } 1020 1021 static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, 1022 int index) 1023 { struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1024 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1025 1026 return rockchip_get_mux(&ctrl->pin_banks[banknum], index); 1027 } 1028 1029 static int rockchip_verify_mux(struct rockchip_pin_bank *bank, 1030 int pin, int mux) 1031 { 1032 int iomux_num = (pin / 8); 1033 1034 if (iomux_num > 3) 1035 return -EINVAL; 1036 1037 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { 1038 debug("pin %d is unrouted\n", pin); 1039 return -EINVAL; 1040 } 1041 1042 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { 1043 if (mux != IOMUX_GPIO_ONLY) { 1044 debug("pin %d only supports a gpio mux\n", pin); 1045 return -ENOTSUPP; 1046 } 1047 } 1048 1049 return 0; 1050 } 1051 1052 /* 1053 * Set a new mux function for a pin. 1054 * 1055 * The register is divided into the upper and lower 16 bit. When changing 1056 * a value, the previous register value is not read and changed. Instead 1057 * it seems the changed bits are marked in the upper 16 bit, while the 1058 * changed value gets set in the same offset in the lower 16 bit. 1059 * All pin settings seem to be 2 bit wide in both the upper and lower 1060 * parts. 1061 * @bank: pin bank to change 1062 * @pin: pin to change 1063 * @mux: new mux function to set 1064 */ 1065 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 1066 { 1067 struct rockchip_pinctrl_priv *priv = bank->priv; 1068 int iomux_num = (pin / 8); 1069 struct regmap *regmap; 1070 int reg, ret, mask, mux_type; 1071 u8 bit; 1072 u32 data, route_reg, route_val; 1073 1074 ret = rockchip_verify_mux(bank, pin, mux); 1075 if (ret < 0) 1076 return ret; 1077 1078 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) 1079 return 0; 1080 1081 debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); 1082 1083 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 1084 ? priv->regmap_pmu : priv->regmap_base; 1085 1086 /* get basic quadrupel of mux registers and the correct reg inside */ 1087 mux_type = bank->iomux[iomux_num].type; 1088 reg = bank->iomux[iomux_num].offset; 1089 if (mux_type & IOMUX_WIDTH_4BIT) { 1090 if ((pin % 8) >= 4) 1091 reg += 0x4; 1092 bit = (pin % 4) * 4; 1093 mask = 0xf; 1094 } else if (mux_type & IOMUX_WIDTH_3BIT) { 1095 if ((pin % 8) >= 5) 1096 reg += 0x4; 1097 bit = (pin % 8 % 5) * 3; 1098 mask = 0x7; 1099 } else { 1100 bit = (pin % 8) * 2; 1101 mask = 0x3; 1102 } 1103 1104 if (bank->recalced_mask & BIT(pin)) 1105 rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); 1106 1107 if (bank->route_mask & BIT(pin)) { 1108 if (rockchip_get_mux_route(bank, pin, mux, &route_reg, 1109 &route_val)) { 1110 ret = regmap_write(regmap, route_reg, route_val); 1111 if (ret) 1112 return ret; 1113 } 1114 } 1115 1116 data = (mask << (bit + 16)); 1117 data |= (mux & mask) << bit; 1118 ret = regmap_write(regmap, reg, data); 1119 1120 return ret; 1121 } 1122 1123 #define PX30_PULL_PMU_OFFSET 0x10 1124 #define PX30_PULL_GRF_OFFSET 0x60 1125 #define PX30_PULL_BITS_PER_PIN 2 1126 #define PX30_PULL_PINS_PER_REG 8 1127 #define PX30_PULL_BANK_STRIDE 16 1128 1129 static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1130 int pin_num, struct regmap **regmap, 1131 int *reg, u8 *bit) 1132 { 1133 struct rockchip_pinctrl_priv *priv = bank->priv; 1134 1135 /* The first 32 pins of the first bank are located in PMU */ 1136 if (bank->bank_num == 0) { 1137 *regmap = priv->regmap_pmu; 1138 *reg = PX30_PULL_PMU_OFFSET; 1139 } else { 1140 *regmap = priv->regmap_base; 1141 *reg = PX30_PULL_GRF_OFFSET; 1142 1143 /* correct the offset, as we're starting with the 2nd bank */ 1144 *reg -= 0x10; 1145 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; 1146 } 1147 1148 *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); 1149 *bit = (pin_num % PX30_PULL_PINS_PER_REG); 1150 *bit *= PX30_PULL_BITS_PER_PIN; 1151 } 1152 1153 #define PX30_DRV_PMU_OFFSET 0x20 1154 #define PX30_DRV_GRF_OFFSET 0xf0 1155 #define PX30_DRV_BITS_PER_PIN 2 1156 #define PX30_DRV_PINS_PER_REG 8 1157 #define PX30_DRV_BANK_STRIDE 16 1158 1159 static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1160 int pin_num, struct regmap **regmap, 1161 int *reg, u8 *bit) 1162 { 1163 struct rockchip_pinctrl_priv *priv = bank->priv; 1164 1165 /* The first 32 pins of the first bank are located in PMU */ 1166 if (bank->bank_num == 0) { 1167 *regmap = priv->regmap_pmu; 1168 *reg = PX30_DRV_PMU_OFFSET; 1169 } else { 1170 *regmap = priv->regmap_base; 1171 *reg = PX30_DRV_GRF_OFFSET; 1172 1173 /* correct the offset, as we're starting with the 2nd bank */ 1174 *reg -= 0x10; 1175 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; 1176 } 1177 1178 *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); 1179 *bit = (pin_num % PX30_DRV_PINS_PER_REG); 1180 *bit *= PX30_DRV_BITS_PER_PIN; 1181 } 1182 1183 #define PX30_SCHMITT_PMU_OFFSET 0x38 1184 #define PX30_SCHMITT_GRF_OFFSET 0xc0 1185 #define PX30_SCHMITT_PINS_PER_PMU_REG 16 1186 #define PX30_SCHMITT_BANK_STRIDE 16 1187 #define PX30_SCHMITT_PINS_PER_GRF_REG 8 1188 1189 static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1190 int pin_num, 1191 struct regmap **regmap, 1192 int *reg, u8 *bit) 1193 { 1194 struct rockchip_pinctrl_priv *priv = bank->priv; 1195 int pins_per_reg; 1196 1197 if (bank->bank_num == 0) { 1198 *regmap = priv->regmap_pmu; 1199 *reg = PX30_SCHMITT_PMU_OFFSET; 1200 pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; 1201 } else { 1202 *regmap = priv->regmap_base; 1203 *reg = PX30_SCHMITT_GRF_OFFSET; 1204 pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; 1205 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; 1206 } 1207 *reg += ((pin_num / pins_per_reg) * 4); 1208 *bit = pin_num % pins_per_reg; 1209 1210 return 0; 1211 } 1212 1213 #define RV1108_PULL_PMU_OFFSET 0x10 1214 #define RV1108_PULL_OFFSET 0x110 1215 #define RV1108_PULL_PINS_PER_REG 8 1216 #define RV1108_PULL_BITS_PER_PIN 2 1217 #define RV1108_PULL_BANK_STRIDE 16 1218 1219 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1220 int pin_num, struct regmap **regmap, 1221 int *reg, u8 *bit) 1222 { 1223 struct rockchip_pinctrl_priv *priv = bank->priv; 1224 1225 /* The first 24 pins of the first bank are located in PMU */ 1226 if (bank->bank_num == 0) { 1227 *regmap = priv->regmap_pmu; 1228 *reg = RV1108_PULL_PMU_OFFSET; 1229 } else { 1230 *reg = RV1108_PULL_OFFSET; 1231 *regmap = priv->regmap_base; 1232 /* correct the offset, as we're starting with the 2nd bank */ 1233 *reg -= 0x10; 1234 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; 1235 } 1236 1237 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); 1238 *bit = (pin_num % RV1108_PULL_PINS_PER_REG); 1239 *bit *= RV1108_PULL_BITS_PER_PIN; 1240 } 1241 1242 #define RV1108_DRV_PMU_OFFSET 0x20 1243 #define RV1108_DRV_GRF_OFFSET 0x210 1244 #define RV1108_DRV_BITS_PER_PIN 2 1245 #define RV1108_DRV_PINS_PER_REG 8 1246 #define RV1108_DRV_BANK_STRIDE 16 1247 1248 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1249 int pin_num, struct regmap **regmap, 1250 int *reg, u8 *bit) 1251 { 1252 struct rockchip_pinctrl_priv *priv = bank->priv; 1253 1254 /* The first 24 pins of the first bank are located in PMU */ 1255 if (bank->bank_num == 0) { 1256 *regmap = priv->regmap_pmu; 1257 *reg = RV1108_DRV_PMU_OFFSET; 1258 } else { 1259 *regmap = priv->regmap_base; 1260 *reg = RV1108_DRV_GRF_OFFSET; 1261 1262 /* correct the offset, as we're starting with the 2nd bank */ 1263 *reg -= 0x10; 1264 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; 1265 } 1266 1267 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); 1268 *bit = pin_num % RV1108_DRV_PINS_PER_REG; 1269 *bit *= RV1108_DRV_BITS_PER_PIN; 1270 } 1271 1272 #define RV1108_SCHMITT_PMU_OFFSET 0x30 1273 #define RV1108_SCHMITT_GRF_OFFSET 0x388 1274 #define RV1108_SCHMITT_BANK_STRIDE 8 1275 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 1276 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 1277 1278 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1279 int pin_num, 1280 struct regmap **regmap, 1281 int *reg, u8 *bit) 1282 { 1283 struct rockchip_pinctrl_priv *priv = bank->priv; 1284 int pins_per_reg; 1285 1286 if (bank->bank_num == 0) { 1287 *regmap = priv->regmap_pmu; 1288 *reg = RV1108_SCHMITT_PMU_OFFSET; 1289 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; 1290 } else { 1291 *regmap = priv->regmap_base; 1292 *reg = RV1108_SCHMITT_GRF_OFFSET; 1293 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; 1294 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; 1295 } 1296 *reg += ((pin_num / pins_per_reg) * 4); 1297 *bit = pin_num % pins_per_reg; 1298 1299 return 0; 1300 } 1301 1302 #define RK2928_PULL_OFFSET 0x118 1303 #define RK2928_PULL_PINS_PER_REG 16 1304 #define RK2928_PULL_BANK_STRIDE 8 1305 1306 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1307 int pin_num, struct regmap **regmap, 1308 int *reg, u8 *bit) 1309 { 1310 struct rockchip_pinctrl_priv *priv = bank->priv; 1311 1312 *regmap = priv->regmap_base; 1313 *reg = RK2928_PULL_OFFSET; 1314 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1315 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; 1316 1317 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1318 }; 1319 1320 #define RK3128_PULL_OFFSET 0x118 1321 1322 static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1323 int pin_num, struct regmap **regmap, 1324 int *reg, u8 *bit) 1325 { 1326 struct rockchip_pinctrl_priv *priv = bank->priv; 1327 1328 *regmap = priv->regmap_base; 1329 *reg = RK3128_PULL_OFFSET; 1330 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; 1331 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); 1332 1333 *bit = pin_num % RK2928_PULL_PINS_PER_REG; 1334 } 1335 1336 #define RK3188_PULL_OFFSET 0x164 1337 #define RK3188_PULL_BITS_PER_PIN 2 1338 #define RK3188_PULL_PINS_PER_REG 8 1339 #define RK3188_PULL_BANK_STRIDE 16 1340 #define RK3188_PULL_PMU_OFFSET 0x64 1341 1342 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1343 int pin_num, struct regmap **regmap, 1344 int *reg, u8 *bit) 1345 { 1346 struct rockchip_pinctrl_priv *priv = bank->priv; 1347 1348 /* The first 12 pins of the first bank are located elsewhere */ 1349 if (bank->bank_num == 0 && pin_num < 12) { 1350 *regmap = priv->regmap_pmu; 1351 *reg = RK3188_PULL_PMU_OFFSET; 1352 1353 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1354 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1355 *bit *= RK3188_PULL_BITS_PER_PIN; 1356 } else { 1357 *regmap = priv->regmap_base; 1358 *reg = RK3188_PULL_OFFSET; 1359 1360 /* correct the offset, as it is the 2nd pull register */ 1361 *reg -= 4; 1362 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1363 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1364 1365 /* 1366 * The bits in these registers have an inverse ordering 1367 * with the lowest pin being in bits 15:14 and the highest 1368 * pin in bits 1:0 1369 */ 1370 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); 1371 *bit *= RK3188_PULL_BITS_PER_PIN; 1372 } 1373 } 1374 1375 #define RK3288_PULL_OFFSET 0x140 1376 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1377 int pin_num, struct regmap **regmap, 1378 int *reg, u8 *bit) 1379 { 1380 struct rockchip_pinctrl_priv *priv = bank->priv; 1381 1382 /* The first 24 pins of the first bank are located in PMU */ 1383 if (bank->bank_num == 0) { 1384 *regmap = priv->regmap_pmu; 1385 *reg = RK3188_PULL_PMU_OFFSET; 1386 1387 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1388 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1389 *bit *= RK3188_PULL_BITS_PER_PIN; 1390 } else { 1391 *regmap = priv->regmap_base; 1392 *reg = RK3288_PULL_OFFSET; 1393 1394 /* correct the offset, as we're starting with the 2nd bank */ 1395 *reg -= 0x10; 1396 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1397 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1398 1399 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1400 *bit *= RK3188_PULL_BITS_PER_PIN; 1401 } 1402 } 1403 1404 #define RK3288_DRV_PMU_OFFSET 0x70 1405 #define RK3288_DRV_GRF_OFFSET 0x1c0 1406 #define RK3288_DRV_BITS_PER_PIN 2 1407 #define RK3288_DRV_PINS_PER_REG 8 1408 #define RK3288_DRV_BANK_STRIDE 16 1409 1410 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1411 int pin_num, struct regmap **regmap, 1412 int *reg, u8 *bit) 1413 { 1414 struct rockchip_pinctrl_priv *priv = bank->priv; 1415 1416 /* The first 24 pins of the first bank are located in PMU */ 1417 if (bank->bank_num == 0) { 1418 *regmap = priv->regmap_pmu; 1419 *reg = RK3288_DRV_PMU_OFFSET; 1420 1421 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1422 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1423 *bit *= RK3288_DRV_BITS_PER_PIN; 1424 } else { 1425 *regmap = priv->regmap_base; 1426 *reg = RK3288_DRV_GRF_OFFSET; 1427 1428 /* correct the offset, as we're starting with the 2nd bank */ 1429 *reg -= 0x10; 1430 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1431 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1432 1433 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1434 *bit *= RK3288_DRV_BITS_PER_PIN; 1435 } 1436 } 1437 1438 #define RK3228_PULL_OFFSET 0x100 1439 1440 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1441 int pin_num, struct regmap **regmap, 1442 int *reg, u8 *bit) 1443 { 1444 struct rockchip_pinctrl_priv *priv = bank->priv; 1445 1446 *regmap = priv->regmap_base; 1447 *reg = RK3228_PULL_OFFSET; 1448 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1449 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1450 1451 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1452 *bit *= RK3188_PULL_BITS_PER_PIN; 1453 } 1454 1455 #define RK3228_DRV_GRF_OFFSET 0x200 1456 1457 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1458 int pin_num, struct regmap **regmap, 1459 int *reg, u8 *bit) 1460 { 1461 struct rockchip_pinctrl_priv *priv = bank->priv; 1462 1463 *regmap = priv->regmap_base; 1464 *reg = RK3228_DRV_GRF_OFFSET; 1465 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1466 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1467 1468 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1469 *bit *= RK3288_DRV_BITS_PER_PIN; 1470 } 1471 1472 #define RK3308_PULL_OFFSET 0xa0 1473 1474 static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1475 int pin_num, struct regmap **regmap, 1476 int *reg, u8 *bit) 1477 { 1478 struct rockchip_pinctrl_priv *priv = bank->priv; 1479 1480 *regmap = priv->regmap_base; 1481 *reg = RK3308_PULL_OFFSET; 1482 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1483 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1484 1485 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1486 *bit *= RK3188_PULL_BITS_PER_PIN; 1487 } 1488 1489 #define RK3308_DRV_GRF_OFFSET 0x100 1490 1491 static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1492 int pin_num, struct regmap **regmap, 1493 int *reg, u8 *bit) 1494 { 1495 struct rockchip_pinctrl_priv *priv = bank->priv; 1496 1497 *regmap = priv->regmap_base; 1498 *reg = RK3308_DRV_GRF_OFFSET; 1499 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1500 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1501 1502 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1503 *bit *= RK3288_DRV_BITS_PER_PIN; 1504 } 1505 1506 #define RK3308_SCHMITT_PINS_PER_REG 8 1507 #define RK3308_SCHMITT_BANK_STRIDE 16 1508 #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 1509 1510 static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1511 int pin_num, 1512 struct regmap **regmap, 1513 int *reg, u8 *bit) 1514 { 1515 struct rockchip_pinctrl_priv *priv = bank->priv; 1516 1517 *regmap = priv->regmap_base; 1518 *reg = RK3308_SCHMITT_GRF_OFFSET; 1519 1520 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; 1521 *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); 1522 *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; 1523 1524 return 0; 1525 } 1526 1527 #define RK3368_PULL_GRF_OFFSET 0x100 1528 #define RK3368_PULL_PMU_OFFSET 0x10 1529 1530 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1531 int pin_num, struct regmap **regmap, 1532 int *reg, u8 *bit) 1533 { 1534 struct rockchip_pinctrl_priv *priv = bank->priv; 1535 1536 /* The first 32 pins of the first bank are located in PMU */ 1537 if (bank->bank_num == 0) { 1538 *regmap = priv->regmap_pmu; 1539 *reg = RK3368_PULL_PMU_OFFSET; 1540 1541 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1542 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1543 *bit *= RK3188_PULL_BITS_PER_PIN; 1544 } else { 1545 *regmap = priv->regmap_base; 1546 *reg = RK3368_PULL_GRF_OFFSET; 1547 1548 /* correct the offset, as we're starting with the 2nd bank */ 1549 *reg -= 0x10; 1550 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1551 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1552 1553 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1554 *bit *= RK3188_PULL_BITS_PER_PIN; 1555 } 1556 } 1557 1558 #define RK3368_DRV_PMU_OFFSET 0x20 1559 #define RK3368_DRV_GRF_OFFSET 0x200 1560 1561 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1562 int pin_num, struct regmap **regmap, 1563 int *reg, u8 *bit) 1564 { 1565 struct rockchip_pinctrl_priv *priv = bank->priv; 1566 1567 /* The first 32 pins of the first bank are located in PMU */ 1568 if (bank->bank_num == 0) { 1569 *regmap = priv->regmap_pmu; 1570 *reg = RK3368_DRV_PMU_OFFSET; 1571 1572 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1573 *bit = pin_num % RK3288_DRV_PINS_PER_REG; 1574 *bit *= RK3288_DRV_BITS_PER_PIN; 1575 } else { 1576 *regmap = priv->regmap_base; 1577 *reg = RK3368_DRV_GRF_OFFSET; 1578 1579 /* correct the offset, as we're starting with the 2nd bank */ 1580 *reg -= 0x10; 1581 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; 1582 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); 1583 1584 *bit = (pin_num % RK3288_DRV_PINS_PER_REG); 1585 *bit *= RK3288_DRV_BITS_PER_PIN; 1586 } 1587 } 1588 1589 #define RK3399_PULL_GRF_OFFSET 0xe040 1590 #define RK3399_PULL_PMU_OFFSET 0x40 1591 #define RK3399_DRV_3BITS_PER_PIN 3 1592 1593 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 1594 int pin_num, struct regmap **regmap, 1595 int *reg, u8 *bit) 1596 { 1597 struct rockchip_pinctrl_priv *priv = bank->priv; 1598 1599 /* The bank0:16 and bank1:32 pins are located in PMU */ 1600 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { 1601 *regmap = priv->regmap_pmu; 1602 *reg = RK3399_PULL_PMU_OFFSET; 1603 1604 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1605 1606 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1607 *bit = pin_num % RK3188_PULL_PINS_PER_REG; 1608 *bit *= RK3188_PULL_BITS_PER_PIN; 1609 } else { 1610 *regmap = priv->regmap_base; 1611 *reg = RK3399_PULL_GRF_OFFSET; 1612 1613 /* correct the offset, as we're starting with the 3rd bank */ 1614 *reg -= 0x20; 1615 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; 1616 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); 1617 1618 *bit = (pin_num % RK3188_PULL_PINS_PER_REG); 1619 *bit *= RK3188_PULL_BITS_PER_PIN; 1620 } 1621 } 1622 1623 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 1624 int pin_num, struct regmap **regmap, 1625 int *reg, u8 *bit) 1626 { 1627 struct rockchip_pinctrl_priv *priv = bank->priv; 1628 int drv_num = (pin_num / 8); 1629 1630 /* The bank0:16 and bank1:32 pins are located in PMU */ 1631 if ((bank->bank_num == 0) || (bank->bank_num == 1)) 1632 *regmap = priv->regmap_pmu; 1633 else 1634 *regmap = priv->regmap_base; 1635 1636 *reg = bank->drv[drv_num].offset; 1637 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 1638 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) 1639 *bit = (pin_num % 8) * 3; 1640 else 1641 *bit = (pin_num % 8) * 2; 1642 } 1643 1644 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { 1645 { 2, 4, 8, 12, -1, -1, -1, -1 }, 1646 { 3, 6, 9, 12, -1, -1, -1, -1 }, 1647 { 5, 10, 15, 20, -1, -1, -1, -1 }, 1648 { 4, 6, 8, 10, 12, 14, 16, 18 }, 1649 { 4, 7, 10, 13, 16, 19, 22, 26 } 1650 }; 1651 1652 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, 1653 int pin_num, int strength) 1654 { 1655 struct rockchip_pinctrl_priv *priv = bank->priv; 1656 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1657 struct regmap *regmap; 1658 int reg, ret, i; 1659 u32 data, rmask_bits, temp; 1660 u8 bit; 1661 int drv_type = bank->drv[pin_num / 8].drv_type; 1662 1663 debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num, 1664 pin_num, strength); 1665 1666 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); 1667 1668 ret = -EINVAL; 1669 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { 1670 if (rockchip_perpin_drv_list[drv_type][i] == strength) { 1671 ret = i; 1672 break; 1673 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { 1674 ret = rockchip_perpin_drv_list[drv_type][i]; 1675 break; 1676 } 1677 } 1678 1679 if (ret < 0) { 1680 debug("unsupported driver strength %d\n", strength); 1681 return ret; 1682 } 1683 1684 switch (drv_type) { 1685 case DRV_TYPE_IO_1V8_3V0_AUTO: 1686 case DRV_TYPE_IO_3V3_ONLY: 1687 rmask_bits = RK3399_DRV_3BITS_PER_PIN; 1688 switch (bit) { 1689 case 0 ... 12: 1690 /* regular case, nothing to do */ 1691 break; 1692 case 15: 1693 /* 1694 * drive-strength offset is special, as it is spread 1695 * over 2 registers, the bit data[15] contains bit 0 1696 * of the value while temp[1:0] contains bits 2 and 1 1697 */ 1698 data = (ret & 0x1) << 15; 1699 temp = (ret >> 0x1) & 0x3; 1700 1701 data |= BIT(31); 1702 ret = regmap_write(regmap, reg, data); 1703 if (ret) 1704 return ret; 1705 1706 temp |= (0x3 << 16); 1707 reg += 0x4; 1708 ret = regmap_write(regmap, reg, temp); 1709 1710 return ret; 1711 case 18 ... 21: 1712 /* setting fully enclosed in the second register */ 1713 reg += 4; 1714 bit -= 16; 1715 break; 1716 default: 1717 debug("unsupported bit: %d for pinctrl drive type: %d\n", 1718 bit, drv_type); 1719 return -EINVAL; 1720 } 1721 break; 1722 case DRV_TYPE_IO_DEFAULT: 1723 case DRV_TYPE_IO_1V8_OR_3V0: 1724 case DRV_TYPE_IO_1V8_ONLY: 1725 rmask_bits = RK3288_DRV_BITS_PER_PIN; 1726 break; 1727 default: 1728 debug("unsupported pinctrl drive type: %d\n", 1729 drv_type); 1730 return -EINVAL; 1731 } 1732 1733 /* enable the write to the equivalent lower bits */ 1734 data = ((1 << rmask_bits) - 1) << (bit + 16); 1735 data |= (ret << bit); 1736 1737 ret = regmap_write(regmap, reg, data); 1738 return ret; 1739 } 1740 1741 static int rockchip_pull_list[PULL_TYPE_MAX][4] = { 1742 { 1743 PIN_CONFIG_BIAS_DISABLE, 1744 PIN_CONFIG_BIAS_PULL_UP, 1745 PIN_CONFIG_BIAS_PULL_DOWN, 1746 PIN_CONFIG_BIAS_BUS_HOLD 1747 }, 1748 { 1749 PIN_CONFIG_BIAS_DISABLE, 1750 PIN_CONFIG_BIAS_PULL_DOWN, 1751 PIN_CONFIG_BIAS_DISABLE, 1752 PIN_CONFIG_BIAS_PULL_UP 1753 }, 1754 }; 1755 1756 static int rockchip_set_pull(struct rockchip_pin_bank *bank, 1757 int pin_num, int pull) 1758 { 1759 struct rockchip_pinctrl_priv *priv = bank->priv; 1760 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1761 struct regmap *regmap; 1762 int reg, ret, i, pull_type; 1763 u8 bit; 1764 u32 data; 1765 1766 debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num, 1767 pin_num, pull); 1768 1769 /* rk3066b does support any pulls */ 1770 if (ctrl->type == RK3066B) 1771 return pull ? -EINVAL : 0; 1772 1773 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); 1774 1775 switch (ctrl->type) { 1776 case RK2928: 1777 case RK3128: 1778 data = BIT(bit + 16); 1779 if (pull == PIN_CONFIG_BIAS_DISABLE) 1780 data |= BIT(bit); 1781 ret = regmap_write(regmap, reg, data); 1782 break; 1783 case PX30: 1784 case RV1108: 1785 case RK3188: 1786 case RK3288: 1787 case RK3308: 1788 case RK3368: 1789 case RK3399: 1790 pull_type = bank->pull_type[pin_num / 8]; 1791 ret = -EINVAL; 1792 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); 1793 i++) { 1794 if (rockchip_pull_list[pull_type][i] == pull) { 1795 ret = i; 1796 break; 1797 } 1798 } 1799 1800 if (ret < 0) { 1801 debug("unsupported pull setting %d\n", pull); 1802 return ret; 1803 } 1804 1805 /* enable the write to the equivalent lower bits */ 1806 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); 1807 data |= (ret << bit); 1808 1809 ret = regmap_write(regmap, reg, data); 1810 break; 1811 default: 1812 debug("unsupported pinctrl type\n"); 1813 return -EINVAL; 1814 } 1815 1816 return ret; 1817 } 1818 1819 #define RK3328_SCHMITT_BITS_PER_PIN 1 1820 #define RK3328_SCHMITT_PINS_PER_REG 16 1821 #define RK3328_SCHMITT_BANK_STRIDE 8 1822 #define RK3328_SCHMITT_GRF_OFFSET 0x380 1823 1824 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 1825 int pin_num, 1826 struct regmap **regmap, 1827 int *reg, u8 *bit) 1828 { 1829 struct rockchip_pinctrl_priv *priv = bank->priv; 1830 1831 *regmap = priv->regmap_base; 1832 *reg = RK3328_SCHMITT_GRF_OFFSET; 1833 1834 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; 1835 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); 1836 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; 1837 1838 return 0; 1839 } 1840 1841 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, 1842 int pin_num, int enable) 1843 { 1844 struct rockchip_pinctrl_priv *priv = bank->priv; 1845 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1846 struct regmap *regmap; 1847 int reg, ret; 1848 u8 bit; 1849 u32 data; 1850 1851 debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num, 1852 pin_num, enable); 1853 1854 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); 1855 if (ret) 1856 return ret; 1857 1858 /* enable the write to the equivalent lower bits */ 1859 data = BIT(bit + 16) | (enable << bit); 1860 1861 return regmap_write(regmap, reg, data); 1862 } 1863 1864 /* 1865 * Pinconf_ops handling 1866 */ 1867 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 1868 unsigned int pull) 1869 { 1870 switch (ctrl->type) { 1871 case RK2928: 1872 case RK3128: 1873 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || 1874 pull == PIN_CONFIG_BIAS_DISABLE); 1875 case RK3066B: 1876 return pull ? false : true; 1877 case PX30: 1878 case RV1108: 1879 case RK3188: 1880 case RK3288: 1881 case RK3308: 1882 case RK3368: 1883 case RK3399: 1884 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); 1885 } 1886 1887 return false; 1888 } 1889 1890 /* set the pin config settings for a specified pin */ 1891 static int rockchip_pinconf_set(struct rockchip_pin_bank *bank, 1892 u32 pin, u32 param, u32 arg) 1893 { 1894 struct rockchip_pinctrl_priv *priv = bank->priv; 1895 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1896 int rc; 1897 1898 switch (param) { 1899 case PIN_CONFIG_BIAS_DISABLE: 1900 rc = rockchip_set_pull(bank, pin, param); 1901 if (rc) 1902 return rc; 1903 break; 1904 1905 case PIN_CONFIG_BIAS_PULL_UP: 1906 case PIN_CONFIG_BIAS_PULL_DOWN: 1907 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 1908 case PIN_CONFIG_BIAS_BUS_HOLD: 1909 if (!rockchip_pinconf_pull_valid(ctrl, param)) 1910 return -ENOTSUPP; 1911 1912 if (!arg) 1913 return -EINVAL; 1914 1915 rc = rockchip_set_pull(bank, pin, param); 1916 if (rc) 1917 return rc; 1918 break; 1919 1920 case PIN_CONFIG_DRIVE_STRENGTH: 1921 if (!ctrl->drv_calc_reg) 1922 return -ENOTSUPP; 1923 1924 rc = rockchip_set_drive_perpin(bank, pin, arg); 1925 if (rc < 0) 1926 return rc; 1927 break; 1928 1929 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 1930 if (!ctrl->schmitt_calc_reg) 1931 return -ENOTSUPP; 1932 1933 rc = rockchip_set_schmitt(bank, pin, arg); 1934 if (rc < 0) 1935 return rc; 1936 break; 1937 1938 default: 1939 break; 1940 } 1941 1942 return 0; 1943 } 1944 1945 static const struct pinconf_param rockchip_conf_params[] = { 1946 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, 1947 { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 }, 1948 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, 1949 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, 1950 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 1951 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 1952 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 }, 1953 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 1954 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 1955 }; 1956 1957 static int rockchip_pinconf_prop_name_to_param(const char *property, 1958 u32 *default_value) 1959 { 1960 const struct pinconf_param *p, *end; 1961 1962 p = rockchip_conf_params; 1963 end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param); 1964 1965 /* See if this pctldev supports this parameter */ 1966 for (; p < end; p++) { 1967 if (!strcmp(property, p->property)) { 1968 *default_value = p->default_value; 1969 return p->param; 1970 } 1971 } 1972 1973 *default_value = 0; 1974 return -EPERM; 1975 } 1976 1977 static int rockchip_pinctrl_set_state(struct udevice *dev, 1978 struct udevice *config) 1979 { 1980 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 1981 struct rockchip_pin_ctrl *ctrl = priv->ctrl; 1982 u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4]; 1983 u32 bank, pin, mux, conf, arg, default_val; 1984 int ret, count, i; 1985 const char *prop_name; 1986 const void *value; 1987 int prop_len, param; 1988 const u32 *data; 1989 ofnode node; 1990 #ifdef CONFIG_OF_LIVE 1991 const struct device_node *np; 1992 struct property *pp; 1993 #else 1994 int property_offset, pcfg_node; 1995 const void *blob = gd->fdt_blob; 1996 #endif 1997 data = dev_read_prop(config, "rockchip,pins", &count); 1998 if (count < 0) { 1999 debug("%s: bad array size %d\n", __func__, count); 2000 return -EINVAL; 2001 } 2002 2003 count /= sizeof(u32); 2004 if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) { 2005 debug("%s: unsupported pins array count %d\n", 2006 __func__, count); 2007 return -EINVAL; 2008 } 2009 2010 for (i = 0; i < count; i++) 2011 cells[i] = fdt32_to_cpu(data[i]); 2012 2013 for (i = 0; i < (count >> 2); i++) { 2014 bank = cells[4 * i + 0]; 2015 pin = cells[4 * i + 1]; 2016 mux = cells[4 * i + 2]; 2017 conf = cells[4 * i + 3]; 2018 2019 ret = rockchip_verify_config(dev, bank, pin); 2020 if (ret) 2021 return ret; 2022 2023 ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux); 2024 if (ret) 2025 return ret; 2026 2027 node = ofnode_get_by_phandle(conf); 2028 if (!ofnode_valid(node)) 2029 return -ENODEV; 2030 #ifdef CONFIG_OF_LIVE 2031 np = ofnode_to_np(node); 2032 for (pp = np->properties; pp; pp = pp->next) { 2033 prop_name = pp->name; 2034 prop_len = pp->length; 2035 value = pp->value; 2036 #else 2037 pcfg_node = ofnode_to_offset(node); 2038 fdt_for_each_property_offset(property_offset, blob, pcfg_node) { 2039 value = fdt_getprop_by_offset(blob, property_offset, 2040 &prop_name, &prop_len); 2041 if (!value) 2042 return -ENOENT; 2043 #endif 2044 param = rockchip_pinconf_prop_name_to_param(prop_name, 2045 &default_val); 2046 if (param < 0) 2047 break; 2048 2049 if (prop_len >= sizeof(fdt32_t)) 2050 arg = fdt32_to_cpu(*(fdt32_t *)value); 2051 else 2052 arg = default_val; 2053 2054 ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin, 2055 param, arg); 2056 if (ret) { 2057 debug("%s: rockchip_pinconf_set fail: %d\n", 2058 __func__, ret); 2059 return ret; 2060 } 2061 } 2062 } 2063 2064 return 0; 2065 } 2066 2067 static struct pinctrl_ops rockchip_pinctrl_ops = { 2068 .set_state = rockchip_pinctrl_set_state, 2069 .get_gpio_mux = rockchip_pinctrl_get_gpio_mux, 2070 }; 2071 2072 /* retrieve the soc specific data */ 2073 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev) 2074 { 2075 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2076 struct rockchip_pin_ctrl *ctrl = 2077 (struct rockchip_pin_ctrl *)dev_get_driver_data(dev); 2078 struct rockchip_pin_bank *bank; 2079 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; 2080 2081 grf_offs = ctrl->grf_mux_offset; 2082 pmu_offs = ctrl->pmu_mux_offset; 2083 drv_pmu_offs = ctrl->pmu_drv_offset; 2084 drv_grf_offs = ctrl->grf_drv_offset; 2085 bank = ctrl->pin_banks; 2086 2087 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { 2088 int bank_pins = 0; 2089 2090 bank->priv = priv; 2091 bank->pin_base = ctrl->nr_pins; 2092 ctrl->nr_pins += bank->nr_pins; 2093 2094 /* calculate iomux and drv offsets */ 2095 for (j = 0; j < 4; j++) { 2096 struct rockchip_iomux *iom = &bank->iomux[j]; 2097 struct rockchip_drv *drv = &bank->drv[j]; 2098 int inc; 2099 2100 if (bank_pins >= bank->nr_pins) 2101 break; 2102 2103 /* preset iomux offset value, set new start value */ 2104 if (iom->offset >= 0) { 2105 if (iom->type & IOMUX_SOURCE_PMU) 2106 pmu_offs = iom->offset; 2107 else 2108 grf_offs = iom->offset; 2109 } else { /* set current iomux offset */ 2110 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2111 pmu_offs : grf_offs; 2112 } 2113 2114 /* preset drv offset value, set new start value */ 2115 if (drv->offset >= 0) { 2116 if (iom->type & IOMUX_SOURCE_PMU) 2117 drv_pmu_offs = drv->offset; 2118 else 2119 drv_grf_offs = drv->offset; 2120 } else { /* set current drv offset */ 2121 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? 2122 drv_pmu_offs : drv_grf_offs; 2123 } 2124 2125 debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", 2126 i, j, iom->offset, drv->offset); 2127 2128 /* 2129 * Increase offset according to iomux width. 2130 * 4bit iomux'es are spread over two registers. 2131 */ 2132 inc = (iom->type & (IOMUX_WIDTH_4BIT | 2133 IOMUX_WIDTH_3BIT | 2134 IOMUX_8WIDTH_2BIT)) ? 8 : 4; 2135 if (iom->type & IOMUX_SOURCE_PMU) 2136 pmu_offs += inc; 2137 else 2138 grf_offs += inc; 2139 2140 /* 2141 * Increase offset according to drv width. 2142 * 3bit drive-strenth'es are spread over two registers. 2143 */ 2144 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || 2145 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) 2146 inc = 8; 2147 else 2148 inc = 4; 2149 2150 if (iom->type & IOMUX_SOURCE_PMU) 2151 drv_pmu_offs += inc; 2152 else 2153 drv_grf_offs += inc; 2154 2155 bank_pins += 8; 2156 } 2157 2158 /* calculate the per-bank recalced_mask */ 2159 for (j = 0; j < ctrl->niomux_recalced; j++) { 2160 int pin = 0; 2161 2162 if (ctrl->iomux_recalced[j].num == bank->bank_num) { 2163 pin = ctrl->iomux_recalced[j].pin; 2164 bank->recalced_mask |= BIT(pin); 2165 } 2166 } 2167 2168 /* calculate the per-bank route_mask */ 2169 for (j = 0; j < ctrl->niomux_routes; j++) { 2170 int pin = 0; 2171 2172 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { 2173 pin = ctrl->iomux_routes[j].pin; 2174 bank->route_mask |= BIT(pin); 2175 } 2176 } 2177 } 2178 2179 return ctrl; 2180 } 2181 2182 static int rockchip_pinctrl_probe(struct udevice *dev) 2183 { 2184 struct rockchip_pinctrl_priv *priv = dev_get_priv(dev); 2185 struct rockchip_pin_ctrl *ctrl; 2186 struct udevice *syscon; 2187 struct regmap *regmap; 2188 int ret = 0; 2189 2190 /* get rockchip grf syscon phandle */ 2191 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf", 2192 &syscon); 2193 if (ret) { 2194 debug("unable to find rockchip,grf syscon device (%d)\n", ret); 2195 return ret; 2196 } 2197 2198 /* get grf-reg base address */ 2199 regmap = syscon_get_regmap(syscon); 2200 if (!regmap) { 2201 debug("unable to find rockchip grf regmap\n"); 2202 return -ENODEV; 2203 } 2204 priv->regmap_base = regmap; 2205 2206 /* option: get pmu-reg base address */ 2207 ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu", 2208 &syscon); 2209 if (!ret) { 2210 /* get pmugrf-reg base address */ 2211 regmap = syscon_get_regmap(syscon); 2212 if (!regmap) { 2213 debug("unable to find rockchip pmu regmap\n"); 2214 return -ENODEV; 2215 } 2216 priv->regmap_pmu = regmap; 2217 } 2218 2219 ctrl = rockchip_pinctrl_get_soc_data(dev); 2220 if (!ctrl) { 2221 debug("driver data not available\n"); 2222 return -EINVAL; 2223 } 2224 2225 priv->ctrl = ctrl; 2226 return 0; 2227 } 2228 2229 static struct rockchip_pin_bank px30_pin_banks[] = { 2230 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2231 IOMUX_SOURCE_PMU, 2232 IOMUX_SOURCE_PMU, 2233 IOMUX_SOURCE_PMU 2234 ), 2235 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, 2236 IOMUX_WIDTH_4BIT, 2237 IOMUX_WIDTH_4BIT, 2238 IOMUX_WIDTH_4BIT 2239 ), 2240 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, 2241 IOMUX_WIDTH_4BIT, 2242 IOMUX_WIDTH_4BIT, 2243 IOMUX_WIDTH_4BIT 2244 ), 2245 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, 2246 IOMUX_WIDTH_4BIT, 2247 IOMUX_WIDTH_4BIT, 2248 IOMUX_WIDTH_4BIT 2249 ), 2250 }; 2251 2252 static struct rockchip_pin_ctrl px30_pin_ctrl = { 2253 .pin_banks = px30_pin_banks, 2254 .nr_banks = ARRAY_SIZE(px30_pin_banks), 2255 .label = "PX30-GPIO", 2256 .type = PX30, 2257 .grf_mux_offset = 0x0, 2258 .pmu_mux_offset = 0x0, 2259 .iomux_routes = px30_mux_route_data, 2260 .niomux_routes = ARRAY_SIZE(px30_mux_route_data), 2261 .pull_calc_reg = px30_calc_pull_reg_and_bit, 2262 .drv_calc_reg = px30_calc_drv_reg_and_bit, 2263 .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, 2264 }; 2265 2266 static struct rockchip_pin_bank rv1108_pin_banks[] = { 2267 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2268 IOMUX_SOURCE_PMU, 2269 IOMUX_SOURCE_PMU, 2270 IOMUX_SOURCE_PMU), 2271 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2272 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), 2273 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), 2274 }; 2275 2276 static struct rockchip_pin_ctrl rv1108_pin_ctrl = { 2277 .pin_banks = rv1108_pin_banks, 2278 .nr_banks = ARRAY_SIZE(rv1108_pin_banks), 2279 .label = "RV1108-GPIO", 2280 .type = RV1108, 2281 .grf_mux_offset = 0x10, 2282 .pmu_mux_offset = 0x0, 2283 .iomux_recalced = rv1108_mux_recalced_data, 2284 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), 2285 .pull_calc_reg = rv1108_calc_pull_reg_and_bit, 2286 .drv_calc_reg = rv1108_calc_drv_reg_and_bit, 2287 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, 2288 }; 2289 2290 static struct rockchip_pin_bank rk2928_pin_banks[] = { 2291 PIN_BANK(0, 32, "gpio0"), 2292 PIN_BANK(1, 32, "gpio1"), 2293 PIN_BANK(2, 32, "gpio2"), 2294 PIN_BANK(3, 32, "gpio3"), 2295 }; 2296 2297 static struct rockchip_pin_ctrl rk2928_pin_ctrl = { 2298 .pin_banks = rk2928_pin_banks, 2299 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 2300 .label = "RK2928-GPIO", 2301 .type = RK2928, 2302 .grf_mux_offset = 0xa8, 2303 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2304 }; 2305 2306 static struct rockchip_pin_bank rk3036_pin_banks[] = { 2307 PIN_BANK(0, 32, "gpio0"), 2308 PIN_BANK(1, 32, "gpio1"), 2309 PIN_BANK(2, 32, "gpio2"), 2310 }; 2311 2312 static struct rockchip_pin_ctrl rk3036_pin_ctrl = { 2313 .pin_banks = rk3036_pin_banks, 2314 .nr_banks = ARRAY_SIZE(rk3036_pin_banks), 2315 .label = "RK3036-GPIO", 2316 .type = RK2928, 2317 .grf_mux_offset = 0xa8, 2318 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2319 }; 2320 2321 static struct rockchip_pin_bank rk3066a_pin_banks[] = { 2322 PIN_BANK(0, 32, "gpio0"), 2323 PIN_BANK(1, 32, "gpio1"), 2324 PIN_BANK(2, 32, "gpio2"), 2325 PIN_BANK(3, 32, "gpio3"), 2326 PIN_BANK(4, 32, "gpio4"), 2327 PIN_BANK(6, 16, "gpio6"), 2328 }; 2329 2330 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { 2331 .pin_banks = rk3066a_pin_banks, 2332 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 2333 .label = "RK3066a-GPIO", 2334 .type = RK2928, 2335 .grf_mux_offset = 0xa8, 2336 .pull_calc_reg = rk2928_calc_pull_reg_and_bit, 2337 }; 2338 2339 static struct rockchip_pin_bank rk3066b_pin_banks[] = { 2340 PIN_BANK(0, 32, "gpio0"), 2341 PIN_BANK(1, 32, "gpio1"), 2342 PIN_BANK(2, 32, "gpio2"), 2343 PIN_BANK(3, 32, "gpio3"), 2344 }; 2345 2346 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { 2347 .pin_banks = rk3066b_pin_banks, 2348 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 2349 .label = "RK3066b-GPIO", 2350 .type = RK3066B, 2351 .grf_mux_offset = 0x60, 2352 }; 2353 2354 static struct rockchip_pin_bank rk3128_pin_banks[] = { 2355 PIN_BANK(0, 32, "gpio0"), 2356 PIN_BANK(1, 32, "gpio1"), 2357 PIN_BANK(2, 32, "gpio2"), 2358 PIN_BANK(3, 32, "gpio3"), 2359 }; 2360 2361 static struct rockchip_pin_ctrl rk3128_pin_ctrl = { 2362 .pin_banks = rk3128_pin_banks, 2363 .nr_banks = ARRAY_SIZE(rk3128_pin_banks), 2364 .label = "RK3128-GPIO", 2365 .type = RK3128, 2366 .grf_mux_offset = 0xa8, 2367 .iomux_recalced = rk3128_mux_recalced_data, 2368 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), 2369 .iomux_routes = rk3128_mux_route_data, 2370 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), 2371 .pull_calc_reg = rk3128_calc_pull_reg_and_bit, 2372 }; 2373 2374 static struct rockchip_pin_bank rk3188_pin_banks[] = { 2375 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), 2376 PIN_BANK(1, 32, "gpio1"), 2377 PIN_BANK(2, 32, "gpio2"), 2378 PIN_BANK(3, 32, "gpio3"), 2379 }; 2380 2381 static struct rockchip_pin_ctrl rk3188_pin_ctrl = { 2382 .pin_banks = rk3188_pin_banks, 2383 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 2384 .label = "RK3188-GPIO", 2385 .type = RK3188, 2386 .grf_mux_offset = 0x60, 2387 .pull_calc_reg = rk3188_calc_pull_reg_and_bit, 2388 }; 2389 2390 static struct rockchip_pin_bank rk3228_pin_banks[] = { 2391 PIN_BANK(0, 32, "gpio0"), 2392 PIN_BANK(1, 32, "gpio1"), 2393 PIN_BANK(2, 32, "gpio2"), 2394 PIN_BANK(3, 32, "gpio3"), 2395 }; 2396 2397 static struct rockchip_pin_ctrl rk3228_pin_ctrl = { 2398 .pin_banks = rk3228_pin_banks, 2399 .nr_banks = ARRAY_SIZE(rk3228_pin_banks), 2400 .label = "RK3228-GPIO", 2401 .type = RK3288, 2402 .grf_mux_offset = 0x0, 2403 .iomux_routes = rk3228_mux_route_data, 2404 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), 2405 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2406 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2407 }; 2408 2409 static struct rockchip_pin_bank rk3288_pin_banks[] = { 2410 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 2411 IOMUX_SOURCE_PMU, 2412 IOMUX_SOURCE_PMU, 2413 IOMUX_UNROUTED 2414 ), 2415 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 2416 IOMUX_UNROUTED, 2417 IOMUX_UNROUTED, 2418 0 2419 ), 2420 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 2421 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 2422 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 2423 IOMUX_WIDTH_4BIT, 2424 0, 2425 0 2426 ), 2427 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 2428 0, 2429 0, 2430 IOMUX_UNROUTED 2431 ), 2432 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 2433 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 2434 0, 2435 IOMUX_WIDTH_4BIT, 2436 IOMUX_UNROUTED 2437 ), 2438 PIN_BANK(8, 16, "gpio8"), 2439 }; 2440 2441 static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 2442 .pin_banks = rk3288_pin_banks, 2443 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 2444 .label = "RK3288-GPIO", 2445 .type = RK3288, 2446 .grf_mux_offset = 0x0, 2447 .pmu_mux_offset = 0x84, 2448 .iomux_routes = rk3288_mux_route_data, 2449 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 2450 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 2451 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 2452 }; 2453 2454 static struct rockchip_pin_bank rk3308_pin_banks[] = { 2455 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT, 2456 IOMUX_8WIDTH_2BIT, 2457 IOMUX_8WIDTH_2BIT, 2458 IOMUX_8WIDTH_2BIT), 2459 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT, 2460 IOMUX_8WIDTH_2BIT, 2461 IOMUX_8WIDTH_2BIT, 2462 IOMUX_8WIDTH_2BIT), 2463 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT, 2464 IOMUX_8WIDTH_2BIT, 2465 IOMUX_8WIDTH_2BIT, 2466 IOMUX_8WIDTH_2BIT), 2467 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT, 2468 IOMUX_8WIDTH_2BIT, 2469 IOMUX_8WIDTH_2BIT, 2470 IOMUX_8WIDTH_2BIT), 2471 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT, 2472 IOMUX_8WIDTH_2BIT, 2473 IOMUX_8WIDTH_2BIT, 2474 IOMUX_8WIDTH_2BIT), 2475 }; 2476 2477 static struct rockchip_pin_ctrl rk3308_pin_ctrl = { 2478 .pin_banks = rk3308_pin_banks, 2479 .nr_banks = ARRAY_SIZE(rk3308_pin_banks), 2480 .label = "RK3308-GPIO", 2481 .type = RK3308, 2482 .grf_mux_offset = 0x0, 2483 .iomux_recalced = rk3308_mux_recalced_data, 2484 .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), 2485 .iomux_routes = rk3308_mux_route_data, 2486 .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), 2487 .pull_calc_reg = rk3308_calc_pull_reg_and_bit, 2488 .drv_calc_reg = rk3308_calc_drv_reg_and_bit, 2489 .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, 2490 }; 2491 2492 static struct rockchip_pin_bank rk3328_pin_banks[] = { 2493 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), 2494 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), 2495 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 2496 IOMUX_WIDTH_3BIT, 2497 IOMUX_WIDTH_3BIT, 2498 0), 2499 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 2500 IOMUX_WIDTH_3BIT, 2501 IOMUX_WIDTH_3BIT, 2502 0, 2503 0), 2504 }; 2505 2506 static struct rockchip_pin_ctrl rk3328_pin_ctrl = { 2507 .pin_banks = rk3328_pin_banks, 2508 .nr_banks = ARRAY_SIZE(rk3328_pin_banks), 2509 .label = "RK3328-GPIO", 2510 .type = RK3288, 2511 .grf_mux_offset = 0x0, 2512 .iomux_recalced = rk3328_mux_recalced_data, 2513 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), 2514 .iomux_routes = rk3328_mux_route_data, 2515 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), 2516 .pull_calc_reg = rk3228_calc_pull_reg_and_bit, 2517 .drv_calc_reg = rk3228_calc_drv_reg_and_bit, 2518 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, 2519 }; 2520 2521 static struct rockchip_pin_bank rk3368_pin_banks[] = { 2522 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, 2523 IOMUX_SOURCE_PMU, 2524 IOMUX_SOURCE_PMU, 2525 IOMUX_SOURCE_PMU 2526 ), 2527 PIN_BANK(1, 32, "gpio1"), 2528 PIN_BANK(2, 32, "gpio2"), 2529 PIN_BANK(3, 32, "gpio3"), 2530 }; 2531 2532 static struct rockchip_pin_ctrl rk3368_pin_ctrl = { 2533 .pin_banks = rk3368_pin_banks, 2534 .nr_banks = ARRAY_SIZE(rk3368_pin_banks), 2535 .label = "RK3368-GPIO", 2536 .type = RK3368, 2537 .grf_mux_offset = 0x0, 2538 .pmu_mux_offset = 0x0, 2539 .pull_calc_reg = rk3368_calc_pull_reg_and_bit, 2540 .drv_calc_reg = rk3368_calc_drv_reg_and_bit, 2541 }; 2542 2543 static struct rockchip_pin_bank rk3399_pin_banks[] = { 2544 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", 2545 IOMUX_SOURCE_PMU, 2546 IOMUX_SOURCE_PMU, 2547 IOMUX_SOURCE_PMU, 2548 IOMUX_SOURCE_PMU, 2549 DRV_TYPE_IO_1V8_ONLY, 2550 DRV_TYPE_IO_1V8_ONLY, 2551 DRV_TYPE_IO_DEFAULT, 2552 DRV_TYPE_IO_DEFAULT, 2553 0x80, 2554 0x88, 2555 -1, 2556 -1, 2557 PULL_TYPE_IO_1V8_ONLY, 2558 PULL_TYPE_IO_1V8_ONLY, 2559 PULL_TYPE_IO_DEFAULT, 2560 PULL_TYPE_IO_DEFAULT 2561 ), 2562 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, 2563 IOMUX_SOURCE_PMU, 2564 IOMUX_SOURCE_PMU, 2565 IOMUX_SOURCE_PMU, 2566 DRV_TYPE_IO_1V8_OR_3V0, 2567 DRV_TYPE_IO_1V8_OR_3V0, 2568 DRV_TYPE_IO_1V8_OR_3V0, 2569 DRV_TYPE_IO_1V8_OR_3V0, 2570 0xa0, 2571 0xa8, 2572 0xb0, 2573 0xb8 2574 ), 2575 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 2576 DRV_TYPE_IO_1V8_OR_3V0, 2577 DRV_TYPE_IO_1V8_ONLY, 2578 DRV_TYPE_IO_1V8_ONLY, 2579 PULL_TYPE_IO_DEFAULT, 2580 PULL_TYPE_IO_DEFAULT, 2581 PULL_TYPE_IO_1V8_ONLY, 2582 PULL_TYPE_IO_1V8_ONLY 2583 ), 2584 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, 2585 DRV_TYPE_IO_3V3_ONLY, 2586 DRV_TYPE_IO_3V3_ONLY, 2587 DRV_TYPE_IO_1V8_OR_3V0 2588 ), 2589 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, 2590 DRV_TYPE_IO_1V8_3V0_AUTO, 2591 DRV_TYPE_IO_1V8_OR_3V0, 2592 DRV_TYPE_IO_1V8_OR_3V0 2593 ), 2594 }; 2595 2596 static struct rockchip_pin_ctrl rk3399_pin_ctrl = { 2597 .pin_banks = rk3399_pin_banks, 2598 .nr_banks = ARRAY_SIZE(rk3399_pin_banks), 2599 .label = "RK3399-GPIO", 2600 .type = RK3399, 2601 .grf_mux_offset = 0xe000, 2602 .pmu_mux_offset = 0x0, 2603 .grf_drv_offset = 0xe100, 2604 .pmu_drv_offset = 0x80, 2605 .iomux_routes = rk3399_mux_route_data, 2606 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), 2607 .pull_calc_reg = rk3399_calc_pull_reg_and_bit, 2608 .drv_calc_reg = rk3399_calc_drv_reg_and_bit, 2609 }; 2610 2611 static const struct udevice_id rockchip_pinctrl_dt_match[] = { 2612 { .compatible = "rockchip,px30-pinctrl", 2613 .data = (ulong)&px30_pin_ctrl }, 2614 { .compatible = "rockchip,rv1108-pinctrl", 2615 .data = (ulong)&rv1108_pin_ctrl }, 2616 { .compatible = "rockchip,rk2928-pinctrl", 2617 .data = (ulong)&rk2928_pin_ctrl }, 2618 { .compatible = "rockchip,rk3036-pinctrl", 2619 .data = (ulong)&rk3036_pin_ctrl }, 2620 { .compatible = "rockchip,rk3066a-pinctrl", 2621 .data = (ulong)&rk3066a_pin_ctrl }, 2622 { .compatible = "rockchip,rk3066b-pinctrl", 2623 .data = (ulong)&rk3066b_pin_ctrl }, 2624 { .compatible = "rockchip,rk3128-pinctrl", 2625 .data = (ulong)&rk3128_pin_ctrl }, 2626 { .compatible = "rockchip,rk3188-pinctrl", 2627 .data = (ulong)&rk3188_pin_ctrl }, 2628 { .compatible = "rockchip,rk3228-pinctrl", 2629 .data = (ulong)&rk3228_pin_ctrl }, 2630 { .compatible = "rockchip,rk3288-pinctrl", 2631 .data = (ulong)&rk3288_pin_ctrl }, 2632 { .compatible = "rockchip,rk3308-pinctrl", 2633 .data = (ulong)&rk3308_pin_ctrl }, 2634 { .compatible = "rockchip,rk3328-pinctrl", 2635 .data = (ulong)&rk3328_pin_ctrl }, 2636 { .compatible = "rockchip,rk3368-pinctrl", 2637 .data = (ulong)&rk3368_pin_ctrl }, 2638 { .compatible = "rockchip,rk3399-pinctrl", 2639 .data = (ulong)&rk3399_pin_ctrl }, 2640 {}, 2641 }; 2642 2643 U_BOOT_DRIVER(pinctrl_rockchip) = { 2644 .name = "rockchip_pinctrl", 2645 .id = UCLASS_PINCTRL, 2646 .of_match = rockchip_pinctrl_dt_match, 2647 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv), 2648 .ops = &rockchip_pinctrl_ops, 2649 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 2650 .bind = dm_scan_fdt_dev, 2651 #endif 2652 .probe = rockchip_pinctrl_probe, 2653 }; 2654