i.MX6: add enable_sata_clock()

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>

i.MX6: Add ANATOP regulator init

Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix s

i.MX6: Add ANATOP regulator init

Init the core regulator voltage to 1.2V. This is required for the correct
functioning of the GPU and when the ARM LDO is set to 1.225V. This is a
workaround to fix some memory clock jitter.

Note: This should be but can't be done in the DCD. The bootloader
prevents access to the ANATOP registers.

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>

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imx-common: Factor out get_ahb_clk()

get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Est

imx-common: Factor out get_ahb_clk()

get_ahb_clk() is a common function between mx5 and mx6.

Place it into imx-common directory.

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

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imx: Remove unneeded/repititive definitions from imx headers

Remove gpio related unused/repititive definitions from imx headers.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Stef

imx: Remove unneeded/repititive definitions from imx headers

Remove gpio related unused/repititive definitions from imx headers.

Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>

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i.MX6: define CACHELINE_SIZE

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>

mx6: Read silicon revision from register

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-li

mx6: Read silicon revision from register

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>

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mx6: Remove duplicate definition of ANATOP_BASE_ADDR

Remove duplicate definition of ANATOP_BASE_ADDR.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

usb/ehci: Add USB support for the MX6Q

Currently, only USB Host 1 is supported.

Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>

net: fec_mxc: add 1000 Mbps selection

Define FEC_QUIRK_ENET_MAC and add to
arch-mx6/imx-regs.h

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.c

net: fec_mxc: add 1000 Mbps selection

Define FEC_QUIRK_ENET_MAC and add to
arch-mx6/imx-regs.h

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>

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mx6q: Add support for ECSPI through mxc_spi driver

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de

mx6q: Add support for ECSPI through mxc_spi driver

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>

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mx6q: define GPIO macros for translating between ordinals and port:index

The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The register

mx6q: define GPIO macros for translating between ordinals and port:index

The interface to the mxc_gpio driver uses integer (ordinal) values to
refer to all GPIOs on the i.MX processors. The registers themselves
and much of the i.MX documentation are banked in groups of 32, and these
macros allow the use of the port:index numbering for clarity.

GPIO_NUMBER() converts to ordinal value from port:index
GPIO_PORT() returns the port of an ordinal value
GPIO_INDEX() returns the index or offset of the ordinal.

Discussion on the mailing list at
http://lists.denx.de/pipermail/u-boot/2012-January/116927.html

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

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i.mx6: mx6x_pins: Fix uart txd definitions

The uart txd pad can also provide the rxd function. But it does not stop its
tx role. This could be used for a half duplex serial port.

Change names to re

i.mx6: mx6x_pins: Fix uart txd definitions

The uart txd pad can also provide the rxd function. But it does not stop its
tx role. This could be used for a half duplex serial port.

Change names to reduce confusion.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>

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imx: mx6q: add aipstz init for off platform periph

Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW): 0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require su

imx: mx6q: add aipstz init for off platform periph

Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW): 0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP): 0 -> allows write accesses.
Trusted Protect(TP): 0 -> allows unstrusted master

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>

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i.mx6:imx6q: allign MAC address with burned-in ordering

For the i.mx6q, the burned-in MAC address will be the following odering,

fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5]
fuse: 0x620[15:8]

i.mx6:imx6q: allign MAC address with burned-in ordering

For the i.mx6q, the burned-in MAC address will be the following odering,

fuse: 0x620[7:0] MAC_ADDR[7:0] ---> mac[5]
fuse: 0x620[15:8] MAC_ADDR[15:8] ---> mac[4]
fuse: 0x620[23:16] MAC_ADDR[23:16] ---> mac[3]
fuse: 0x620[31:24] MAC_ADDR[31:24] ---> mac[2]
fuse: 0x630[7:0] MAC_ADDR[39:32] ---> mac[1]
fuse: 0x630[15:8] MAC_ADDR[47:40] ---> mac[0]

This patch also fix the error caculation for the fuse bank[0] address

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>

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net: imx: Add multi-FEC support for imx_get_mac_from_fuse

Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.

This feature is important on mx28 SoC for example that ha

net: imx: Add multi-FEC support for imx_get_mac_from_fuse

Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter.

This feature is important on mx28 SoC for example that has two FEC ports.

Cc: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

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i.mx: add the initial support for freescale i.MX6Q processor

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.

Signed

i.mx: add the initial support for freescale i.MX6Q processor

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex.
This patch is to add the initial support for this processor.

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>

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