1 /* 2 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> 3 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> 4 * (C) Copyright 2008 Armadeus Systems nc 5 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 6 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <malloc.h> 26 #include <net.h> 27 #include <miiphy.h> 28 #include "fec_mxc.h" 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 #include <asm/io.h> 33 #include <asm/errno.h> 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 #ifndef CONFIG_MII 38 #error "CONFIG_MII has to be defined!" 39 #endif 40 41 #ifndef CONFIG_FEC_XCV_TYPE 42 #define CONFIG_FEC_XCV_TYPE MII100 43 #endif 44 45 /* 46 * The i.MX28 operates with packets in big endian. We need to swap them before 47 * sending and after receiving. 48 */ 49 #ifdef CONFIG_MX28 50 #define CONFIG_FEC_MXC_SWAP_PACKET 51 #endif 52 53 #undef DEBUG 54 55 struct nbuf { 56 uint8_t data[1500]; /**< actual data */ 57 int length; /**< actual length */ 58 int used; /**< buffer in use or not */ 59 uint8_t head[16]; /**< MAC header(6 + 6 + 2) + 2(aligned) */ 60 }; 61 62 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 63 static void swap_packet(uint32_t *packet, int length) 64 { 65 int i; 66 67 for (i = 0; i < DIV_ROUND_UP(length, 4); i++) 68 packet[i] = __swab32(packet[i]); 69 } 70 #endif 71 72 /* 73 * The i.MX28 has two ethernet interfaces, but they are not equal. 74 * Only the first one can access the MDIO bus. 75 */ 76 #ifdef CONFIG_MX28 77 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) 78 { 79 return (struct ethernet_regs *)MXS_ENET0_BASE; 80 } 81 #else 82 static inline struct ethernet_regs *fec_miiphy_fec_to_eth(struct fec_priv *fec) 83 { 84 return fec->eth; 85 } 86 #endif 87 88 /* 89 * MII-interface related functions 90 */ 91 static int fec_miiphy_read(const char *dev, uint8_t phyAddr, uint8_t regAddr, 92 uint16_t *retVal) 93 { 94 struct eth_device *edev = eth_get_dev_by_name(dev); 95 struct fec_priv *fec = (struct fec_priv *)edev->priv; 96 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); 97 98 uint32_t reg; /* convenient holder for the PHY register */ 99 uint32_t phy; /* convenient holder for the PHY */ 100 uint32_t start; 101 102 /* 103 * reading from any PHY's register is done by properly 104 * programming the FEC's MII data register. 105 */ 106 writel(FEC_IEVENT_MII, ð->ievent); 107 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 108 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 109 110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | 111 phy | reg, ð->mii_data); 112 113 /* 114 * wait for the related interrupt 115 */ 116 start = get_timer(0); 117 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 118 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 119 printf("Read MDIO failed...\n"); 120 return -1; 121 } 122 } 123 124 /* 125 * clear mii interrupt bit 126 */ 127 writel(FEC_IEVENT_MII, ð->ievent); 128 129 /* 130 * it's now safe to read the PHY's register 131 */ 132 *retVal = readl(ð->mii_data); 133 debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr, 134 regAddr, *retVal); 135 return 0; 136 } 137 138 static void fec_mii_setspeed(struct fec_priv *fec) 139 { 140 /* 141 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock 142 * and do not drop the Preamble. 143 */ 144 writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1, 145 &fec->eth->mii_speed); 146 debug("fec_init: mii_speed %08x\n", 147 readl(&fec->eth->mii_speed)); 148 } 149 static int fec_miiphy_write(const char *dev, uint8_t phyAddr, uint8_t regAddr, 150 uint16_t data) 151 { 152 struct eth_device *edev = eth_get_dev_by_name(dev); 153 struct fec_priv *fec = (struct fec_priv *)edev->priv; 154 struct ethernet_regs *eth = fec_miiphy_fec_to_eth(fec); 155 156 uint32_t reg; /* convenient holder for the PHY register */ 157 uint32_t phy; /* convenient holder for the PHY */ 158 uint32_t start; 159 160 reg = regAddr << FEC_MII_DATA_RA_SHIFT; 161 phy = phyAddr << FEC_MII_DATA_PA_SHIFT; 162 163 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | 164 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); 165 166 /* 167 * wait for the MII interrupt 168 */ 169 start = get_timer(0); 170 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { 171 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { 172 printf("Write MDIO failed...\n"); 173 return -1; 174 } 175 } 176 177 /* 178 * clear MII interrupt bit 179 */ 180 writel(FEC_IEVENT_MII, ð->ievent); 181 debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr, 182 regAddr, data); 183 184 return 0; 185 } 186 187 static int miiphy_restart_aneg(struct eth_device *dev) 188 { 189 struct fec_priv *fec = (struct fec_priv *)dev->priv; 190 int ret = 0; 191 192 /* 193 * Wake up from sleep if necessary 194 * Reset PHY, then delay 300ns 195 */ 196 #ifdef CONFIG_MX27 197 miiphy_write(dev->name, fec->phy_id, MII_DCOUNTER, 0x00FF); 198 #endif 199 miiphy_write(dev->name, fec->phy_id, MII_BMCR, 200 BMCR_RESET); 201 udelay(1000); 202 203 /* 204 * Set the auto-negotiation advertisement register bits 205 */ 206 miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE, 207 LPA_100FULL | LPA_100HALF | LPA_10FULL | 208 LPA_10HALF | PHY_ANLPAR_PSB_802_3); 209 miiphy_write(dev->name, fec->phy_id, MII_BMCR, 210 BMCR_ANENABLE | BMCR_ANRESTART); 211 212 if (fec->mii_postcall) 213 ret = fec->mii_postcall(fec->phy_id); 214 215 return ret; 216 } 217 218 static int miiphy_wait_aneg(struct eth_device *dev) 219 { 220 uint32_t start; 221 uint16_t status; 222 struct fec_priv *fec = (struct fec_priv *)dev->priv; 223 224 /* 225 * Wait for AN completion 226 */ 227 start = get_timer(0); 228 do { 229 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 230 printf("%s: Autonegotiation timeout\n", dev->name); 231 return -1; 232 } 233 234 if (miiphy_read(dev->name, fec->phy_id, 235 MII_BMSR, &status)) { 236 printf("%s: Autonegotiation failed. status: 0x%04x\n", 237 dev->name, status); 238 return -1; 239 } 240 } while (!(status & BMSR_LSTATUS)); 241 242 return 0; 243 } 244 static int fec_rx_task_enable(struct fec_priv *fec) 245 { 246 writel(1 << 24, &fec->eth->r_des_active); 247 return 0; 248 } 249 250 static int fec_rx_task_disable(struct fec_priv *fec) 251 { 252 return 0; 253 } 254 255 static int fec_tx_task_enable(struct fec_priv *fec) 256 { 257 writel(1 << 24, &fec->eth->x_des_active); 258 return 0; 259 } 260 261 static int fec_tx_task_disable(struct fec_priv *fec) 262 { 263 return 0; 264 } 265 266 /** 267 * Initialize receive task's buffer descriptors 268 * @param[in] fec all we know about the device yet 269 * @param[in] count receive buffer count to be allocated 270 * @param[in] size size of each receive buffer 271 * @return 0 on success 272 * 273 * For this task we need additional memory for the data buffers. And each 274 * data buffer requires some alignment. Thy must be aligned to a specific 275 * boundary each (DB_DATA_ALIGNMENT). 276 */ 277 static int fec_rbd_init(struct fec_priv *fec, int count, int size) 278 { 279 int ix; 280 uint32_t p = 0; 281 282 /* reserve data memory and consider alignment */ 283 if (fec->rdb_ptr == NULL) 284 fec->rdb_ptr = malloc(size * count + DB_DATA_ALIGNMENT); 285 p = (uint32_t)fec->rdb_ptr; 286 if (!p) { 287 puts("fec_mxc: not enough malloc memory\n"); 288 return -ENOMEM; 289 } 290 memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT); 291 p += DB_DATA_ALIGNMENT-1; 292 p &= ~(DB_DATA_ALIGNMENT-1); 293 294 for (ix = 0; ix < count; ix++) { 295 writel(p, &fec->rbd_base[ix].data_pointer); 296 p += size; 297 writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status); 298 writew(0, &fec->rbd_base[ix].data_length); 299 } 300 /* 301 * mark the last RBD to close the ring 302 */ 303 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status); 304 fec->rbd_index = 0; 305 306 return 0; 307 } 308 309 /** 310 * Initialize transmit task's buffer descriptors 311 * @param[in] fec all we know about the device yet 312 * 313 * Transmit buffers are created externally. We only have to init the BDs here.\n 314 * Note: There is a race condition in the hardware. When only one BD is in 315 * use it must be marked with the WRAP bit to use it for every transmitt. 316 * This bit in combination with the READY bit results into double transmit 317 * of each data buffer. It seems the state machine checks READY earlier then 318 * resetting it after the first transfer. 319 * Using two BDs solves this issue. 320 */ 321 static void fec_tbd_init(struct fec_priv *fec) 322 { 323 writew(0x0000, &fec->tbd_base[0].status); 324 writew(FEC_TBD_WRAP, &fec->tbd_base[1].status); 325 fec->tbd_index = 0; 326 } 327 328 /** 329 * Mark the given read buffer descriptor as free 330 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 331 * @param[in] pRbd buffer descriptor to mark free again 332 */ 333 static void fec_rbd_clean(int last, struct fec_bd *pRbd) 334 { 335 /* 336 * Reset buffer descriptor as empty 337 */ 338 if (last) 339 writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status); 340 else 341 writew(FEC_RBD_EMPTY, &pRbd->status); 342 /* 343 * no data in it 344 */ 345 writew(0, &pRbd->data_length); 346 } 347 348 static int fec_get_hwaddr(struct eth_device *dev, int dev_id, 349 unsigned char *mac) 350 { 351 imx_get_mac_from_fuse(dev_id, mac); 352 return !is_valid_ether_addr(mac); 353 } 354 355 static int fec_set_hwaddr(struct eth_device *dev) 356 { 357 uchar *mac = dev->enetaddr; 358 struct fec_priv *fec = (struct fec_priv *)dev->priv; 359 360 writel(0, &fec->eth->iaddr1); 361 writel(0, &fec->eth->iaddr2); 362 writel(0, &fec->eth->gaddr1); 363 writel(0, &fec->eth->gaddr2); 364 365 /* 366 * Set physical address 367 */ 368 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], 369 &fec->eth->paddr1); 370 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); 371 372 return 0; 373 } 374 375 /** 376 * Start the FEC engine 377 * @param[in] dev Our device to handle 378 */ 379 static int fec_open(struct eth_device *edev) 380 { 381 struct fec_priv *fec = (struct fec_priv *)edev->priv; 382 int speed; 383 384 debug("fec_open: fec_open(dev)\n"); 385 /* full-duplex, heartbeat disabled */ 386 writel(1 << 2, &fec->eth->x_cntrl); 387 fec->rbd_index = 0; 388 389 #ifdef FEC_QUIRK_ENET_MAC 390 /* Enable ENET HW endian SWAP */ 391 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, 392 &fec->eth->ecntrl); 393 /* Enable ENET store and forward mode */ 394 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, 395 &fec->eth->x_wmrk); 396 #endif 397 /* 398 * Enable FEC-Lite controller 399 */ 400 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, 401 &fec->eth->ecntrl); 402 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) 403 udelay(100); 404 /* 405 * setup the MII gasket for RMII mode 406 */ 407 408 /* disable the gasket */ 409 writew(0, &fec->eth->miigsk_enr); 410 411 /* wait for the gasket to be disabled */ 412 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) 413 udelay(2); 414 415 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ 416 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); 417 418 /* re-enable the gasket */ 419 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); 420 421 /* wait until MII gasket is ready */ 422 int max_loops = 10; 423 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { 424 if (--max_loops <= 0) { 425 printf("WAIT for MII Gasket ready timed out\n"); 426 break; 427 } 428 } 429 #endif 430 431 miiphy_wait_aneg(edev); 432 speed = miiphy_speed(edev->name, fec->phy_id); 433 miiphy_duplex(edev->name, fec->phy_id); 434 435 #ifdef FEC_QUIRK_ENET_MAC 436 { 437 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; 438 u32 rcr = (readl(&fec->eth->r_cntrl) & 439 ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | 440 FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; 441 if (speed == _1000BASET) 442 ecr |= FEC_ECNTRL_SPEED; 443 else if (speed != _100BASET) 444 rcr |= FEC_RCNTRL_RMII_10T; 445 writel(ecr, &fec->eth->ecntrl); 446 writel(rcr, &fec->eth->r_cntrl); 447 } 448 #endif 449 debug("%s:Speed=%i\n", __func__, speed); 450 451 /* 452 * Enable SmartDMA receive task 453 */ 454 fec_rx_task_enable(fec); 455 456 udelay(100000); 457 return 0; 458 } 459 460 static int fec_init(struct eth_device *dev, bd_t* bd) 461 { 462 uint32_t base; 463 struct fec_priv *fec = (struct fec_priv *)dev->priv; 464 uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; 465 uint32_t rcntrl; 466 int i; 467 468 /* Initialize MAC address */ 469 fec_set_hwaddr(dev); 470 471 /* 472 * reserve memory for both buffer descriptor chains at once 473 * Datasheet forces the startaddress of each chain is 16 byte 474 * aligned 475 */ 476 if (fec->base_ptr == NULL) 477 fec->base_ptr = malloc((2 + FEC_RBD_NUM) * 478 sizeof(struct fec_bd) + DB_ALIGNMENT); 479 base = (uint32_t)fec->base_ptr; 480 if (!base) { 481 puts("fec_mxc: not enough malloc memory\n"); 482 return -ENOMEM; 483 } 484 memset((void *)base, 0, (2 + FEC_RBD_NUM) * 485 sizeof(struct fec_bd) + DB_ALIGNMENT); 486 base += (DB_ALIGNMENT-1); 487 base &= ~(DB_ALIGNMENT-1); 488 489 fec->rbd_base = (struct fec_bd *)base; 490 491 base += FEC_RBD_NUM * sizeof(struct fec_bd); 492 493 fec->tbd_base = (struct fec_bd *)base; 494 495 /* 496 * Set interrupt mask register 497 */ 498 writel(0x00000000, &fec->eth->imask); 499 500 /* 501 * Clear FEC-Lite interrupt event register(IEVENT) 502 */ 503 writel(0xffffffff, &fec->eth->ievent); 504 505 506 /* 507 * Set FEC-Lite receive control register(R_CNTRL): 508 */ 509 510 /* Start with frame length = 1518, common for all modes. */ 511 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; 512 if (fec->xcv_type == SEVENWIRE) 513 rcntrl |= FEC_RCNTRL_FCE; 514 else if (fec->xcv_type == RGMII) 515 rcntrl |= FEC_RCNTRL_RGMII; 516 else if (fec->xcv_type == RMII) 517 rcntrl |= FEC_RCNTRL_RMII; 518 else /* MII mode */ 519 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; 520 521 writel(rcntrl, &fec->eth->r_cntrl); 522 523 if (fec->xcv_type == MII10 || fec->xcv_type == MII100) 524 fec_mii_setspeed(fec); 525 526 /* 527 * Set Opcode/Pause Duration Register 528 */ 529 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ 530 writel(0x2, &fec->eth->x_wmrk); 531 /* 532 * Set multicast address filter 533 */ 534 writel(0x00000000, &fec->eth->gaddr1); 535 writel(0x00000000, &fec->eth->gaddr2); 536 537 538 /* clear MIB RAM */ 539 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) 540 writel(0, i); 541 542 /* FIFO receive start register */ 543 writel(0x520, &fec->eth->r_fstart); 544 545 /* size and address of each buffer */ 546 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); 547 writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); 548 writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); 549 550 /* 551 * Initialize RxBD/TxBD rings 552 */ 553 if (fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE) < 0) { 554 free(fec->base_ptr); 555 fec->base_ptr = NULL; 556 return -ENOMEM; 557 } 558 fec_tbd_init(fec); 559 560 561 if (fec->xcv_type != SEVENWIRE) 562 miiphy_restart_aneg(dev); 563 564 fec_open(dev); 565 return 0; 566 } 567 568 /** 569 * Halt the FEC engine 570 * @param[in] dev Our device to handle 571 */ 572 static void fec_halt(struct eth_device *dev) 573 { 574 struct fec_priv *fec = (struct fec_priv *)dev->priv; 575 int counter = 0xffff; 576 577 /* 578 * issue graceful stop command to the FEC transmitter if necessary 579 */ 580 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), 581 &fec->eth->x_cntrl); 582 583 debug("eth_halt: wait for stop regs\n"); 584 /* 585 * wait for graceful stop to register 586 */ 587 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) 588 udelay(1); 589 590 /* 591 * Disable SmartDMA tasks 592 */ 593 fec_tx_task_disable(fec); 594 fec_rx_task_disable(fec); 595 596 /* 597 * Disable the Ethernet Controller 598 * Note: this will also reset the BD index counter! 599 */ 600 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, 601 &fec->eth->ecntrl); 602 fec->rbd_index = 0; 603 fec->tbd_index = 0; 604 debug("eth_halt: done\n"); 605 } 606 607 /** 608 * Transmit one frame 609 * @param[in] dev Our ethernet device to handle 610 * @param[in] packet Pointer to the data to be transmitted 611 * @param[in] length Data count in bytes 612 * @return 0 on success 613 */ 614 static int fec_send(struct eth_device *dev, volatile void* packet, int length) 615 { 616 unsigned int status; 617 618 /* 619 * This routine transmits one frame. This routine only accepts 620 * 6-byte Ethernet addresses. 621 */ 622 struct fec_priv *fec = (struct fec_priv *)dev->priv; 623 624 /* 625 * Check for valid length of data. 626 */ 627 if ((length > 1500) || (length <= 0)) { 628 printf("Payload (%d) too large\n", length); 629 return -1; 630 } 631 632 /* 633 * Setup the transmit buffer 634 * Note: We are always using the first buffer for transmission, 635 * the second will be empty and only used to stop the DMA engine 636 */ 637 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 638 swap_packet((uint32_t *)packet, length); 639 #endif 640 writew(length, &fec->tbd_base[fec->tbd_index].data_length); 641 writel((uint32_t)packet, &fec->tbd_base[fec->tbd_index].data_pointer); 642 /* 643 * update BD's status now 644 * This block: 645 * - is always the last in a chain (means no chain) 646 * - should transmitt the CRC 647 * - might be the last BD in the list, so the address counter should 648 * wrap (-> keep the WRAP flag) 649 */ 650 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; 651 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; 652 writew(status, &fec->tbd_base[fec->tbd_index].status); 653 654 /* 655 * Enable SmartDMA transmit task 656 */ 657 fec_tx_task_enable(fec); 658 659 /* 660 * wait until frame is sent . 661 */ 662 while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) { 663 udelay(1); 664 } 665 debug("fec_send: status 0x%x index %d\n", 666 readw(&fec->tbd_base[fec->tbd_index].status), 667 fec->tbd_index); 668 /* for next transmission use the other buffer */ 669 if (fec->tbd_index) 670 fec->tbd_index = 0; 671 else 672 fec->tbd_index = 1; 673 674 return 0; 675 } 676 677 /** 678 * Pull one frame from the card 679 * @param[in] dev Our ethernet device to handle 680 * @return Length of packet read 681 */ 682 static int fec_recv(struct eth_device *dev) 683 { 684 struct fec_priv *fec = (struct fec_priv *)dev->priv; 685 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; 686 unsigned long ievent; 687 int frame_length, len = 0; 688 struct nbuf *frame; 689 uint16_t bd_status; 690 uchar buff[FEC_MAX_PKT_SIZE]; 691 692 /* 693 * Check if any critical events have happened 694 */ 695 ievent = readl(&fec->eth->ievent); 696 writel(ievent, &fec->eth->ievent); 697 debug("fec_recv: ievent 0x%lx\n", ievent); 698 if (ievent & FEC_IEVENT_BABR) { 699 fec_halt(dev); 700 fec_init(dev, fec->bd); 701 printf("some error: 0x%08lx\n", ievent); 702 return 0; 703 } 704 if (ievent & FEC_IEVENT_HBERR) { 705 /* Heartbeat error */ 706 writel(0x00000001 | readl(&fec->eth->x_cntrl), 707 &fec->eth->x_cntrl); 708 } 709 if (ievent & FEC_IEVENT_GRA) { 710 /* Graceful stop complete */ 711 if (readl(&fec->eth->x_cntrl) & 0x00000001) { 712 fec_halt(dev); 713 writel(~0x00000001 & readl(&fec->eth->x_cntrl), 714 &fec->eth->x_cntrl); 715 fec_init(dev, fec->bd); 716 } 717 } 718 719 /* 720 * ensure reading the right buffer status 721 */ 722 bd_status = readw(&rbd->status); 723 debug("fec_recv: status 0x%x\n", bd_status); 724 725 if (!(bd_status & FEC_RBD_EMPTY)) { 726 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && 727 ((readw(&rbd->data_length) - 4) > 14)) { 728 /* 729 * Get buffer address and size 730 */ 731 frame = (struct nbuf *)readl(&rbd->data_pointer); 732 frame_length = readw(&rbd->data_length) - 4; 733 /* 734 * Fill the buffer and pass it to upper layers 735 */ 736 #ifdef CONFIG_FEC_MXC_SWAP_PACKET 737 swap_packet((uint32_t *)frame->data, frame_length); 738 #endif 739 memcpy(buff, frame->data, frame_length); 740 NetReceive(buff, frame_length); 741 len = frame_length; 742 } else { 743 if (bd_status & FEC_RBD_ERR) 744 printf("error frame: 0x%08lx 0x%08x\n", 745 (ulong)rbd->data_pointer, 746 bd_status); 747 } 748 /* 749 * free the current buffer, restart the engine 750 * and move forward to the next buffer 751 */ 752 fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd); 753 fec_rx_task_enable(fec); 754 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; 755 } 756 debug("fec_recv: stop\n"); 757 758 return len; 759 } 760 761 static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr) 762 { 763 struct eth_device *edev; 764 struct fec_priv *fec; 765 unsigned char ethaddr[6]; 766 uint32_t start; 767 int ret = 0; 768 769 /* create and fill edev struct */ 770 edev = (struct eth_device *)malloc(sizeof(struct eth_device)); 771 if (!edev) { 772 puts("fec_mxc: not enough malloc memory for eth_device\n"); 773 ret = -ENOMEM; 774 goto err1; 775 } 776 777 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); 778 if (!fec) { 779 puts("fec_mxc: not enough malloc memory for fec_priv\n"); 780 ret = -ENOMEM; 781 goto err2; 782 } 783 784 memset(edev, 0, sizeof(*edev)); 785 memset(fec, 0, sizeof(*fec)); 786 787 edev->priv = fec; 788 edev->init = fec_init; 789 edev->send = fec_send; 790 edev->recv = fec_recv; 791 edev->halt = fec_halt; 792 edev->write_hwaddr = fec_set_hwaddr; 793 794 fec->eth = (struct ethernet_regs *)base_addr; 795 fec->bd = bd; 796 797 fec->xcv_type = CONFIG_FEC_XCV_TYPE; 798 799 /* Reset chip. */ 800 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); 801 start = get_timer(0); 802 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { 803 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { 804 printf("FEC MXC: Timeout reseting chip\n"); 805 goto err3; 806 } 807 udelay(10); 808 } 809 810 /* 811 * Set interrupt mask register 812 */ 813 writel(0x00000000, &fec->eth->imask); 814 815 /* 816 * Clear FEC-Lite interrupt event register(IEVENT) 817 */ 818 writel(0xffffffff, &fec->eth->ievent); 819 820 /* 821 * Set FEC-Lite receive control register(R_CNTRL): 822 */ 823 /* 824 * Frame length=1518; MII mode; 825 */ 826 writel((PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT) | FEC_RCNTRL_FCE | 827 FEC_RCNTRL_MII_MODE, &fec->eth->r_cntrl); 828 fec_mii_setspeed(fec); 829 830 if (dev_id == -1) { 831 sprintf(edev->name, "FEC"); 832 fec->dev_id = 0; 833 } else { 834 sprintf(edev->name, "FEC%i", dev_id); 835 fec->dev_id = dev_id; 836 } 837 fec->phy_id = phy_id; 838 839 miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write); 840 841 eth_register(edev); 842 843 if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { 844 debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); 845 memcpy(edev->enetaddr, ethaddr, 6); 846 } 847 848 return ret; 849 850 err3: 851 free(fec); 852 err2: 853 free(edev); 854 err1: 855 return ret; 856 } 857 858 #ifndef CONFIG_FEC_MXC_MULTI 859 int fecmxc_initialize(bd_t *bd) 860 { 861 int lout = 1; 862 863 debug("eth_init: fec_probe(bd)\n"); 864 lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 865 866 return lout; 867 } 868 #endif 869 870 int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) 871 { 872 int lout = 1; 873 874 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); 875 lout = fec_probe(bd, dev_id, phy_id, addr); 876 877 return lout; 878 } 879 880 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) 881 { 882 struct fec_priv *fec = (struct fec_priv *)dev->priv; 883 fec->mii_postcall = cb; 884 return 0; 885 } 886