| 708f6927 | 11-Dec-2016 |
Peng Fan <peng.fan@nxp.com> |
imx: clock: gate clk before changing pix clk mux
The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux.
Also change enable_lcdif_clock prototype with a new input paramete
imx: clock: gate clk before changing pix clk mux
The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux.
Also change enable_lcdif_clock prototype with a new input parameter to indicate disable or enable.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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| a425bf72 | 30-Oct-2016 |
Eric Nelson <eric@nelint.com> |
ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines
The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are
ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines
The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL.
Add a KConfig entry to allow boards to selectively include the DDR calibration routines.
Signed-off-by: Eric Nelson <eric@nelint.com>
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| 48c7d437 | 30-Oct-2016 |
Eric Nelson <eric@nelint.com> |
mx6: ddr: add routine to return DDR calibration data
Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static m
mx6: ddr: add routine to return DDR calibration data
Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration.
This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run.
Signed-off-by: Eric Nelson <eric@nelint.com>
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| 7f17fb74 | 30-Oct-2016 |
Eric Nelson <eric@nelint.com> |
mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
The DDR calibration routines have scattered support for bus widths other than 64-bits:
-- The mmdc_do_write_level_calibration() routine assume
mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
The DDR calibration routines have scattered support for bus widths other than 64-bits:
-- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL.
Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active.
This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port.
Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Marek Vasut <marex@denx.de>
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| 07e1c0ae | 11-Aug-2016 |
Peng Fan <van.freenix@gmail.com> |
imx: iomux: fix snvs usage for i.MX6ULL
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these p
imx: iomux: fix snvs usage for i.MX6ULL
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
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| 5b66482d | 11-Aug-2016 |
Peng Fan <van.freenix@gmail.com> |
imx: imx6ull: adjust the ldo 1.2v bandgap voltage
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting t
imx: imx6ull: adjust the ldo 1.2v bandgap voltage
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110.
Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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