fsl: PPA: add support PPA image loading from NAND and SD

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.co

fsl: PPA: add support PPA image loading from NAND and SD

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012A

USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided
instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup

armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012A

USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided
instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup.

Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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board: freescale: ls2080a/ls2088a: Enable PPA

Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by

board: freescale: ls2080a/ls2088a: Enable PPA

Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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pci: layerscape: add LS2088A series SoC pcie support

The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.

Signed-off-by: Hou Zhi

pci: layerscape: add LS2088A series SoC pcie support

The LS2088A series SoCs has different physical memory map address and
CCSR registers address against LS2080A series SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203

This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.

Signed-off-by: Ashish Kumar <Ash

armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203

This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

armv8:fsl-layerscape: Avoid RCWSR28 register hard-coding

SerDes information is not necessary to be present in RCWSR29 register.
It may vary from SoC to SoC.

So Avoid RCWSR28 register hard-coding.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhaka

arm: fsl-layerscape: Move QSGMII wriop_init to SoC file

MAC number used per QSGMII is not fixed. It may wary from SoC to SoC.

So move QSGMII wriop_init_dpmac() to SoC file.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8/fsl-layerscape: Update erratum A009635 implementation

Erratum A009635 is valid only for LS2080A SoC and its
personality. Add SoC svr check.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com

armv8/fsl-layerscape: Update erratum A009635 implementation

Erratum A009635 is valid only for LS2080A SoC and its
personality. Add SoC svr check.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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configs: imx6: Select missing BOARD_LATE_INIT

Select missing BOARD_LATE_INIT from configs/ to
respective targets on arch area for Engicam imx6 boards.

Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano

configs: imx6: Select missing BOARD_LATE_INIT

Select missing BOARD_LATE_INIT from configs/ to
respective targets on arch area for Engicam imx6 boards.

Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
configs/bk4r1_defconfig
configs/colibri_vf_defconfig
configs/pcm052_defconfig
i

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
configs/bk4r1_defconfig
configs/colibri_vf_defconfig
configs/pcm052_defconfig
include/configs/colibri_vf.h
include/configs/pcm052.h

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ARM: vf610: move to standard arch/board approach

Move Freescale/NXP Vybrid to a standard arch/board approach, similar
to what has been done to i.MX 6 earlier in commit 89ebc82137be ("ARM:
mx6: move

ARM: vf610: move to standard arch/board approach

Move Freescale/NXP Vybrid to a standard arch/board approach, similar
to what has been done to i.MX 6 earlier in commit 89ebc82137be ("ARM:
mx6: move to a standard arch/board approach").

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

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mx7: Add 1.2GHz speed grade entry

There are recent MX7 parts that have a 1.2GHz speed grade.

Add support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

mx7: Fix the get_cpu_speed_grade_hz() return values

According to the MX7D fuse map the following speed grades are available:

800 MHz
500 MHz
1000 MHz
1200 MHz

So simply return the real frequency

mx7: Fix the get_cpu_speed_grade_hz() return values

According to the MX7D fuse map the following speed grades are available:

800 MHz
500 MHz
1000 MHz
1200 MHz

So simply return the real frequency that corresponds to the speed grade.

With this change we see on boot:

CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

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mx7: Fix speed grade entry

According to the MX7D fuse map the speed grade of the parts, which
return '1' is 500MHz instead of 850MHz, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.este

mx7: Fix speed grade entry

According to the MX7D fuse map the speed grade of the parts, which
return '1' is 500MHz instead of 850MHz, so fix it accordingly.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

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arm: i.MX6UL: add Armadeus Systems OPOS6UL SoM and OPOS6ULDev carrier board

OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.

arm: i.MX6UL: add Armadeus Systems OPOS6UL SoM and OPOS6ULDev carrier board

OPOS6UL is an i.MX6UL based SoM with 256MB RAM, 4GB eMMC and an ethernet
phy. OPOS6ULDev is carrier board for the OPOS6UL.

U-Boot SPL 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09)
Trying to boot from MMC1

U-Boot 2017.03-rc3-00002-g5085c26 (Mar 07 2017 - 09:48:09 +0100)

CPU: Freescale i.MX6UL rev1.0 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 40C
Reset cause: POR
Model: Armadeus Systems OPOS6UL SoM on OPOS6ULDev board
DRAM: 256 MiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
Video: 800x480x18
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only

arm: Migrate SYS_THUMB_BUILD to Kconfig, introduce SPL_SYS_THUMB_BUILD

Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THUMB_BUILD to
control if we build everything or just SPL (or in theory, just U-Boot) in
Thumb2 mode.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>

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imx6: isiotmx6ul: Add FEC support

Add FEC support for Engicam Is.IoT MX6UL module.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarul

imx6: isiotmx6ul: Add FEC support

Add FEC support for Engicam Is.IoT MX6UL module.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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imx6: isiotmx6ul: Add I2C support

Add I2C support for Engicam Is.IoT MX6UL module.

isiotmx6ul> i2c bus
Bus 0: i2c@021a0000
Bus 1: i2c@021a4000
isiotmx6ul> i2c dev 0
Setting bus to 0
isiotmx6ul> i

imx6: isiotmx6ul: Add I2C support

Add I2C support for Engicam Is.IoT MX6UL module.

isiotmx6ul> i2c bus
Bus 0: i2c@021a0000
Bus 1: i2c@021a4000
isiotmx6ul> i2c dev 0
Setting bus to 0
isiotmx6ul> i2c dev
Current bus is 0
isiotmx6ul> i2c speed 100000
Setting bus speed to 100000 Hz
isiotmx6ul> i2c probe
Valid chip addresses: 00 2C 44 78
isiotmx6ul> i2c md 2C 0xff
00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support

Boot from MMC:
-------------
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1

U-Boot 2017.01

arm: imx6ul: Add Engicam Is.IoT MX6UL Starter Kit initial support

Boot from MMC:
-------------
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1

U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)

CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 33C
Reset cause: POR
Model: Engicam Is.IoT MX6UL Starterkit
DRAM: 512 MiB
MMC: FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Net: CPU Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot: 0
isiotmx6ul>

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

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imx: imx7ulp: add EVK board support

Add EVK board support.
Add the evk dts file.

LOG:
U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800)

CPU: Freescale i.MX7ULP rev1.0 at 500 MHz
R

imx: imx7ulp: add EVK board support

Add EVK board support.
Add the evk dts file.

LOG:
U-Boot 2017.03-rc2-00038-gab86c1d (Feb 22 2017 - 15:59:58 +0800)

CPU: Freescale i.MX7ULP rev1.0 at 500 MHz
Reset cause: POR
Boot mode: Dual boot
Model: NXP i.MX7ULP EVK
DRAM: 1 GiB
MMC: FSL_SDHC: 0
In: serial@402D0000
Out: serial@402D0000
Err: serial@402D0000
Net: Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot: 0

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

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mx7ulp: Add HAB boot support

Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF
size for HAB support boot on mx7ulp.

Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk

mx7ulp: Add HAB boot support

Add CAAM clock functions, SEC_CONFIG[1] fuse checking, and default CSF
size for HAB support boot on mx7ulp.

Users need to uncomment the CONFIG_SECURE_BOOT in mx7ulp_evk.h to build
secure uboot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>

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serial: lpuart: restructure lpuart driver

Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg

serial: lpuart: restructure lpuart driver

Drop CONFIG_LPUART_32B_REG.
Move the register structure to a common file include/fsl_lpuart.h
Define lpuart_serial_platdata structure which includes the reg base and flags.
For 32Bit register access, use lpuart_read32/lpuart_write32 which handles
big/little endian.
For 8Bit register access, still use the orignal code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Shaohui Xie <Shaohui.Xie@nxp.com>
Cc: Alison Wang <b18965@freescale.com>

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imx: mx7ulp: Implement the clock functions for i2c driver

Implement the i2c clock enable and get function for mx7ulp. These
functions are required by imx_lpi2c driver.

Signed-off-by: Peng Fan <peng

imx: mx7ulp: Implement the clock functions for i2c driver

Implement the i2c clock enable and get function for mx7ulp. These
functions are required by imx_lpi2c driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

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imx: mx7ulp: Add soc level initialization codes and functions

Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very

imx: mx7ulp: Add soc level initialization codes and functions

Implement soc level functions to get cpu rev, reset cause, enable cache,
etc. We will disable the wdog and init clocks in s_init at very early u-boot
phase.

Since the we are seeking the way to get chip id for mx7ulp, the get_cpu_rev
is hard coded to a fixed value. This may change in future.

Reuse some code in imx-common.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

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imx: mx7ulp: Add clock framework and functions

Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set
clock source, divider, clock rate and parent source.
Users need to include pc

imx: mx7ulp: Add clock framework and functions

Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set
clock source, divider, clock rate and parent source.
Users need to include pcc.h to use the APIs to for peripherals clock. Each
peripheral clock is defined in enum pcc_clk type.

SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD
enablement and settings, and all SCG clock initialization. User need use enum
scg_clk to access each clock source.

In clock.c, we initialize necessary clocks at u-boot s_init and implement the
clock functions used by driver modules to operate clocks dynamically.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

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