1 /* 2 * Copyright (C) 2016 Amarula Solutions B.V. 3 * Copyright (C) 2016 Engicam S.r.l. 4 * Author: Jagan Teki <jagan@amarulasolutions.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 11 #include <asm/io.h> 12 #include <asm/gpio.h> 13 #include <linux/sizes.h> 14 15 #include <asm/arch/clock.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/iomux.h> 18 #include <asm/arch/mx6-pins.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/imx-common/iomux-v3.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 25 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 26 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 27 28 static iomux_v3_cfg_t const uart1_pads[] = { 29 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 30 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 31 }; 32 33 int board_early_init_f(void) 34 { 35 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 36 37 return 0; 38 } 39 40 int board_init(void) 41 { 42 /* Address of boot parameters */ 43 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 44 45 return 0; 46 } 47 48 int dram_init(void) 49 { 50 gd->ram_size = imx_ddr_size(); 51 52 return 0; 53 } 54 55 #ifdef CONFIG_SPL_BUILD 56 #include <libfdt.h> 57 #include <spl.h> 58 59 #include <asm/arch/crm_regs.h> 60 #include <asm/arch/mx6-ddr.h> 61 62 /* MMC board initialization is needed till adding DM support in SPL */ 63 #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) 64 #include <mmc.h> 65 #include <fsl_esdhc.h> 66 67 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 68 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 69 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 70 71 static iomux_v3_cfg_t const usdhc1_pads[] = { 72 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 79 /* VSELECT */ 80 MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 /* CD */ 82 MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), 83 /* RST_B */ 84 MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 85 }; 86 87 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) 88 89 struct fsl_esdhc_cfg usdhc_cfg[1] = { 90 {USDHC1_BASE_ADDR, 0, 4}, 91 }; 92 93 int board_mmc_getcd(struct mmc *mmc) 94 { 95 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 96 int ret = 0; 97 98 switch (cfg->esdhc_base) { 99 case USDHC1_BASE_ADDR: 100 ret = !gpio_get_value(USDHC1_CD_GPIO); 101 break; 102 } 103 104 return ret; 105 } 106 107 int board_mmc_init(bd_t *bis) 108 { 109 int i, ret; 110 111 /* 112 * According to the board_mmc_init() the following map is done: 113 * (U-boot device node) (Physical Port) 114 * mmc0 USDHC1 115 */ 116 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 117 switch (i) { 118 case 0: 119 imx_iomux_v3_setup_multiple_pads( 120 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 121 gpio_direction_input(USDHC1_CD_GPIO); 122 usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 123 break; 124 default: 125 printf("Warning - USDHC%d controller not supporting\n", 126 i + 1); 127 return 0; 128 } 129 130 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 131 if (ret) { 132 printf("Warning: failed to initialize mmc dev %d\n", i); 133 return ret; 134 } 135 } 136 137 return 0; 138 } 139 #endif /* CONFIG_FSL_ESDHC */ 140 141 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { 142 .grp_addds = 0x00000030, 143 .grp_ddrmode_ctl = 0x00020000, 144 .grp_b0ds = 0x00000030, 145 .grp_ctlds = 0x00000030, 146 .grp_b1ds = 0x00000030, 147 .grp_ddrpke = 0x00000000, 148 .grp_ddrmode = 0x00020000, 149 .grp_ddr_type = 0x000c0000, 150 }; 151 152 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { 153 .dram_dqm0 = 0x00000030, 154 .dram_dqm1 = 0x00000030, 155 .dram_ras = 0x00000030, 156 .dram_cas = 0x00000030, 157 .dram_odt0 = 0x00000030, 158 .dram_odt1 = 0x00000030, 159 .dram_sdba2 = 0x00000000, 160 .dram_sdclk_0 = 0x00000008, 161 .dram_sdqs0 = 0x00000038, 162 .dram_sdqs1 = 0x00000030, 163 .dram_reset = 0x00000030, 164 }; 165 166 static struct mx6_mmdc_calibration mx6_mmcd_calib = { 167 .p0_mpwldectrl0 = 0x00070007, 168 .p0_mpdgctrl0 = 0x41490145, 169 .p0_mprddlctl = 0x40404546, 170 .p0_mpwrdlctl = 0x4040524D, 171 }; 172 173 struct mx6_ddr_sysinfo ddr_sysinfo = { 174 .dsize = 0, 175 .cs_density = 20, 176 .ncs = 1, 177 .cs1_mirror = 0, 178 .rtt_wr = 2, 179 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 180 .walat = 1, /* Write additional latency */ 181 .ralat = 5, /* Read additional latency */ 182 .mif3_mode = 3, /* Command prediction working mode */ 183 .bi_on = 1, /* Bank interleaving enabled */ 184 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 185 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 186 .ddr_type = DDR_TYPE_DDR3, 187 }; 188 189 static struct mx6_ddr3_cfg mem_ddr = { 190 .mem_speed = 800, 191 .density = 4, 192 .width = 16, 193 .banks = 8, 194 .rowaddr = 15, 195 .coladdr = 10, 196 .pagesz = 2, 197 .trcd = 1375, 198 .trcmin = 4875, 199 .trasmin = 3500, 200 }; 201 202 static void ccgr_init(void) 203 { 204 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 205 206 writel(0x00c03f3f, &ccm->CCGR0); 207 writel(0xfcffff00, &ccm->CCGR1); 208 writel(0x0cffffcc, &ccm->CCGR2); 209 writel(0x3f3c3030, &ccm->CCGR3); 210 writel(0xff00fffc, &ccm->CCGR4); 211 writel(0x033f30ff, &ccm->CCGR5); 212 writel(0x00c00fff, &ccm->CCGR6); 213 } 214 215 static void spl_dram_init(void) 216 { 217 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); 218 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); 219 } 220 221 void board_init_f(ulong dummy) 222 { 223 /* setup AIPS and disable watchdog */ 224 arch_cpu_init(); 225 226 ccgr_init(); 227 228 /* iomux and setup of i2c */ 229 board_early_init_f(); 230 231 /* setup GP timer */ 232 timer_init(); 233 234 /* UART clocks enabled and gd valid - init serial console */ 235 preloader_console_init(); 236 237 /* DDR initialization */ 238 spl_dram_init(); 239 240 /* Clear the BSS. */ 241 memset(__bss_start, 0, __bss_end - __bss_start); 242 243 /* load/boot image from boot device */ 244 board_init_r(NULL, 0); 245 } 246 #endif /* CONFIG_SPL_BUILD */ 247