| #
40cb90ee |
| 03-Apr-2008 |
Guennadi Liakhovetski <lg@denx.de> |
net: make ARP timeout configurable
Currently the timeout waiting for an ARP reply is hard set to 5 seconds. On i.MX31ADS due to a hardware "strangeness" up to four first IP packets to the boards get
net: make ARP timeout configurable
Currently the timeout waiting for an ARP reply is hard set to 5 seconds. On i.MX31ADS due to a hardware "strangeness" up to four first IP packets to the boards get lost, which typically are ARP replies. By configuring the timeout to a lower value we significantly improve the first network transfer time on this board. The timeout is specified in milliseconds, later internally it is converted to deciseconds, because it has to be converted to hardware ticks, and CFG_HZ ranges from 900 to 27000000 on different boards.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
show more ...
|
| #
7ce63709 |
| 15-Apr-2008 |
Guennadi Liakhovetski <lg@denx.de> |
RTC driver for MC13783
MC13783 is a multifunction IS with an SPI interface to the host. This driver handles the RTC controller in this chip.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
|
| #
38254f45 |
| 15-Apr-2008 |
Guennadi Liakhovetski <lg@denx.de> |
New i.MX31 SPI driver
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for
New i.MX31 SPI driver
This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
show more ...
|
| #
7d721e34 |
| 14-Apr-2008 |
Bartlomiej Sieka <tur@semihalf.com> |
Boot-related documentation update
- document 'bootm_low' and 'bootm_size' environment variables - update inaccurate CFG_BOOTMAPSZ entry
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
|
| #
8c8428a5 |
| 13-Apr-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of /home/wd/git/u-boot/custodians
|
| #
d6f98e76 |
| 13-Apr-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flash
|
| #
58a3cbbf |
| 13-Apr-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://www.denx.de/git/u-boot-sparc
|
| #
96ef831f |
| 03-Apr-2008 |
Guennadi Liakhovetski <lg@denx.de> |
cfi_flash: Support buffered writes on non-standard Spansion NOR flash
Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit series require different addresses for buffered write comm
cfi_flash: Support buffered writes on non-standard Spansion NOR flash
Some NOR flash chip from Spansion, for example, the s29ws-n MirrorBit series require different addresses for buffered write commands. Define a configuration option to support buffered writes on those chips. A more elegant solution would be to automatically detect those chips by parsing their CFI records, but that would require introduction of a fixup table into the cfi_flash driver.
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
show more ...
|
| #
b330990c |
| 28-Mar-2008 |
Daniel Hellstrom <daniel@gaisler.com> |
SPARC: Added support for SPARC LEON2 SOC Processor.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
|
| #
1e9a164e |
| 26-Mar-2008 |
Daniel Hellstrom <daniel@gaisler.com> |
SPARC: Added support for SPARC LEON3 SOC processor.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
|
| #
c2f02da2 |
| 28-Mar-2008 |
Daniel Hellstrom <daniel@gaisler.com> |
SPARC: Added generic support for SPARC architecture.
Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
|
| #
aeff6d50 |
| 07-Apr-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://www.denx.de/git/u-boot-fdt
|
| #
f9eabcb3 |
| 07-Apr-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://www.denx.de/git/u-boot-net
|
| #
6de54203 |
| 07-Apr-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
|
| #
6fe2946f |
| 28-Mar-2008 |
Kim Phillips <kim.phillips@freescale.com> |
remove remaining CONFIG_OF_HAS_{UBOOT_ENV,BD_T} code
finish off what commit 43ddd9c820fec44816188f53346b464e20b3142d, "Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T" started.
Sig
remove remaining CONFIG_OF_HAS_{UBOOT_ENV,BD_T} code
finish off what commit 43ddd9c820fec44816188f53346b464e20b3142d, "Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_T" started.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
show more ...
|
| #
ac3315c2 |
| 06-Mar-2008 |
Andre Schwarz <andre.schwarz@matrix-vision.de> |
new PHY @ e1000 - 2nd try
Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
Signed-off-by: Andre Schwarz <andre.schwarz@ma
new PHY @ e1000 - 2nd try
Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
show more ...
|
| #
d9a2f416 |
| 25-Mar-2008 |
Aras Vaichas <arasv@magtech.com.au> |
DHCP request fix for Windows Server 2003
Added option CONFIG_BOOTP_DHCP_REQUEST_DELAY. This provides an optional delay before sending "DHCP Request" in net/bootp.c. Required to overcome interoperabi
DHCP request fix for Windows Server 2003
Added option CONFIG_BOOTP_DHCP_REQUEST_DELAY. This provides an optional delay before sending "DHCP Request" in net/bootp.c. Required to overcome interoperability problems with Windows Server 200x DHCP server when U-Boot client responds too fast for server to handle.
Signed-off-by: Aras Vaichas <arasv@magtech.com.au> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
show more ...
|
| #
3596d55e |
| 29-Mar-2008 |
Gerald Van Baren <vanbaren@cideas.com> |
Merge git://www.denx.de/git/u-boot into uboot
|
| #
5e12e75d |
| 28-Mar-2008 |
Stefan Roese <sr@denx.de> |
ppc: Small change to CFG_MEM_TOP_HIDE description
Signed-off-by: Stefan Roese <sr@denx.de>
|
| #
14f73ca6 |
| 26-Mar-2008 |
Stefan Roese <sr@denx.de> |
ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top
ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"
If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally.
This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation:
CHIP_11: End of memory range area restricted access. Category: 3
Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus.
Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU.
Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux.
This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia
The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this:
PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */
It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome.
Signed-off-by: Stefan Roese <sr@denx.de>
show more ...
|
| #
d4ee711d |
| 26-Mar-2008 |
Anatolij Gustschin <agust@denx.de> |
README: update documentation (availability, links, etc.)
Fix typo in README
Signed-off-by: Anatolij Gustschin <agust@denx.de>
|
| #
da8808df |
| 26-Mar-2008 |
Joakim Tjernlund <Joakim.Tjernlund@transmode.se> |
Add CFG_RTC_DS1337_NOOSC to turn off OSC output
The default settings for RTC DS1337 keeps the OSC output, 32,768 Hz, on. This add CFG_RTC_DS1337_NOOSC to turn it off.
Signed-off-by: Joakim Tjernlun
Add CFG_RTC_DS1337_NOOSC to turn off OSC output
The default settings for RTC DS1337 keeps the OSC output, 32,768 Hz, on. This add CFG_RTC_DS1337_NOOSC to turn it off.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
show more ...
|
| #
b951f8d3 |
| 26-Mar-2008 |
Wolfgang Denk <wd@denx.de> |
Merge branch 'master_merge_new-image' of /home/tur/git/u-boot
|
| #
218ca724 |
| 26-Mar-2008 |
Wolfgang Denk <wd@denx.de> |
README: update documentation (availability, links, etc.)
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
| #
27f33e9f |
| 26-Mar-2008 |
Bartlomiej Sieka <tur@semihalf.com> |
Merge branch 'new-image' of git://www.denx.de/git/u-boot-testing
Conflicts:
common/cmd_bootm.c cpu/mpc8xx/cpu.c
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
|