refactor(plat/nxp): use a unified errata api

Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enab

refactor(plat/nxp): use a unified errata api

Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enabled on current platform.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5eab3f338db6b46c57cbad475819043fc60ca6d3

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refactor(plat/soc-lx2160): move errata to common directory

Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between differen

refactor(plat/soc-lx2160): move errata to common directory

Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between different platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ib149b3eac365bdb593331e9f38f0b89d92c9c0d1

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feat(plat/allwinner): add R329 support

Allwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A
support for it, to provide a PSCI implementation containing CPU
boot/shutdown and SoC reset.

feat(plat/allwinner): add R329 support

Allwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A
support for it, to provide a PSCI implementation containing CPU
boot/shutdown and SoC reset.

Change-Id: I0fa37ee9b4a8e0e1137bf7cf7d614b6ca9624bfe
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd7

refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Clus

refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.

Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.

Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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fix(plat/allwinner): delay after enabling CPU power

Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.

Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a

fix(plat/allwinner): delay after enabling CPU power

Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.

Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a77a1619b1b3
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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Merge "fix(rpi4): drop /memreserve/ region" into integration

feat(board/rdn2): add tzc master source ids for soc dma

Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
fr

feat(board/rdn2): add tzc master source ids for soc dma

Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
from these DMAs targeting DRAM.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c

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fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default

It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug

fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default

It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug found
in U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver
for Armada 37xx SoC) which results in SError interrupt caused by AXI
SLVERR on external access (syndrome 0xbf000002) and immediate kernel
panic.

Now when proper patches are in both U-Boot and Linux kernel projects,
this workaround in TF-A should not have to be enabled by default
anymore as it has unwanted side effects like propagating all external
aborts, including non-fatal/correctable into EL3 and making them as
fatal which cause immediate abort.

Add documentation for HANDLE_EA_EL3_FIRST build option into Marvell
Armada build section.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491

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fix(plat/marvell/a3k): update information about PCIe abort hack

A3700 plat_ea_handler was introduced into TF-A codebase just because of
bugs in U-Boot and Linux kernel PCIe controller driver pci-aar

fix(plat/marvell/a3k): update information about PCIe abort hack

A3700 plat_ea_handler was introduced into TF-A codebase just because of
bugs in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c.

These bugs were finally fixed in both U-Boot and Linux kernel drivers:
https://source.denx.de/u-boot/u-boot/-/commit/eccbd4ad8e4e182638eafbfb87ac139c04f24a01
https://git.kernel.org/stable/c/f18139966d072dab8e4398c95ce955a9742e04f7

Add all these information into comments, including printing error
message into a3k plat_ea_handler. Also check that abort is really
asynchronous and comes from lower level than EL3.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I46318d221b39773d5e25b3a0221d7738736ffdf1

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errata: workaround for Cortex-A710 errata 1987031

Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN:

errata: workaround for Cortex-A710 errata 1987031

Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token=

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179

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errata: workaround for Cortex-A78 errata 1952683

Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.

A78 SDEN : https://develop

errata: workaround for Cortex-A78 errata 1952683

Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of
the Cortex-A78 processor core, and it was fixed in r1p0.

A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0

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docs(ff-a): managed exit parameter separation

As of DEN0077A FF-A v1.1 Beta0 section 5.2, managed exit
support is moved out of messaging-method field and is described in a
separate field.

Signed-of

docs(ff-a): managed exit parameter separation

As of DEN0077A FF-A v1.1 Beta0 section 5.2, managed exit
support is moved out of messaging-method field and is described in a
separate field.

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: Icb12d9dc0d10b11c105dc1920e5212b0359af147

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Merge changes I976aef15,I11ae679f into integration

* changes:
feat(plat/xilinx/zynqmp): add support for runtime feature config
feat(plat/xilinx/zynqmp): sync IOCTL IDs

Merge "fix(el3_runtime): correct CASSERT for pauth" into integration

Merge "fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit" into integration

Merge "fix(plat/st): apply security at the end of BL2" into integration

refactor(gicv3): rename GIC Clayton to GIC-700

The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".

Rename occurences of Clayton in comments and macro names to

refactor(gicv3): rename GIC Clayton to GIC-700

The GIC IP formerly known as "GIC Clayton" has been released under the
name of "GIC-700".

Rename occurences of Clayton in comments and macro names to reflect the
official name.

Change-Id: Ie8c55f7da7753127d58c8382b0033c1b486f7909
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options

Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.

Signed-off-by: Pali Rohár <pali

docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options

Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I852f60569a9a49269ae296c56cc83eb438528bee

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Merge "docs(spmc): threat model document" into integration

Merge "fix(plat/arm_fpga): enable AMU extension" into integration

fix(el3_runtime): correct CASSERT for pauth

clang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR=1)
and CRASH_REPORTING (DEBUG=1) options are enabled:

include/lib/el3_runtime/cpu_data.h:135:

fix(el3_runtime): correct CASSERT for pauth

clang build breaks when both ENABLE_PAUTH (BRANCH_PROTECTOR=1)
and CRASH_REPORTING (DEBUG=1) options are enabled:

include/lib/el3_runtime/cpu_data.h:135:2: error: redefinition of typedef
'assert_cpu_data_crash_stack_offset_mismatch' is a C11 feature [-Werror,
-Wtypedef-redefinition]
assert_cpu_data_crash_stack_offset_mismatch);
^
include/lib/el3_runtime/cpu_data.h:128:2: note: previous definition is here
assert_cpu_data_crash_stack_offset_mismatch);
^
1 error generated.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I22c8c45a94a64620007979d55412dbb57b11b813

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feat(cpus): workaround for Cortex A78 AE erratum 1941500

Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting

feat(cpus): workaround for Cortex A78 AE erratum 1941500

Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.

This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.

SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900

Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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docs(spmc): threat model document

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib5f443a6997239d6ba4655d7df6c3fc61d45f991

Merge "feat(cpus): workaround for Cortex A78 AE erratum 1951502" into integration