fix(drivers/usb): add a optional ops get_other_speed_config_desc

Correctly handle USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION request
in USB driver and support a different result than
USB_DESC_TYPE_CONF

fix(drivers/usb): add a optional ops get_other_speed_config_desc

Correctly handle USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION request
in USB driver and support a different result than
USB_DESC_TYPE_CONFIGURATION with the new optional ops
get_other_speed_config_desc().

The support of this descriptor is optionnal and is only
required when high-speed capable device which can operate at its
other possible speed.

This patch allows to remove the pbuf update in usb_core_get_desc()
and solves an issue on USB re-enumeration on STM32MP15 platform
as the result of get_config_desc() is a const array.
This issue is not see on normal use-case, as the USB enumeration
is only done in ROM code and TF-A reuse the same USB descritors.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8edcc1e45065ab4e45d48f4bc37b49120674fdb0

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fix(drivers/usb): remove unnecessary cast

Remove the unnecessary cast on the result of function which
already return the correct type.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

fix(drivers/usb): remove unnecessary cast

Remove the unnecessary cast on the result of function which
already return the correct type.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie21f7e78a880d30d1f31e32b3d2c3fb09489d65b

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fix(errata): workaround for Neoverse-N2 erratum 2280757

Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[2

fix(errata): workaround for Neoverse-N2 erratum 2280757

Neoverse-N2 erratum 2280757 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I615bcc1f993c45659b8b6f1a34fca0eb490f8add

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fix(errata): workaround for Neoverse-N2 erratum 2242400

Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[

fix(errata): workaround for Neoverse-N2 erratum 2242400

Neoverse-N2 erratum 2242400 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[17] to 1'b1 followed by setting few
system control registers to specific values as per attached
SDEN document.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I6a9cb4a23238b8b511802a1ee9fcc5b207137649

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fix(errata): workaround for Neoverse-N2 erratum 2138958

Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[

fix(errata): workaround for Neoverse-N2 erratum 2138958

Neoverse-N2 erratum 2138958 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR5_EL1[13] to 1'b1.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I5247f8f8eef08d38c169aad6d2c5501ac387c720

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fix(errata): workaround for Neoverse-N2 erratum 2242415

Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[2

fix(errata): workaround for Neoverse-N2 erratum 2242415

Neoverse-N2 erratum 2242415 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to set CPUACTLR_EL1[22] to 1'b1. Setting CPUACTLR_EL1[22]
will cause CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I442be81fbc32e21fed51a84f59584df17f845e96

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fix(arm_fpga): Change PL011 UART IRQ

About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-

fix(arm_fpga): Change PL011 UART IRQ

About a year ago there was a change in the underlying Arm platform design
framework, which lead to a reorganisation of the interrupt map (to make
room for multi-chip designs).

This lead to the PL011 debug UART interrupt to move from SPI 115 to SPI
415. Unfortunately there is not a good or easy way to auto-detect this
change: Flooding the TX FIFO and checking GICD_ISPENDR registers might
be possible, but sounds a bit over the top for BL31.

So we would need to break one group of images: newer ones, as we do right
now, or older ones.
By now every interesting FPGA image seems to use the newer IRQ, so in
the interest of having a smooth experience for most users, lets switch
to this IRQ.

When people are interested in older images, they can either change the
number back in the .dts file, or provide a patched DTB on the FPGA
command line.

Change-Id: I3c7e7b711f5142813bd94eecde3095a4fc555bb3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(arm_fpga): write UART baud base clock frequency into DTB

Since we now autodetect the actual system frequency, which is also used
as the base for the UART baudrate generation, we should update t

feat(arm_fpga): write UART baud base clock frequency into DTB

Since we now autodetect the actual system frequency, which is also used
as the base for the UART baudrate generation, we should update the value
currently hard-coded in the DT. Otherwise Linux will reprogram the
divider using a potentially wrong base rate, which breaks the UART
output.

Find the DT node referenced by the UART node as the clock rate, and set
the "clock-frequency" property in that node to the detected system
frequency. This will let Linux reprogram the divider to the same value,
preserving the actual baudrate.

Change-Id: Ib5a936849f2198577b86509f032751d5386ed2f8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(arm_fpga): query PL011 to learn system frequency

The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
si

feat(arm_fpga): query PL011 to learn system frequency

The Arm FPGAs run in mostly one clock domain, which is used for the CPU
cores, the generic timer, and also the UART baudrate base clock. This
single clock can have different rates, to compensate for different IP
complexity. So far most images used 10 MHz, but different rates start to
appear.

To avoid patching both the arch timer frequency and UART baud base fixed
clock in the DTB manually, we would like to set the clock rate
automatically. Fortunately the SCP firmware has the actual clock rate
hard coded, and already programs the PL011 UART baud divider register
with the correct value to achieve a 38400 bps baudrate.

So read the two PL011 baudrate divider values and re-calculate the
original base clock from there, to use as the arch timer frequency. If
the arch timer DT node contains a clock-frequency property, we use that
instead, to support overriding and disabling this autodetection.

Change-Id: I9857fbb418deb4644aeb2816f1102796f9bfd3bb
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(arm_fpga): move command line code into separate function

The code dealing with finding the command line and inserting that into
the DTB is somewhat large, and drowns the other DT handlers i

refactor(arm_fpga): move command line code into separate function

The code dealing with finding the command line and inserting that into
the DTB is somewhat large, and drowns the other DT handlers in our
fpga_prepare_dtb() function.

Move that code into a separate function, to improve readability.

Change-Id: I828203c4bb248d38a2562fcb6afdefedf3179f8d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(fdt): avoid output on missing DT property

When we use our fdt_read_uint32* helper functions, we output a warning
on not finding the requested property.

However non-existing properties are not t

fix(fdt): avoid output on missing DT property

When we use our fdt_read_uint32* helper functions, we output a warning
on not finding the requested property.

However non-existing properties are not that uncommon, and *trying* to
read such a property is actually a nice way of checking its existence.

Since we already return a specific error value in this case, the caller
can easily check this and give a more specific error message, if needed.
When the caller decides to properly handle the error (fallback, default
value, etc), a message on the console is quite misleading.

Demote the message to a VERBOSE, so normal builds will not spam the
console with pointless messages.

Change-Id: I7a279a4ee0147c5f4a0503d0a8745c6cfea58be5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(arm_fpga): add ITS autodetection

Some FPGAs come with a GIC that has an ITS block configured. Since the
ITS sits between the distributor and redistributors, we can autodetect
that, and already

feat(arm_fpga): add ITS autodetection

Some FPGAs come with a GIC that has an ITS block configured. Since the
ITS sits between the distributor and redistributors, we can autodetect
that, and already adjust the GICR base address.

To also make this ITS usable, add an ITS node to our base DTB, and
remove that should we not find an ITS during the scan for the
redistributor. This allows to use the same TF-A binary for FPGA images
with or without an ITS.

Change-Id: I4c0417dec7bccdbad8cbca26fa2634950fc50a66
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(arm_fpga): determine GICR base by probing

When an Arm Ltd GIC (Arm GIC-[567]00) is instantiated with one or more
ITSes, the ITS MMIO frames appear between the distributor and
redistributor addr

feat(arm_fpga): determine GICR base by probing

When an Arm Ltd GIC (Arm GIC-[567]00) is instantiated with one or more
ITSes, the ITS MMIO frames appear between the distributor and
redistributor addresses. This makes the beginning of the redistributor
region dependent on the existence and number of ITSes.

To support various FPGA images, with and without ITSes, probe the
addresses in question, to learn whether they accommodate an ITS or a
redistributor. This can be safely done by looking at the PIDR[01]
registers, which contain an ID code for each region, documented in the
Arm GIC TRMs.

We try to find all ITSes instantiated, and skip either two or four 64K
frames, depending on GICv4.1 support. At some point we will find the
first redistributor; this address we then update in the DTB.

Change-Id: Iefb88c2afa989e044fe0b36b7020b56538c60b07
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(gicv3): introduce GIC component identification

The GIC specification describes ID registers in each GIC register frame
(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC
i

feat(gicv3): introduce GIC component identification

The GIC specification describes ID registers in each GIC register frame
(PIDRx), which can be used to identify a GIC component. The Arm Ltd. GIC
implementations use certain ID values to identify the distributor, the
redistributors and other parts like ITSes.

Introduce a function that reads those part number IDs, which are spread
over two registers. The actual numbers are only meaningful in connection
with a certain GIC model, which would need to be checked beforehand, by
the caller.

Change-Id: Ia6ff326a1e8b12664e4637bc8e2683d2b5c7721c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(libfdt): also allow changing base address

For platforms where we don't know the number of cores at compile time,
the size of the GIC redistributor frame is then also undetermined, since
it depe

feat(libfdt): also allow changing base address

For platforms where we don't know the number of cores at compile time,
the size of the GIC redistributor frame is then also undetermined, since
it depends on this number of cores.
On top of this the GICR base address can also change, when an unknown
number of ITS frames (including zero) take up space between the
distributor and redistributor.

So while those two adjustments are done for independent reasons, the
code for doing so is very similar, so we should utilise the existing
fdt_adjust_gic_redist() function.

Add an (optional) gicr_base parameters to the prototype, so callers can
choose to also adjust this base address later, if needed.

Change-Id: Id39c0ba83e7401fdff1944e86950bb7121f210e8
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(arm_fpga): avoid re-linking from executable ELF file

When we build the convenience firmware package file for the Arm FPGA
boards (bl31.axf), we combine trampolines, the DTB and the actual BL31
c

fix(arm_fpga): avoid re-linking from executable ELF file

When we build the convenience firmware package file for the Arm FPGA
boards (bl31.axf), we combine trampolines, the DTB and the actual BL31
code into one ELF file, which is more a "container with load addresses"
than an actual executable. So far ld was fine with us using bl31.elf as
an input file, but binutils 2.35 changed that and complains about
taking an *executable* ELF file as in *input* to the linker:
-----------------
aarch64-none-elf-ld.bfd: cannot use executable file 'build/arm_fpga/debug/./bl31/bl31.elf' as input to a link
-----------------

Fortunately we don't need the actual BL31 ELF file for *that* part of
the linking, so can use the just created bl31.bin binary version of it.
Actually that shrinks the file, as we needlessly included the .BSS
section in the final file before.

Using the binary works with both older and newer toolchains versions, so
let's do this unconditionally.

Change-Id: Ib7e697f8363499123f7cb860f118f182d0830768
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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chore(docs): update supported FVP models doc

Update supported models list according to changes for v2.6 release in
ci/tf-a-ci-scripts repository:
* general FVP model update: d10c1b9
* gic600 update:

chore(docs): update supported FVP models doc

Update supported models list according to changes for v2.6 release in
ci/tf-a-ci-scripts repository:
* general FVP model update: d10c1b9
* gic600 update: aa2548a
* CSS prebults model update: f1c3a4f

Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Change-Id: If2841f05238facb3cace7d5c8a78083d54f35e27

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fix(drivers/usb): remove deadcode when USBD_EP_NB = 1

CID 373791: Control flow issues (DEADCODE)
CID 373789: Control flow issues (DEADCODE)

Since USBD_EP_NB = 1 for DFU stack on STMP32MP15 plat

fix(drivers/usb): remove deadcode when USBD_EP_NB = 1

CID 373791: Control flow issues (DEADCODE)
CID 373789: Control flow issues (DEADCODE)

Since USBD_EP_NB = 1 for DFU stack on STMP32MP15 platform (only EP0 is
required for DFU support) the value of num can't be different of 0
and the code can't be reached in usb_core_receive / usb_core_transmit.

Add a simple sub-function with this part of code.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I07a56909bb1e6de19ce52da7945b6d2916be8538

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fix(drivers/usb): fix Null pointer dereferences in usb_core_set_config

Correct the invalid test on NULL pointer pdev->class in
usb_core_set_config function.

This patch fix the coverity errors:

*

fix(drivers/usb): fix Null pointer dereferences in usb_core_set_config

Correct the invalid test on NULL pointer pdev->class in
usb_core_set_config function.

This patch fix the coverity errors:

** CID 373790: Null pointer dereferences (FORWARD_NULL)
/drivers/usb/usb_device.c: 182 in usb_core_set_config()

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I83e43261bafa2d47f800e56df0b047a6c58a1e29

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feat(SPMD): route secure interrupts to SPMC

Define a handler in the SPMD to route secure interrupts occurring while
the normal world runs. On a Group1 Secure interrupt (with a GICv3 or a
Group0 inte

feat(SPMD): route secure interrupts to SPMC

Define a handler in the SPMD to route secure interrupts occurring while
the normal world runs. On a Group1 Secure interrupt (with a GICv3 or a
Group0 interrupt on GICv2), the normal world is pre-empted to EL3 and
redirected to the SPMD/SPMC for further handling.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: I1350d74048c5549a2af8da0ba004c08512cc006a

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Merge changes from topic "fix_checkpatch_merges" into integration

* changes:
fix(plat/st): remove double space
fix(checkpatch): do not check merge commits

feat(tc0): add Ivy partition

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: Ie9d6a77722b2350c8479ecf7b0df701428e4d

feat(tc0): add Ivy partition

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
Change-Id: Ie9d6a77722b2350c8479ecf7b0df701428e4da73

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Merge "docs(gcc): update GCC to version 10.3-2021.07" into integration

fix(plat/st): remove double space

Replace double space with single space in stm32cubeprogrammer_usb.c.

Change-Id: I717b136119e85fe8e25dd540758525f995200458
Signed-off-by: Yann Gautier <yann.gautier

fix(plat/st): remove double space

Replace double space with single space in stm32cubeprogrammer_usb.c.

Change-Id: I717b136119e85fe8e25dd540758525f995200458
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(checkpatch): do not check merge commits

Add the --no-merges option when listing patches to check with rev-list
command, when running make checkpatch.

Change-Id: I47f3f5dfe358ed2b960a754f70aec0d

fix(checkpatch): do not check merge commits

Add the --no-merges option when listing patches to check with rev-list
command, when running make checkpatch.

Change-Id: I47f3f5dfe358ed2b960a754f70aec0dc3c2b4536
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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