1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <common/fdt_fixup.h> 11 #include <common/fdt_wrappers.h> 12 #include <drivers/arm/gicv3.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/extensions/spe.h> 16 #include <lib/mmio.h> 17 #include <libfdt.h> 18 19 #include "fpga_private.h" 20 #include <plat/common/platform.h> 21 #include <platform_def.h> 22 23 static entry_point_info_t bl33_image_ep_info; 24 volatile uint32_t secondary_core_spinlock; 25 26 uintptr_t plat_get_ns_image_entrypoint(void) 27 { 28 #ifdef PRELOADED_BL33_BASE 29 return PRELOADED_BL33_BASE; 30 #else 31 return 0ULL; 32 #endif 33 } 34 35 uint32_t fpga_get_spsr_for_bl33_entry(void) 36 { 37 return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 38 } 39 40 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 41 u_register_t arg2, u_register_t arg3) 42 { 43 /* Add this core to the VALID mpids list */ 44 fpga_valid_mpids[plat_my_core_pos()] = VALID_MPID; 45 46 /* 47 * Notify the secondary CPUs that the C runtime is ready 48 * so they can announce themselves. 49 */ 50 secondary_core_spinlock = C_RUNTIME_READY_KEY; 51 dsbish(); 52 sev(); 53 54 fpga_console_init(); 55 56 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 57 bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry(); 58 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 59 60 /* Set x0-x3 for the primary CPU as expected by the kernel */ 61 bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE; 62 bl33_image_ep_info.args.arg1 = 0U; 63 bl33_image_ep_info.args.arg2 = 0U; 64 bl33_image_ep_info.args.arg3 = 0U; 65 } 66 67 void bl31_plat_arch_setup(void) 68 { 69 } 70 71 void bl31_platform_setup(void) 72 { 73 /* Write frequency to CNTCRL and initialize timer */ 74 generic_delay_timer_init(); 75 76 /* 77 * Before doing anything else, wait for some time to ensure that 78 * the secondary CPUs have populated the fpga_valid_mpids array. 79 * As the number of secondary cores is unknown and can even be 0, 80 * it is not possible to rely on any signal from them, so use a 81 * delay instead. 82 */ 83 mdelay(5); 84 85 /* 86 * On the event of a cold reset issued by, for instance, a reset pin 87 * assertion, we cannot guarantee memory to be initialized to zero. 88 * In such scenario, if the secondary cores reached 89 * plat_secondary_cold_boot_setup before the primary one initialized 90 * .BSS, we could end up having a race condition if the spinlock 91 * was not cleared before. 92 * 93 * Similarly, if there were a reset before the spinlock had been 94 * cleared, the secondary cores would find the lock opened before 95 * .BSS is cleared, causing another race condition. 96 * 97 * So clean the spinlock as soon as we think it is safe to reduce the 98 * chances of any race condition on a reset. 99 */ 100 secondary_core_spinlock = 0UL; 101 102 /* Initialize the GIC driver, cpu and distributor interfaces */ 103 plat_fpga_gic_init(); 104 } 105 106 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 107 { 108 entry_point_info_t *next_image_info; 109 next_image_info = &bl33_image_ep_info; 110 111 /* Only expecting BL33: the kernel will run in EL2NS */ 112 assert(type == NON_SECURE); 113 114 /* None of the images can have 0x0 as the entrypoint */ 115 if (next_image_info->pc) { 116 return next_image_info; 117 } else { 118 return NULL; 119 } 120 } 121 122 /* 123 * Even though we sell the FPGA UART as an SBSA variant, it is actually 124 * a full fledged PL011. So the baudrate divider registers exist. 125 */ 126 #ifndef UARTIBRD 127 #define UARTIBRD 0x024 128 #define UARTFBRD 0x028 129 #endif 130 131 /* Round an integer to the closest multiple of a value. */ 132 static unsigned int round_multiple(unsigned int x, unsigned int multiple) 133 { 134 if (multiple < 2) { 135 return x; 136 } 137 138 return ((x + (multiple / 2 - 1)) / multiple) * multiple; 139 } 140 141 #define PL011_FRAC_SHIFT 6 142 #define FPGA_DEFAULT_BAUDRATE 38400 143 #define PL011_OVERSAMPLING 16 144 static unsigned int pl011_freq_from_divider(unsigned int divider) 145 { 146 unsigned int freq; 147 148 freq = divider * FPGA_DEFAULT_BAUDRATE * PL011_OVERSAMPLING; 149 150 return freq >> PL011_FRAC_SHIFT; 151 } 152 153 /* 154 * The FPGAs run most peripherals from one main clock, among them the CPUs, 155 * the arch timer, and the UART baud base clock. 156 * The SCP knows this frequency and programs the UART clock divider for a 157 * 38400 bps baudrate. Recalculate the base input clock from there. 158 */ 159 static unsigned int fpga_get_system_frequency(void) 160 { 161 const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE; 162 int node, err; 163 164 /* 165 * If the arch timer DT node has an explicit clock-frequency property 166 * set, use that, to allow people overriding auto-detection. 167 */ 168 node = fdt_node_offset_by_compatible(fdt, 0, "arm,armv8-timer"); 169 if (node >= 0) { 170 uint32_t freq; 171 172 err = fdt_read_uint32(fdt, node, "clock-frequency", &freq); 173 if (err >= 0) { 174 return freq; 175 } 176 } 177 178 node = fdt_node_offset_by_compatible(fdt, 0, "arm,pl011"); 179 if (node >= 0) { 180 uintptr_t pl011_base; 181 unsigned int divider; 182 183 err = fdt_get_reg_props_by_index(fdt, node, 0, 184 &pl011_base, NULL); 185 if (err >= 0) { 186 divider = mmio_read_32(pl011_base + UARTIBRD); 187 divider <<= PL011_FRAC_SHIFT; 188 divider += mmio_read_32(pl011_base + UARTFBRD); 189 190 /* 191 * The result won't be exact, due to rounding errors, 192 * but the input frequency was a multiple of 250 KHz. 193 */ 194 return round_multiple(pl011_freq_from_divider(divider), 195 250000); 196 } else { 197 WARN("Cannot read PL011 MMIO base\n"); 198 } 199 } else { 200 WARN("No PL011 DT node\n"); 201 } 202 203 /* No PL011 DT node or calculation failed. */ 204 return FPGA_DEFAULT_TIMER_FREQUENCY; 205 } 206 207 unsigned int plat_get_syscnt_freq2(void) 208 { 209 return fpga_get_system_frequency(); 210 } 211 212 #define CMDLINE_SIGNATURE "CMD:" 213 214 static int fpga_dtb_set_commandline(void *fdt, const char *cmdline) 215 { 216 int chosen; 217 const char *eol; 218 char nul = 0; 219 int slen, err; 220 221 chosen = fdt_add_subnode(fdt, 0, "chosen"); 222 if (chosen == -FDT_ERR_EXISTS) { 223 chosen = fdt_path_offset(fdt, "/chosen"); 224 } 225 226 if (chosen < 0) { 227 return chosen; 228 } 229 230 /* 231 * There is most likely an EOL at the end of the 232 * command line, make sure we terminate the line there. 233 * We can't replace the EOL with a NUL byte in the 234 * source, as this is in read-only memory. So we first 235 * create the property without any termination, then 236 * append a single NUL byte. 237 */ 238 eol = strchr(cmdline, '\n'); 239 if (eol == NULL) { 240 eol = strchr(cmdline, 0); 241 } 242 /* Skip the signature and omit the EOL/NUL byte. */ 243 slen = eol - (cmdline + strlen(CMDLINE_SIGNATURE)); 244 /* 245 * Let's limit the size of the property, just in case 246 * we find the signature by accident. The Linux kernel 247 * limits to 4096 characters at most (in fact 2048 for 248 * arm64), so that sounds like a reasonable number. 249 */ 250 if (slen > 4095) { 251 slen = 4095; 252 } 253 254 err = fdt_setprop(fdt, chosen, "bootargs", 255 cmdline + strlen(CMDLINE_SIGNATURE), slen); 256 if (err != 0) { 257 return err; 258 } 259 260 return fdt_appendprop(fdt, chosen, "bootargs", &nul, 1); 261 } 262 263 static void fpga_prepare_dtb(void) 264 { 265 void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE; 266 const char *cmdline = (void *)(uintptr_t)FPGA_PRELOADED_CMD_LINE; 267 int err; 268 269 err = fdt_open_into(fdt, fdt, FPGA_MAX_DTB_SIZE); 270 if (err < 0) { 271 ERROR("cannot open devicetree at %p: %d\n", fdt, err); 272 panic(); 273 } 274 275 /* Reserve memory used by Trusted Firmware. */ 276 if (fdt_add_reserved_memory(fdt, "tf-a@80000000", BL31_BASE, 277 BL31_LIMIT - BL31_BASE)) { 278 WARN("Failed to add reserved memory node to DT\n"); 279 } 280 281 /* Check for the command line signature. */ 282 if (!strncmp(cmdline, CMDLINE_SIGNATURE, strlen(CMDLINE_SIGNATURE))) { 283 err = fpga_dtb_set_commandline(fdt, cmdline); 284 if (err == 0) { 285 INFO("using command line at 0x%x\n", 286 FPGA_PRELOADED_CMD_LINE); 287 } else { 288 ERROR("failed to put command line into DTB: %d\n", err); 289 } 290 } 291 292 if (err < 0) { 293 ERROR("Error %d extending Device Tree\n", err); 294 panic(); 295 } 296 297 err = fdt_add_cpus_node(fdt, FPGA_MAX_PE_PER_CPU, 298 FPGA_MAX_CPUS_PER_CLUSTER, 299 FPGA_MAX_CLUSTER_COUNT); 300 301 if (err == -EEXIST) { 302 WARN("Not overwriting already existing /cpus node in DTB\n"); 303 } else { 304 if (err < 0) { 305 ERROR("Error %d creating the /cpus DT node\n", err); 306 panic(); 307 } else { 308 unsigned int nr_cores = fpga_get_nr_gic_cores(); 309 310 INFO("Adjusting GICR DT region to cover %u cores\n", 311 nr_cores); 312 err = fdt_adjust_gic_redist(fdt, nr_cores, 313 fpga_get_redist_base(), 314 fpga_get_redist_size()); 315 if (err < 0) { 316 ERROR("Error %d fixing up GIC DT node\n", err); 317 } 318 } 319 } 320 321 /* Check whether we support the SPE PMU. Remove the DT node if not. */ 322 if (!spe_supported()) { 323 int node = fdt_node_offset_by_compatible(fdt, 0, 324 "arm,statistical-profiling-extension-v1"); 325 326 if (node >= 0) { 327 fdt_del_node(fdt, node); 328 } 329 } 330 331 /* Check whether we have an ITS. Remove the DT node if not. */ 332 if (!fpga_has_its()) { 333 int node = fdt_node_offset_by_compatible(fdt, 0, 334 "arm,gic-v3-its"); 335 336 if (node >= 0) { 337 fdt_del_node(fdt, node); 338 } 339 } 340 341 err = fdt_pack(fdt); 342 if (err < 0) { 343 ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, err); 344 } 345 346 clean_dcache_range((uintptr_t)fdt, fdt_blob_size(fdt)); 347 } 348 349 void bl31_plat_runtime_setup(void) 350 { 351 fpga_prepare_dtb(); 352 } 353 354 void bl31_plat_enable_mmu(uint32_t flags) 355 { 356 /* TODO: determine if MMU needs to be enabled */ 357 } 358