feat(intel): allow to access all register addresses if DEBUG=1

Allow to access all register addresses from SMC call if compile the code
with DEBUG=1 for debugging purpose.

Signed-off-by: Siew Chin

feat(intel): allow to access all register addresses if DEBUG=1

Allow to access all register addresses from SMC call if compile the code
with DEBUG=1 for debugging purpose.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idd31827fb71307efbdbcceeaa05f6cb072842e10

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fix(intel): modify how configuration type is handled

This patch creates macros to handle different configuration
types. These changes will help in adding new configuration
types in the future.

Sign

fix(intel): modify how configuration type is handled

This patch creates macros to handle different configuration
types. These changes will help in adding new configuration
types in the future.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I5826a8e5942228a9ed376212f0df43b1605c0199

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feat(intel): support SiP SVC version

This command supports to return SiP SVC major and minor version.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.li

feat(intel): support SiP SVC version

This command supports to return SiP SVC major and minor version.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8bf678b8de0278aeaae748f24bdd05f8c9f9b47

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feat(intel): enable firewall for OCRAM in BL31

Set OCRAM as secure region and required privileged access in BL31 to
prevent software running in normal world (non-secure) accessing memory
region in O

feat(intel): enable firewall for OCRAM in BL31

Set OCRAM as secure region and required privileged access in BL31 to
prevent software running in normal world (non-secure) accessing memory
region in OCRAM which may contain sensitive information (e.g. FSBL,
handoff data)

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib6b24efd69f49cd3f9aa4ef2ea9f1af5ce582bd6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): create source file for firewall configuration

Move codes that previously were part of system_manager driver into
firewall driver which are more appropriate based on their functionalitie

feat(intel): create source file for firewall configuration

Move codes that previously were part of system_manager driver into
firewall driver which are more appropriate based on their functionalities.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I35e9d792f35ee7491c2f306781417a0c8faae3fd
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): refactor NOC header

Refactor NOC header to be shareable across both Stratix 10 and Agilex
platforms. This patch also removes redundant NOC declarations in system
manager header file.

Si

fix(intel): refactor NOC header

Refactor NOC header to be shareable across both Stratix 10 and Agilex
platforms. This patch also removes redundant NOC declarations in system
manager header file.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6348b67a8b54c2ad19327d6b8c25ae37d25e4b4a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(plat/mediatek/build_helpers): introduce mtk makefile

In order to modularize software libraries and platform drivers,
we create makefile helpers to treat a folder as a basic compile
unit.

Each

feat(plat/mediatek/build_helpers): introduce mtk makefile

In order to modularize software libraries and platform drivers,
we create makefile helpers to treat a folder as a basic compile
unit.

Each module has a build rule (rules.mk) to describe driver and software
library source codes to be built in.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: Ib2113b259dc97937b7295b265509025b43b14077

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build(makefile): add extra makefile variable for extension

Introduce EXTRA_LINKERFILE for GCC linker options. GCC linker
can realize multiple linker scripts, and vendors can extend ro or
text sectio

build(makefile): add extra makefile variable for extension

Introduce EXTRA_LINKERFILE for GCC linker options. GCC linker
can realize multiple linker scripts, and vendors can extend ro or
text sections by inserting sections among the original sections
specified by blx.ld.S.

Vendors can assign compiled object files by assigning MODULE_OBJS
with their own built path.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I1bd2e0383a52204723816131da4b7948def4c4e9

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docs(fvp): update loading addresses of HW_CONFIG

As per change [1], now HW_CONFIG gets loaded in secure and
non-secure memory. Hence updated the documentation to show
secure and non-secure load regi

docs(fvp): update loading addresses of HW_CONFIG

As per change [1], now HW_CONFIG gets loaded in secure and
non-secure memory. Hence updated the documentation to show
secure and non-secure load region of HW_CONFIG in FVP Arm
platform.

Additionally, added a note on how FW_CONFIG address gets
passed from BL2 to BL31/SP_MIN.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14620

Change-Id: I37e02ff4f433c87bccbe67c7df5ecde3017668b9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(fconf): update device tree binding for FCONF

Added a description for the newly introduced 'ns-load-address' property
in the dtb-registry node of FCONF.

Change-Id: Ief8e8a55a6363fd42b23491d000b

docs(fconf): update device tree binding for FCONF

Added a description for the newly introduced 'ns-load-address' property
in the dtb-registry node of FCONF.

Change-Id: Ief8e8a55a6363fd42b23491d000b097b0c48453b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(fvp): update HW_CONFIG DT loading mechanism

Currently, HW-config is loaded into non-secure memory, which mean
a malicious NS-agent could tamper with it. Ideally, this shouldn't
be an issue sinc

feat(fvp): update HW_CONFIG DT loading mechanism

Currently, HW-config is loaded into non-secure memory, which mean
a malicious NS-agent could tamper with it. Ideally, this shouldn't
be an issue since no software runs in non-secure world at this time
(non-secure world has not been started yet).

It does not provide a guarantee though since malicious external
NS-agents can take control of this memory region for update/corruption
after BL2 loads it and before BL31/BL32/SP_MIN consumes it. The threat
is mapped to Threat ID#3 (Bypass authentication scenario) in threat
model [1].

Hence modified the code as below -
1. BL2 loads the HW_CONFIG into secure memory
2. BL2 makes a copy of the HW_CONFIG in the non-secure memory at an
address provided by the newly added property(ns-load-address) in
the 'hw-config' node of the FW_CONFIG
3. SP_MIN receives the FW_CONFIG address from BL2 via arg1 so that
it can retrieve details (address and size) of HW_CONFIG from
FW_CONFIG
4. A secure and non-secure HW_CONFIG address will eventually be used
by BL31/SP_MIN/BL32 and BL33 components respectively
5. BL31/SP_MIN dynamically maps the Secure HW_CONFIG region and reads
information from it to local variables (structures) and then
unmaps it
6. Reduce HW_CONFIG maximum size from 16MB to 1MB; it appears
sufficient, and it will also create a free space for any future
components to be added to memory

[1]: https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/threat_model.html

Change-Id: I1d431f3e640ded60616604b1c33aa638b9a1e55e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(ti): allow build config of low power mode support

Not all K3 platforms support low power mode, so to allow these
features to be included for platforms that do in build and
therefore reported in

feat(ti): allow build config of low power mode support

Not all K3 platforms support low power mode, so to allow these
features to be included for platforms that do in build and
therefore reported in the PSCI caps, define K3_PM_SYSTEM_SUSPEND
flag that can be set during build that will cause appropriate
space and functionality to be included in build for system
suspend support.

Change-Id: I821fbbd5232d91de6c40f63254b855e285d9b3e8
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Ge

feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): add PSCI handlers for system suspend

Add necessary K3 PSCI handlers to enable system suspend to be reported
in the PSCI capabilities when asked during OS boot.

Additionally, have the hand

feat(ti): add PSCI handlers for system suspend

Add necessary K3 PSCI handlers to enable system suspend to be reported
in the PSCI capabilities when asked during OS boot.

Additionally, have the handlers provide information that all domains
should be off and also have the power domain suspend handler invoke the
TISCI_MSG_ENTER_SLEEP message to enter system suspend.

Change-Id: I351a16167770e9909e8ca525ee0d74fa93331194
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): add gic save and restore calls

Add functions to save and restore GICv3 redist and dist contexts during
low power mode and then call these during the suspend entry and finish
psci handlers.

feat(ti): add gic save and restore calls

Add functions to save and restore GICv3 redist and dist contexts during
low power mode and then call these during the suspend entry and finish
psci handlers.

Change-Id: I26c2c0f3b7fc925de3b349499fa42d2405441577
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): add enter sleep method

This TISCI API must be used to trigger entry into system suspend, and
this is done through the use of TI_SCI_MSG_ENTER_SLEEP. Introduce a
method to send this message

feat(ti): add enter sleep method

This TISCI API must be used to trigger entry into system suspend, and
this is done through the use of TI_SCI_MSG_ENTER_SLEEP. Introduce a
method to send this message.

Change-Id: Id7af5fb2a34623ad69e76764f389ff4d8d259fba
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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Merge "docs(zynqmp): update the make command" into integration

Merge changes Ibe6fd206,Icdca3de6,I72016620,I57a2787c into integration

* changes:
fix(versal): fix coverity scan warnings
feat(versal): get version for ATF related EEMI APIs
feat(versal): enha

Merge changes Ibe6fd206,Icdca3de6,I72016620,I57a2787c into integration

* changes:
fix(versal): fix coverity scan warnings
feat(versal): get version for ATF related EEMI APIs
feat(versal): enhance PM_IOCTL EEMI API to support additional arg
feat(versal): add common interfaces to handle EEMI commands

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Merge "refactor(twed): improve TWED enablement in EL-3" into integration

Merge changes from topic "st_clk_fix" into integration

* changes:
fix(st-clock): correct stm32_clk_parse_fdt_by_name
fix(st-clock): check _clk_stm32_get_parent return

docs(zynqmp): update the make command

Update the make command with the RESET_TO_BL31=1 addition.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I46cc81abb5397737

docs(zynqmp): update the make command

Update the make command with the RESET_TO_BL31=1 addition.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I46cc81abb539773706348464b3061d20d94522e9

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fix(versal): fix coverity scan warnings

- Fix memory overrun issue
- include header file to fix Unknown macro warning

Change-Id: Ibe6fd206f44fbc22de746d255ff17c2b2325cd7b
Signed-off-by: Tanmay Shah

fix(versal): fix coverity scan warnings

- Fix memory overrun issue
- include header file to fix Unknown macro warning

Change-Id: Ibe6fd206f44fbc22de746d255ff17c2b2325cd7b
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>

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feat(versal): get version for ATF related EEMI APIs

The patch does below things.

1. As per current implementation, when Linux send a request to ATF to
get the version of APIs which are implemented

feat(versal): get version for ATF related EEMI APIs

The patch does below things.

1. As per current implementation, when Linux send a request to ATF to
get the version of APIs which are implemented in ATF then ATF wasn't
returning any version because there is a check for LIBPM module id.
The ATF is used to return version for the APIs which are implemented
in the firmware only.

Hence moved this switch-case before checking module id to get ATF
version.

Also, no need to pass Linux request to the firmware for the APIs
which are implemented in ATF instead return success after updating
version.

2. As per current implementation, higher 16-bit is used for ATF
version and lower 16-bit is used for firmware version. Now, removed
16-bit shift operation and send complete word i.e. 32-bit to Linux
user as there is no user who checks ATF version.

3. Add bit mask support in the feature check PM EEMI API for QUERY and
IOCTL ids.

Change-Id: Icdca3de6659f3b673b81a423ed79a3c20b678768
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>

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feat(versal): enhance PM_IOCTL EEMI API to support additional arg

Currently, SMC handler is limited to parsing 5 arguments (1 API ID + 4
32-bit command args). Extend this handling to support one mor

feat(versal): enhance PM_IOCTL EEMI API to support additional arg

Currently, SMC handler is limited to parsing 5 arguments (1 API ID + 4
32-bit command args). Extend this handling to support one more 32-bit
command argument which is necessary to support new IOCTL IDs for
secure read/write interface.

Note that, this change is completely transparent and does not affect
existing functionality of any of the EEMI APIs.

Change-Id: I72016620eeeaf598f14853512120bfb30bb9a3e9
Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>

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feat(versal): add common interfaces to handle EEMI commands

This change adds common interfaces to handle commands from firmware driver
to power management controller. It removes big chunk of source

feat(versal): add common interfaces to handle EEMI commands

This change adds common interfaces to handle commands from firmware driver
to power management controller. It removes big chunk of source line of code
that was handling each command separately and doing same repetitive work.

EEMI - Embedded Energy Management Interface is Xilinx proprietary
protocol to allow communication between power management controller
and different processing clusters.

As of now, Each EEMI command has its own implementation in TF-A.
This is redundant. Essentially most EEMI command implementation
in TF-A does same work. It prepares payload received from kernel, sends
payload to firmware, receives response from firmware and send response
back to kernel.

The same functionality can be achieved if common interface is used among
multiple EEMI commands. This change divides platform management related
SMCCC requests into 4 categories.

1) EEMI commands required for backward compatibility.

Some EEMI commands are still required for backward compatibility
until removed completely or its use is changed to accommodate
common interface

2) EEMI commands that require for PSCI interface and accessed from debugfs

For example EEMI calls related to CPU suspend/resume

3) TF-A specific requests

Functionality such as getting TF-A version and getting callback
data for platform management is handled by this interface

4) Common interface for rest of EEMI commands

This handlers performs payload and firmware response transaction job for
rest of EEMI commands. Also it parses module ID from SMC payload and inserts
in IPI request. If not module ID is found, then default is LIBPM_MODULE_ID.
This helps in making common path in TF-A for all the modules in PLM firmware

Change-Id: I57a2787c7fff9f2e1d1f9003b3daab092632d57e
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>

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