feat(mt8188): initialize GIC

Initialize GIC for mt8188.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5acf77d654f1bbce32e9fbb3f3567600b7db10ed

feat(mt8188): initialize systimer

Add systimer to support timer function.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ibe6b96a162caa8804bebb7f

feat(mt8188): initialize systimer

Add systimer to support timer function.

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ibe6b96a162caa8804bebb7ff7de326ebcb2a6daa

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feat(mt8188): initialize platform for MediaTek MT8188

- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mt

feat(mt8188): initialize platform for MediaTek MT8188

- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mtk_pm.c in lib/pm

TEST=build pass
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5f8617c42ffba2c9d3a16f3980cb75fda5624031

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refator(mediatek): remove unused files

We do not use oem_svc.[c|h], so remove them.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0afb64d997cf4e23063f4fa2226e8d2649d22574

refator(mediatek): move drivers folder in common to plat/mediatek

We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.

Signed-off-by: Bo-Ch

refator(mediatek): move drivers folder in common to plat/mediatek

We plan to put some soc related drivers in common/drivers. To reduce
confision, we move them to plat/mediatek.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6b344e660f40a23b15151aab073d3045b28f52aa

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Merge "fix(bl31): allow use of EHF with S-EL2 SPMC" into integration

fix(n1sdp): mapping Run-time UART to IOFPGA UART0

Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UA

fix(n1sdp): mapping Run-time UART to IOFPGA UART0

Currently the Run-time UART is mapped to AP UART1 which is internally
routed to MCP UART1, so unsharing it from AP UART1 and mapping it to
IOFPGA UART0 for exclusiveness among the usage of the UARTs.

Signed-off-by: Himanshu Sharma <Himanshu.Sharma@arm.com>
Change-Id: I366740a971a880decf0d373e9055e7ebda5df53a

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fix(n1sdp): add numa node id for pcie controllers

If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-

fix(n1sdp): add numa node id for pcie controllers

If not mentioned explicitly, numa-node-id for pcie_ctlr
is assigned as unknown. With this patch pcie_ctlr and
ccix_pcie_ctlr are assigned numa-node-id=0 and
pcie_secondary_ctlr is assigned numa-node-id=1.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I533abdd6ea162df7b15ee04cbfc48ba7a544b91a

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fix(n1sdp): replace non-inclusive terms from dts file

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I6aa3b6dcf7c2fea18ea2d4f44a2293123ff34bdf

Merge "refactor(cpu): update IP names of Makalu CPU lib" into integration

refactor(cpu): update IP names of Makalu CPU lib

* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.

Signed-off-by: Rupin

refactor(cpu): update IP names of Makalu CPU lib

* ASM files are renamed to have public IP names in their filename.
* updated other files to include ASM filename changes.

Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: Ie899c512b11fd7c4312e3a808bb6b9d2376cdb8c

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Merge "chore: use tabs for indentation" into integration

feat(mediatek): support coreboot BL31 loading

The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.

Signed-off-by:

feat(mediatek): support coreboot BL31 loading

The ChromeOS project uses Coreboot as BL2 instead of MediaTek regular
bootloader, so we use COREBOOT flag to support Coreboot boot flow.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I45e95ea51e90158187452eba52fc58090d1c60a4

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fix(errata): workaround for Cortex-A510 erratum 2347730

Cortex-A510 erratum 2347730 is a Cat B erratum that affects
revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is
fixed in r1p2. The workarou

fix(errata): workaround for Cortex-A510 erratum 2347730

Cortex-A510 erratum 2347730 is a Cat B erratum that affects
revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is
fixed in r1p2. The workaround is to set CPUACTLR_EL1[17]
to 1, which will disable specific microarchitectural clock
gating behaviour.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest

Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I115386284c2d91bd61515142f971e2e72de43e68

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chore: use tabs for indentation

This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding

chore: use tabs for indentation

This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I7bd99a50a79499aca0d349e49a3e095e6c5d2f08

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feat(ti-k3): add support for J784S4 SoCs

The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration

feat(ti-k3): add support for J784S4 SoCs

The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration is introduced to support quad core clusters on the J784S4
SoC of the K3 family of devices.

See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Change-Id: I0ed1f14ab32a56ae06e3df3161ace4597d14a48d

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fix(bl31): allow use of EHF with S-EL2 SPMC

Currently, when SPMC at S-EL2 is used, we cannot use the RAS framework
to handle Group 0 interrupts. This is required on platforms where first
level of tr

fix(bl31): allow use of EHF with S-EL2 SPMC

Currently, when SPMC at S-EL2 is used, we cannot use the RAS framework
to handle Group 0 interrupts. This is required on platforms where first
level of triaging needs to occur at EL3, before forwarding RAS handling
to a secure partition running atop an SPMC (hafnium).
The RAS framework depends on EHF and EHF registers for Group 0
interrupts to be trapped to EL3 when execution is both in secure world
and normal world. However, an FF-A compliant SPMC requires secure
interrupts to be trapped by the SPMC when execution is in S-EL0/S-EL1.
Consequently, the SPMC (hafnium) is incompatible with EHF, since it is
not re-entrant, and a Group 0 interrupt trapped to EL3 when execution is
in secure world, cannot be forwarded to an SP running atop SPMC.
This patch changes EHF to only register for Group 0 interrupts to be
trapped to EL3 when execution is in normal world and also makes it a
valid routing model to do so, when EL3_EXCEPTION_HANDLING is set (when
enabling the RAS framework).

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I72d4cf4d8ecc549a832d1c36055fbe95866747fe

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Merge "docs(marvell): document UART image downloading" into integration

Merge changes from topics "mtk_cold_boot", "mtk_init_scheme", "smc_registration_use_case", "vendor_extend_pubsub_event" into integration

* changes:
feat(mediatek): implement generic platform port

Merge changes from topics "mtk_cold_boot", "mtk_init_scheme", "smc_registration_use_case", "vendor_extend_pubsub_event" into integration

* changes:
feat(mediatek): implement generic platform port
refactor(mediatek): smc registration services
feat(mediatek): introduce mtk init framework
refactor(mediatek): partition MTK SiP SMC ID
feat(mediatek): extend SiP vendor subscription events

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feat(mediatek): implement generic platform port

Implement mandatory platform port functions. Receive
boot arguments from bl2, populate bl33 and bl32 image
entry structs, call each MTK initcall level

feat(mediatek): implement generic platform port

Implement mandatory platform port functions. Receive
boot arguments from bl2, populate bl33 and bl32 image
entry structs, call each MTK initcall levels
in these mandatory platform port functions.
After bl31_main exit and handover to 2nd boot loader,
mtk bl33 issues SMC and traps to TF-A to execute boot_to_kernel
and then handover to Linux kernel.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8d5a3511668fc749c4c71edf1ac700002cb5a9c8

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refactor(mediatek): smc registration services

To modularize SMC handler, provide macro function in mtk_sip_svc.h.
Drivers register SMC name with value in mtk_sip_def.h, and bind the SMC
handler with

refactor(mediatek): smc registration services

To modularize SMC handler, provide macro function in mtk_sip_svc.h.
Drivers register SMC name with value in mtk_sip_def.h, and bind the SMC
handler with the SMC ID by calling DECLARE_SMC_HANDLER macro.

MTK_SIP_SMC_FROM_BL33_TABLE expand the SMC table as switch-case table
statically. DECLARE_SMC_HANDLER wrap SMC handlers with a structure and
put in a section.
During cold boot initialization, in MTK_EARLY_PLAT_INIT level parse the
section to assign each handler with an index. Each SMC request can be
identified with switch-case and take the index to call into
corresponding SMC handler.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I03da212c786de0ec0ea646ba906065ecfcd82571

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feat(mediatek): introduce mtk init framework

Provide six initcall levels for drivers/modules initialize HW
controllers or runtime arguments during cold boot.

The initcall level cold boot execution

feat(mediatek): introduce mtk init framework

Provide six initcall levels for drivers/modules initialize HW
controllers or runtime arguments during cold boot.

The initcall level cold boot execution order:

-MTK_EARLY_PLAT_INIT
Call before MMU enabled.

-MTK_ARCH_INIT
MMU Enabled, arch related init(GiC init, interrupt type registration).

-MTK_PLAT_SETUP_0_INIT
MTK driver init level 0.

-MTK_PLAT_SETUP_1_INIT
MTK driver init level 1.

-MTK_PLAT_RUNTIME_INIT
MTK driver init. After this initcall, TF-A handovers to MTK 2nd
bootloader.

-MTK_PLAT_BL33_DEFER_INIT
MTK 2nd bootloader traps to TF-A before handover to rich OS.
This initcall executed in the trap handler(boot_to_kernel).

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: Icd7fe95372441db73c975ccb6ce77a6c529df1cc

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refactor(mediatek): partition MTK SiP SMC ID

Manage MTK SiP SMC ID with macros for 32/64 bit and
function declaration code generation.
Partition SMC ID with different exception level sources.

Signe

refactor(mediatek): partition MTK SiP SMC ID

Manage MTK SiP SMC ID with macros for 32/64 bit and
function declaration code generation.
Partition SMC ID with different exception level sources.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I8966cd94f0d825e7ebae08833d2bd9fceedfd45e

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feat(mediatek): extend SiP vendor subscription events

Leverage pubsub event framework to customize vendor's
event for better software modularization instead of adding
call entries in abstraction lay

feat(mediatek): extend SiP vendor subscription events

Leverage pubsub event framework to customize vendor's
event for better software modularization instead of adding
call entries in abstraction layer for customized platform function
with wrap-up define.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I48be2303c45f759776fa2baa1c21130c1a8f0fa3

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feat(stm32mp1): allow to override MTD base offset

Add an external parameter STM32MP_FORCE_MTD_START_OFFSET that allows to
override the default FIP offset used to read the first programmed image.
It

feat(stm32mp1): allow to override MTD base offset

Add an external parameter STM32MP_FORCE_MTD_START_OFFSET that allows to
override the default FIP offset used to read the first programmed image.
It can be used for NOR, RAW_NAND or SPI_NAND boot device.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ibe664aae0e5ee90dd6629e544c9e034d751fffed

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