1/* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <services/sdei_flags.h> 9 10#define LEVEL 0 11#define EDGE 2 12#define SDEI_NORMAL 0x70 13#define HIGHEST_SEC 0 14 15/ { 16 model = "FVP Base"; 17 compatible = "arm,fvp-base", "arm,vexpress"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22#if (ENABLE_RME == 1) 23 chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";}; 24#else 25 chosen {}; 26#endif 27 28 aliases { 29 serial0 = &v2m_serial0; 30 serial1 = &v2m_serial1; 31 serial2 = &v2m_serial2; 32 serial3 = &v2m_serial3; 33 }; 34 35 psci { 36 compatible = "arm,psci-1.0", "arm,psci-0.2"; 37 method = "smc"; 38 max-pwr-lvl = <2>; 39 }; 40 41#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF 42 firmware { 43#if SDEI_IN_FCONF 44 sdei { 45 compatible = "arm,sdei-1.0"; 46 method = "smc"; 47 private_event_count = <3>; 48 shared_event_count = <3>; 49 /* 50 * Each event descriptor has typically 3 fields: 51 * 1. Event number 52 * 2. Interrupt number the event is bound to or 53 * if event is dynamic, specified as SDEI_DYN_IRQ 54 * 3. Bit map of event flags 55 */ 56 private_events = <1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 57 <1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 58 <1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 59 shared_events = <2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 60 <2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>, 61 <2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>; 62 }; 63#endif /* SDEI_IN_FCONF */ 64 65#if SEC_INT_DESC_IN_FCONF 66 sec_interrupts { 67 compatible = "arm,secure_interrupt_desc"; 68 /* Number of G0 and G1 secure interrupts defined by the platform */ 69 g0_intr_cnt = <2>; 70 g1s_intr_cnt = <9>; 71 /* 72 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 73 * terminology. Each interrupt property descriptor has 3 fields: 74 * 1. Interrupt number 75 * 2. Interrupt priority 76 * 3. Type of interrupt (Edge or Level configured) 77 */ 78 g0_intr_desc = < 8 SDEI_NORMAL EDGE>, 79 <14 HIGHEST_SEC EDGE>; 80 81 g1s_intr_desc = < 9 HIGHEST_SEC EDGE>, 82 <10 HIGHEST_SEC EDGE>, 83 <11 HIGHEST_SEC EDGE>, 84 <12 HIGHEST_SEC EDGE>, 85 <13 HIGHEST_SEC EDGE>, 86 <15 HIGHEST_SEC EDGE>, 87 <29 HIGHEST_SEC LEVEL>, 88 <56 HIGHEST_SEC LEVEL>, 89 <57 HIGHEST_SEC LEVEL>; 90 }; 91#endif /* SEC_INT_DESC_IN_FCONF */ 92 }; 93#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */ 94 95 cpus { 96 #address-cells = <2>; 97 #size-cells = <0>; 98 99 CPU_MAP 100 101 idle-states { 102 entry-method = "arm,psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 local-timer-stop; 107 arm,psci-suspend-param = <0x0010000>; 108 entry-latency-us = <40>; 109 exit-latency-us = <100>; 110 min-residency-us = <150>; 111 }; 112 113 CLUSTER_SLEEP_0: cluster-sleep-0 { 114 compatible = "arm,idle-state"; 115 local-timer-stop; 116 arm,psci-suspend-param = <0x1010000>; 117 entry-latency-us = <500>; 118 exit-latency-us = <1000>; 119 min-residency-us = <2500>; 120 }; 121 }; 122 123 CPUS 124 125 L2_0: l2-cache0 { 126 compatible = "cache"; 127 }; 128 }; 129 130 memory@80000000 { 131 device_type = "memory"; 132#if (ENABLE_RME == 1) 133 reg = <0x00000000 0x80000000 0 0x7C000000>, 134 <0x00000008 0x80000000 0 0x80000000>; 135#else 136 reg = <0x00000000 0x80000000 0 0x7F000000>, 137 <0x00000008 0x80000000 0 0x80000000>; 138#endif 139 }; 140 141 timer { 142 compatible = "arm,armv8-timer"; 143 interrupts = <GIC_PPI 13 144 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 145 <GIC_PPI 14 146 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 147 <GIC_PPI 11 148 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 10 150 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 151 clock-frequency = <100000000>; 152 }; 153 154 timer@2a810000 { 155 compatible = "arm,armv7-timer-mem"; 156 reg = <0x0 0x2a810000 0x0 0x10000>; 157 clock-frequency = <100000000>; 158 #address-cells = <2>; 159 #size-cells = <2>; 160 ranges; 161 frame@2a830000 { 162 frame-number = <1>; 163 interrupts = <0 26 4>; 164 reg = <0x0 0x2a830000 0x0 0x10000>; 165 }; 166 }; 167 168 pmu { 169 compatible = "arm,armv8-pmuv3"; 170 interrupts = <0 60 4>, 171 <0 61 4>, 172 <0 62 4>, 173 <0 63 4>; 174 }; 175 176 smb@0 { 177 compatible = "simple-bus"; 178 179 #address-cells = <2>; 180 #size-cells = <1>; 181 ranges = <0 0 0 0x08000000 0x04000000>, 182 <1 0 0 0x14000000 0x04000000>, 183 <2 0 0 0x18000000 0x04000000>, 184 <3 0 0 0x1c000000 0x04000000>, 185 <4 0 0 0x0c000000 0x04000000>, 186 <5 0 0 0x10000000 0x04000000>; 187 188 #interrupt-cells = <1>; 189 interrupt-map-mask = <0 0 63>; 190 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 191 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 192 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 193 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 194 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 195 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 196 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 197 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 198 <0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 199 <0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 200 <0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 201 <0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 202 <0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 203 <0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 204 <0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 205 <0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 206 <0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 207 <0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 208 <0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 209 <0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 210 <0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 211 <0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 212 <0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 213 <0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 214 <0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 215 <0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 216 <0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 217 <0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 218 <0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 219 <0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 220 <0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 221 <0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 222 <0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 223 <0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 224 <0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 225 <0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 226 <0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 227 <0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 228 <0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 229 <0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 230 <0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 231 <0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 232 <0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 233 234 #include "rtsm_ve-motherboard.dtsi" 235 }; 236 237 panels { 238 panel { 239 compatible = "panel"; 240 mode = "XVGA"; 241 refresh = <60>; 242 xres = <1024>; 243 yres = <768>; 244 pixclock = <15748>; 245 left_margin = <152>; 246 right_margin = <48>; 247 upper_margin = <23>; 248 lower_margin = <3>; 249 hsync_len = <104>; 250 vsync_len = <4>; 251 sync = <0>; 252 vmode = "FB_VMODE_NONINTERLACED"; 253 tim2 = "TIM2_BCD", "TIM2_IPC"; 254 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 255 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 256 bpp = <16>; 257 }; 258 }; 259}; 260