1/* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/* Configuration: max 4 clusters with up to 4 CPUs */ 8 9/dts-v1/; 10 11#define AFF 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include "fvp-defs.dtsi" 15 16/memreserve/ 0x80000000 0x00010000; 17 18/ { 19}; 20 21/ { 22 model = "FVP Base"; 23 compatible = "arm,vfp-base", "arm,vexpress"; 24 interrupt-parent = <&gic>; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 chosen { }; 29 30 aliases { 31 serial0 = &v2m_serial0; 32 serial1 = &v2m_serial1; 33 serial2 = &v2m_serial2; 34 serial3 = &v2m_serial3; 35 }; 36 37 psci { 38 compatible = "arm,psci-1.0", "arm,psci-0.2"; 39 method = "smc"; 40 max-pwr-lvl = <2>; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU_MAP 48 49 idle-states { 50 entry-method = "arm,psci"; 51 52 CPU_SLEEP_0: cpu-sleep-0 { 53 compatible = "arm,idle-state"; 54 local-timer-stop; 55 arm,psci-suspend-param = <0x0010000>; 56 entry-latency-us = <40>; 57 exit-latency-us = <100>; 58 min-residency-us = <150>; 59 }; 60 61 CLUSTER_SLEEP_0: cluster-sleep-0 { 62 compatible = "arm,idle-state"; 63 local-timer-stop; 64 arm,psci-suspend-param = <0x1010000>; 65 entry-latency-us = <500>; 66 exit-latency-us = <1000>; 67 min-residency-us = <2500>; 68 }; 69 }; 70 71 CPUS 72 73 L2_0: l2-cache0 { 74 compatible = "cache"; 75 }; 76 }; 77 78 memory@80000000 { 79 device_type = "memory"; 80 reg = <0x00000000 0x80000000 0 0x7F000000>, 81 <0x00000008 0x80000000 0 0x80000000>; 82 }; 83 84 gic: interrupt-controller@2f000000 { 85 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 86 #interrupt-cells = <3>; 87 #address-cells = <0>; 88 interrupt-controller; 89 reg = <0x0 0x2f000000 0 0x10000>, 90 <0x0 0x2c000000 0 0x2000>, 91 <0x0 0x2c010000 0 0x2000>, 92 <0x0 0x2c02F000 0 0x2000>; 93 interrupts = <1 9 0xf04>; 94 }; 95 96 timer { 97 compatible = "arm,armv8-timer"; 98 interrupts = <GIC_PPI 13 99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 103 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 105 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 106 clock-frequency = <100000000>; 107 }; 108 109 timer@2a810000 { 110 compatible = "arm,armv7-timer-mem"; 111 reg = <0x0 0x2a810000 0x0 0x10000>; 112 clock-frequency = <100000000>; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 frame@2a830000 { 117 frame-number = <1>; 118 interrupts = <0 26 4>; 119 reg = <0x0 0x2a830000 0x0 0x10000>; 120 }; 121 }; 122 123 pmu { 124 compatible = "arm,armv8-pmuv3"; 125 interrupts = <0 60 4>, 126 <0 61 4>, 127 <0 62 4>, 128 <0 63 4>; 129 }; 130 131 smb { 132 compatible = "simple-bus"; 133 134 #address-cells = <2>; 135 #size-cells = <1>; 136 ranges = <0 0 0 0x08000000 0x04000000>, 137 <1 0 0 0x14000000 0x04000000>, 138 <2 0 0 0x18000000 0x04000000>, 139 <3 0 0 0x1c000000 0x04000000>, 140 <4 0 0 0x0c000000 0x04000000>, 141 <5 0 0 0x10000000 0x04000000>; 142 143 #include "rtsm_ve-motherboard.dtsi" 144 }; 145 146 panels { 147 panel@0 { 148 compatible = "panel"; 149 mode = "XVGA"; 150 refresh = <60>; 151 xres = <1024>; 152 yres = <768>; 153 pixclock = <15748>; 154 left_margin = <152>; 155 right_margin = <48>; 156 upper_margin = <23>; 157 lower_margin = <3>; 158 hsync_len = <104>; 159 vsync_len = <4>; 160 sync = <0>; 161 vmode = "FB_VMODE_NONINTERLACED"; 162 tim2 = "TIM2_BCD", "TIM2_IPC"; 163 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; 164 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; 165 bpp = <16>; 166 }; 167 }; 168}; 169