Merge "fix(imx8m): update poweroff related SNVS_LPCR bits only" into integration

fix(cpus): workaround for Cortex-A710 erratum 2291219

Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CP

fix(cpus): workaround for Cortex-A710 erratum 2291219

Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691

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fix(cpus): workaround for Cortex-X3 erratum 2313909

Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions
r0p0 and r1p0, and is fixed in r1p1. The workaround is to set
CPUACTLR2_EL1

fix(cpus): workaround for Cortex-X3 erratum 2313909

Cortex-X3 erratum 2313909 is a Cat B erratum that applies to revisions
r0p0 and r1p0, and is fixed in r1p1. The workaround is to set
CPUACTLR2_EL1[36] to 1 before the power down sequence that sets
CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents
the deadlock. TF-A never clears this bit even if it wakes up from the
wfi in the sequence since it is not expected to do anything but retry to
power down after and the bit is cleared on reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5935b4bcd1e6712477c0d6eab2acc96d7964a35d

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fix(cpus): workaround for Neoverse-N2 erratum 2326639

Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to

fix(cpus): workaround for Neoverse-N2 erratum 2326639

Neoverse-N2 erratum 2326639 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[36] to
1 before the power down sequence that sets CORE_PWRDN_EN. This allows
the cpu to retry the power down and prevents the deadlock. TF-A never
clears this bit even if it wakes up from the wfi in the sequence since
it is not expected to do anything but retry to power down after and the
bit is cleared on reset.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest/

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9a325c5b9b498798e5efd5c79a4a6d5bed97c619

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fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour

Platforms which implement pwr_domain_pwr_down_wfi differ substantially
in behaviour. However, different cpus require similar sequences t

fix(rpi3): tighten platform pwr_domain_pwr_down_wfi behaviour

Platforms which implement pwr_domain_pwr_down_wfi differ substantially
in behaviour. However, different cpus require similar sequences to power
down. This patch tightens the behaviour of these platforms to end on a
wfi loop after performing platform power down. This is required so that
platforms behave more consistently on power down, in cases where the wfi
can fall through.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie29bd3a5e654780bacb4e07a6d123ac6d2467c1f

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docs(spm): add threat model for el3 spmc

Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Cha

docs(spm): add threat model for el3 spmc

Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I7f4c9370b6eefe6d1a7d1afac27e8b3a7b476072

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docs(spm): add design documentation

Add documentation how to build EL3 SPMC,
briefly describes all FF-A interfaces,
SP boot flow, SP Manifest, Power Management,
Boot Info Protocol, Runtime model and

docs(spm): add design documentation

Add documentation how to build EL3 SPMC,
briefly describes all FF-A interfaces,
SP boot flow, SP Manifest, Power Management,
Boot Info Protocol, Runtime model and state
transition and Interrupt Handling.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I630df1d50a4621b344a09e462563eacc90109de4

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chore: rename Makalu ELP to Cortex-X3

The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.

Si

chore: rename Makalu ELP to Cortex-X3

The Cortex-X3 cpu port was developed before its public release when it
was known as Makalu ELP. Now that it's released we can use the official
product name.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iebb90cf2f77330ed848a3d61c5f6928942189c5a

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Merge "fix(security): optimisations for CVE-2022-23960" into integration

fix(security): optimisations for CVE-2022-23960

Optimised the loop workaround for Spectre_BHB mitigation:
1. use of speculation barrier for cores implementing SB instruction.
2. use str/ldr instead

fix(security): optimisations for CVE-2022-23960

Optimised the loop workaround for Spectre_BHB mitigation:
1. use of speculation barrier for cores implementing SB instruction.
2. use str/ldr instead of stp/ldp as the loop uses only X2 register.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8ac53ea1e42407ad8004c1d59c05f791011f195d

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fix(mediatek): switch console to runtime state before leaving BL31

We should switch console to runtime state. If we don't do this, the
state will keep boot state even we exit from BL31.

Signed-off-

fix(mediatek): switch console to runtime state before leaving BL31

We should switch console to runtime state. If we don't do this, the
state will keep boot state even we exit from BL31.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id2269ccf2fdc22e0fa088c3c0365836730172233

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Merge "fix(sme): add missing ISBs" into integration

fix(imx8m): update poweroff related SNVS_LPCR bits only

Function imx_system_off() writes SNVS_LPCR register to power off the SoC
without bit masking. This clears other bits like LPWUI_EN and breaks

fix(imx8m): update poweroff related SNVS_LPCR bits only

Function imx_system_off() writes SNVS_LPCR register to power off the SoC
without bit masking. This clears other bits like LPWUI_EN and breaks
the function of SoC wake-up using RTC alarm. Fix it by updating poweroff
related bits only.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Change-Id: If641af4dc1103c67e1a645c03bb36a5f56665aef

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Merge "fix(gicv3/multichip): fix overflow caused by left shift" into integration

Merge "fix(stm32mp13-fdts): correct PLL nodes name" into integration

fix(build): fix arch32 build issue for clang

Fixed the qemu 32 bit clang build fail caused because of
no march32 directives in TF_CFLAGS_aarch32 variable

march32_directive is initialized later in M

fix(build): fix arch32 build issue for clang

Fixed the qemu 32 bit clang build fail caused because of
no march32 directives in TF_CFLAGS_aarch32 variable

march32_directive is initialized later in Makefile and since clang build
uses Immediate set instead of Lazy set , TF_CFLAGS_aarch32 doesn't
have mcpu variable.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I09094a0912ee2d9d0e11f65135a352de8a135936

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feat(compiler-rt): update compiler-rt source files

Update the compiler-rt source files to the tip of the llvm-project [1].
To do this some new header files were pulled in from the freebsd-src
repo [

feat(compiler-rt): update compiler-rt source files

Update the compiler-rt source files to the tip of the llvm-project [1].
To do this some new header files were pulled in from the freebsd-src
repo [2].

[1] https://github.com/llvm/llvm-project/commit/fae258e
[2] https://github.com/freebsd/freebsd-src/commit/243a0eda

Change-Id: I1a012b1fe04e127d35e208923877c98c5d999d00
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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fix(deps): add missing aeabi_memcpy.S

Add missing aeabi_memcpy.S file from llvm compiler-rt library [1]. This
is required for Aarch32 builds with clang.

[1] https://github.com/llvm/llvm-project.git

fix(deps): add missing aeabi_memcpy.S

Add missing aeabi_memcpy.S file from llvm compiler-rt library [1]. This
is required for Aarch32 builds with clang.

[1] https://github.com/llvm/llvm-project.git

Change-Id: I7fd6ab1e81dd45d24afef49a3eb8fcdcbc5c082f
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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feat(zlib): update zlib source files

Upgrade the zlib source files to the ones present in the version 1.2.13
of zlib [1]. Since 1.2.11 the use of Arm crc32 instructions has been
introduced so update

feat(zlib): update zlib source files

Upgrade the zlib source files to the ones present in the version 1.2.13
of zlib [1]. Since 1.2.11 the use of Arm crc32 instructions has been
introduced so update the files to make use of this.

[1] https://github.com/madler/zlib/tree/v1.2.13

Change-Id: Ideef78c56f05ae7daec390d00dcaa8f66b18729e
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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docs(changelog): add zlib and compiler-rt scope

Change-Id: Id98ca7762fd17cb793b0ec9119d0b026195cf2c2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

feat(hikey960): increase secure workspace to 64MB

Common TEE use cases require 64 MB these days, and not just 16 MB.
This in turn requires more XLAT tables to be pre-allocated for BL31.

Change-Id:

feat(hikey960): increase secure workspace to 64MB

Common TEE use cases require 64 MB these days, and not just 16 MB.
This in turn requires more XLAT tables to be pre-allocated for BL31.

Change-Id: I85c4033da64785f3e3272b0e9a4da4bceb20fcc7
Signed-off-by: vallau01 <valentin.laurent@trustonic.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>

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feat(hikey960): upgrade to xlat_tables_v2

Allow 36-bit addresses.
Don't map BL32 memory into BL31 to save space

Change-Id: I033132354dc4b9876f4a384491097b9b5238e700
Signed-off-by: vallau01 <valenti

feat(hikey960): upgrade to xlat_tables_v2

Allow 36-bit addresses.
Don't map BL32 memory into BL31 to save space

Change-Id: I033132354dc4b9876f4a384491097b9b5238e700
Signed-off-by: vallau01 <valentin.laurent@trustonic.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>

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Merge "fix(rme): relax RME compiler requirements" into integration

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and

Merge changes from topic "imx8m-hab-support" into integration

* changes:
docs(imx8m): update for high assurance boot
feat(imx8m): add support for high assurance boot
feat(imx8mp): add hab and map required memory blocks
feat(imx8mn): add hab and map required memory blocks
feat(imx8mm): add hab and map required memory blocks

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style(linker_script): fix indentation

Use four spaces for indentation to maintain a consistent style. This
attempts to make the linker scripts more friendly for readers.

Signed-off-by: Jorge Tronco

style(linker_script): fix indentation

Use four spaces for indentation to maintain a consistent style. This
attempts to make the linker scripts more friendly for readers.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: Iaf26d3c8bd7053fd9605a64ebccdae0792a90b9e

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