Merge "feat(rss): add TC platform UUIDs for RSS images" into integration

fix(mpam): run-time checks for mpam save/restore routines

With "ENABLE_MPAM_FOR_LOWER_ELS" and "CTX_INCLUDE_EL2_REGS" build
options enabled, MPAM EL2 registers would be saved/restored as part of
con

fix(mpam): run-time checks for mpam save/restore routines

With "ENABLE_MPAM_FOR_LOWER_ELS" and "CTX_INCLUDE_EL2_REGS" build
options enabled, MPAM EL2 registers would be saved/restored as part of
context management. Context save/restore routines as of now would
proceed to access all of MPAM EL2 registers without any runtime checks.
MPAM specification states that MPAMHCR_EL2 should only be accessed if
MPAMIDR_EL1.HAS_HCR is "1". Likewise, MPAMIDR_EL1.VPMR_MAX has to be
probed to obtain the maximum supported MPAMVPM<x>_EL2 before accessing
corresponding MPAMVPM<x>_EL2 registers. Since runtime checks are not
being made, an exception would be raised if the platform under test
doesn't support one of the registers. On Neoverse reference design
platforms, an exception is being raised while MPAMVPM2_EL2 or above are
accessed. Neoverse reference design platforms support only registers
till MPAMVPM1_EL2 at this point.

To resolve this, add sufficient runtime checks in MPAM EL2 context
save/restore routines. As part of the new save/restore routines,
MPAMIDR_EL1.HAS_HCR and MPAMIDR_EL1.VPMR_MAX are probed for the right
set of registers to be saved and restored.

CC: Davidson Kumaresan <davidson.kumaresan@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I2e3affd23091023b287b2bd5057a4a549037b611

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feat(fiptool): handle FIP in a disk partition

When FIP is programmed in a disk partition, fiptool cannot be used
directly; this forces the user to temporarily copy the partition
to a file, apply fip

feat(fiptool): handle FIP in a disk partition

When FIP is programmed in a disk partition, fiptool cannot be used
directly; this forces the user to temporarily copy the partition
to a file, apply fiptool and copy back the file. This is caused by
fstat() that returns zero file size on a block special file, thus
making fiptool commands info, update, unpack and remove to exit.

For either Linux host or Linux target, recover the partition size
with ioctl() and use it as FIP file size. E.g.:
fiptool info /dev/disk/by-partlabel/fip-a
fiptool info /dev/mtdblock4

While there, rework two identical error log messages to provide
more details about the failure and update the date in copyright.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I7cab60e577422d94c24ba7e39458f58bcebc2336

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Merge changes from topic "srm/errata" into integration

* changes:
fix(cpus): workaround for Neoverse V1 errata 2779461
fix(cpus): workaround for Cortex-A78 erratum 2779479

Merge changes from topic "fix_sparse_warnings" into integration

* changes:
fix(libc): remove __putchar alias
fix(console): correct scopes for console symbols
fix(auth): use NULL instead of 0 f

Merge changes from topic "fix_sparse_warnings" into integration

* changes:
fix(libc): remove __putchar alias
fix(console): correct scopes for console symbols
fix(auth): use NULL instead of 0 for pointer check
fix(io): compare function pointers with NULL
fix(fdt-wrappers): use correct prototypes

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fix(build): allow warnings when using lld

After https://reviews.llvm.org/D118840, ld.lld reports
below section type mismatch warnings:

LD trusted-firmware-a/build/qemu/release/bl1/bl1.elf
ld

fix(build): allow warnings when using lld

After https://reviews.llvm.org/D118840, ld.lld reports
below section type mismatch warnings:

LD trusted-firmware-a/build/qemu/release/bl1/bl1.elf
ld.lld: error: section type mismatch for base_xlat_table
>>> trusted-firmware-a/build/qemu/release/bl1/xlat_tables_context.o:
(base_xlat_table): SHT_PROGBITS
>>> output section .bss: SHT_NOBITS

ld.lld: error: section type mismatch for xlat_table
>>> trusted-firmware-a/build/qemu/release/bl1/xlat_tables_context.o:
(xlat_table): SHT_PROGBITS
>>> output section xlat_table: SHT_NOBITS

So allow warnings to make build pass.

Change-Id: I70503ad03b3be7a18ffe29ef6f2127c3f4d540f1
Signed-off-by: Yabin Cui <yabinc@google.com>

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fix(cpus): workaround for Neoverse V1 errata 2779461

Neoverse V1 erratum 2779461 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open.

The workaround sets CPUACTLR3_EL1[47] bit

fix(cpus): workaround for Neoverse V1 errata 2779461

Neoverse V1 erratum 2779461 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open.

The workaround sets CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact
on performance.

SDEN documentation:https://developer.arm.com/documentation/SDEN1401781/latest

Change-Id: I367cda1779684638063d7292fda20ca6734e6f10
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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fix(cpus): workaround for Cortex-A78 erratum 2779479

Cortex-A78 erratum 2779479 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR3_EL

fix(cpus): workaround for Cortex-A78 erratum 2779479

Cortex-A78 erratum 2779479 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact
on performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Change-Id: I3779fd1eff3017c5961ffa101b357918070b3b36
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge changes from topic "feat_state_rework" into integration

* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): conv

Merge changes from topic "feat_state_rework" into integration

* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): convert FEAT_HCX to new scheme
feat(fvp): enable FEAT_FGT by default
refactor(context-mgmt): move FEAT_FGT save/restore code into C
refactor(amu): convert FEAT_AMUv1 to new scheme
refactor(cpufeat): decouple FGT feature detection and build flags
refactor(cpufeat): check FEAT_FGT in a new way
refactor(cpufeat): move helpers into .c file, rename FEAT_STATE_
feat(aarch64): make ID system register reads non-volatile

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Merge "fix(plat/css): fix invalid redistributor poweroff" into integration

fix(cpus): workaround for Cortex-A78C erratum 2772121

Cortex-A78C erratum 2772121 is a Cat B erratum that applies to
all revisions <=r0p2 and is still open. The workaround is to
insert a dsb before

fix(cpus): workaround for Cortex-A78C erratum 2772121

Cortex-A78C erratum 2772121 is a Cat B erratum that applies to
all revisions <=r0p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0e190dabffc20c4d3b9b98d1abeb50f308b80bb9

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Merge "fix: add parenthesis for tests in MIN, MAX and CLAMP macros" into integration

fix(plat/css): fix invalid redistributor poweroff

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf
introduced an invalid redistributor power off
where we turn off the redistributor without
checking i

fix(plat/css): fix invalid redistributor poweroff

Commit 4d8c18196378824e388cf31ef991ba8fbbb09cbf
introduced an invalid redistributor power off
where we turn off the redistributor without
checking if the system power domain level is
turning off, otherwise we can turn off a
redistributor when other cores or clusters are
sharing it, also if it does indeed needs
powering off during suspend we do it twice.
This change fixes this by checking on the
system power state first then turning off
the redistributor.

Signed-off-by: Waleed Elmelegy <waleed.elmelegy@arm.com>
Change-Id: Id202bc2316ab7c516298fa33ea089ae2e221a933

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Merge "fix(zynqmp): fix xck24 silicon ID" into integration

Merge changes from topic "mtk_spm" into integration

* changes:
refactor(mediatek): add new LPM API for further extension
refactor(mediatek): change the parameters of LPM API
refactor(mediatek)

Merge changes from topic "mtk_spm" into integration

* changes:
refactor(mediatek): add new LPM API for further extension
refactor(mediatek): change the parameters of LPM API
refactor(mediatek): change LPM header file path for further extension
feat(mt8188): keep infra and peri on when system suspend
feat(mt8188): enable SPM and LPM
feat(mt8188): add SPM feature support
feat(mt8188): add MT8188 SPM support
feat(mediatek): add SPM's SSPM notifier
feat(mt8188): add the register definitions accessed by SPM
feat(mediatek): add new features of LPM

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fix(zynqmp): fix xck24 silicon ID

Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99

fix(zynqmp): fix xck24 silicon ID

Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99d0c1 ("feat(zynqmp): add support for xck24 silicon").

Change-Id: I727bfe43fd7ef9e604f63bde5fa37fa3666db8c4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "st_dt_update" into integration

* changes:
refactor(stm32mp15-fdts): remove unused PMIC nodes
fix(stm32mp15-fdts): use interrupts-extended for i2c2
style(stm32mp15-fdt

Merge changes from topic "st_dt_update" into integration

* changes:
refactor(stm32mp15-fdts): remove unused PMIC nodes
fix(stm32mp15-fdts): use interrupts-extended for i2c2
style(stm32mp15-fdts): remove extra spaces on vbus

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feat(rme): set DRAM information in Boot Manifest platform data

This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manife

feat(rme): set DRAM information in Boot Manifest platform data

This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manifest' is extended with 'plat_dram' structure
which contains information about platform's DRAM layout:
- number of DRAM banks;
- pointer to 'dram_bank[]' array;
- check sum: two's complement 64-bit value of the sum of
data in 'plat_dram' and 'dram_bank[] array.
Each 'dram_bank' structure holds information about DRAM
bank base address and its size. This values must be aligned
to 4KB page size.
The patch increases Boot Manifest minor version to 2 and
removes 'typedef rmm_manifest_t' as per
"3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I5176caa5780e27d1e0daeb5dea3e40cf6ad5fd12

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Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function

Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function
refactor(ti): use console_set_scope() rather than empty function hack
refactor(ti): factor out common board code into common files
feat(ti): add PSCI system_off support
feat(ti): do not handle EAs in EL3
feat(ti): set snoop-delayed exclusive handling on A72 cores
feat(ti): disable L2 dataless UniqueClean evictions
feat(ti): set L2 cache ECC and and parity on A72 cores
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

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Merge changes from topic "deprecate_io_drivers" into integration

* changes:
refactor(st): remove unused io_mmc driver
docs: deprecate io_dummy driver

Merge changes from topic "refactor_st_common" into integration

* changes:
refactor(st): move board info in common code
refactor(st): move GIC code to common directory
refactor(st): move boot b

Merge changes from topic "refactor_st_common" into integration

* changes:
refactor(st): move board info in common code
refactor(st): move GIC code to common directory
refactor(st): move boot backup register management

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Merge "feat(versal-net): add support for uart1 console" into integration

Merge "docs(security): security advisory for CVE-2022-47630" into integration

docs(security): security advisory for CVE-2022-47630

Reported-by: Demi Marie Obenour <demiobenour@gmail.com>
Co-authored-by: Demi Marie Obenour <demiobenour@gmail.com>
Signed-off-by: Sandrine Baille

docs(security): security advisory for CVE-2022-47630

Reported-by: Demi Marie Obenour <demiobenour@gmail.com>
Co-authored-by: Demi Marie Obenour <demiobenour@gmail.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I20be2d280437eb223c988e2bf59c4562515817a0

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feat(versal-net): add support for uart1 console

Versal NET platform supports two UART(UART0, UART1)
Add support for UART1 to be used as console for Versal NET platform.

Change-Id: I3bc2034f54052e37

feat(versal-net): add support for uart1 console

Versal NET platform supports two UART(UART0, UART1)
Add support for UART1 to be used as console for Versal NET platform.

Change-Id: I3bc2034f54052e37cc480f98d48335fa5b2138bf
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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