feat(qemu): add A76/N1 cpu support for virt

Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I77a3e0bb

feat(qemu): add A76/N1 cpu support for virt

Add support to "cortex-a76" and "neoverse-n1" cpu for "qemu" ('virt')
platform.

Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Change-Id: I77a3e0bb8397a2fb45a2caa7d93ba38e39297f93

show more ...

Merge "fix(tc): unify TC ROM start addresses" into integration

Merge "test(tc): test for AP/RSS NV counter interface" into integration

feat(stm32mp1-fdts): use /omit-if-no-ref/ for pins nodes

With the /omit-if-no-ref/ keyword in DT, the non-referenced nodes
are just removed. This allows reducing the size of device tree blobs.
Setti

feat(stm32mp1-fdts): use /omit-if-no-ref/ for pins nodes

With the /omit-if-no-ref/ keyword in DT, the non-referenced nodes
are just removed. This allows reducing the size of device tree blobs.
Setting it before pins node allows a size reduction of more than 2kB.
The corresponding nodes can also be removed from BL2 and BL32 DT
overlays.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6b4a4d227d5592e1d253a1b35da2dafaac2ddcae

show more ...

feat(st): mandate dtc version 1.4.7

To be able to use /omit-if-no-ref/ in DT files, the dtc version should
be at least 1.4.7. Update the makefile rule that checks dtc version.

Signed-off-by: Yann G

feat(st): mandate dtc version 1.4.7

To be able to use /omit-if-no-ref/ in DT files, the dtc version should
be at least 1.4.7. Update the makefile rule that checks dtc version.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I06bde289cf359a7383694e4c86991dfba781e7d7

show more ...

refactor(st): move mbedtls config files

The files stm32mp_mbedtls_config-{2,3}.h are moved to
plat/st/common/include directory as they could be shared with other ST
platforms. Their prefixes are cha

refactor(st): move mbedtls config files

The files stm32mp_mbedtls_config-{2,3}.h are moved to
plat/st/common/include directory as they could be shared with other ST
platforms. Their prefixes are changed from stm32mp1 to stm32mp.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I86e39481b6c8d2689c59eb9a351b77b3d6233b08

show more ...

refactor(st): add common mk files

Group configuration that could be common to several ST platforms.
Two common makefiles are created: common.mk for definitions and files
to compile, and common_rules

refactor(st): add common mk files

Group configuration that could be common to several ST platforms.
Two common makefiles are created: common.mk for definitions and files
to compile, and common_rules.mk that gathers makefile compilation rules.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7ea9b75c78e7d916854cdd984bbf921b1a46ebc4

show more ...

Merge "style(hooks): adds Arm copyright style fix" into integration

style(hooks): adds Arm copyright style fix

Adds a check to pre-commit hook that makes sure "Arm" is written in a
correct case and not "arm" or "ARM". Same as a copyright-year check, the
hook will fi

style(hooks): adds Arm copyright style fix

Adds a check to pre-commit hook that makes sure "Arm" is written in a
correct case and not "arm" or "ARM". Same as a copyright-year check, the
hook will fix the issue and prompt user to stage the fix.

Change-Id: I39db148d6621d542193f3ee703bddc23c7e8dc27
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

show more ...

Merge "feat(morello): implement methods to retrieve soc-id information" into integration

Merge "fix(versal_net): fix irq for IPI0" into integration

Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin

refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3

BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>

show more ...

feat(ufs): adds timeout and error handling

Adds a common function to poll for interrupt status which reports errors
and returns error codes

Signed-off-by: Anand Saminathan <anans@google.com>
Change

feat(ufs): adds timeout and error handling

Adds a common function to poll for interrupt status which reports errors
and returns error codes

Signed-off-by: Anand Saminathan <anans@google.com>
Change-Id: Ie5df036dc979e984871de4ae7e974b994296ca4c

show more ...

feat(morello): implement methods to retrieve soc-id information

Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
f

feat(morello): implement methods to retrieve soc-id information

Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
for the morello SoC platform. SoC revision, which is same as
silicon revision, is fetched from the morello_plat_info structure
and SoC version is populated with the part number from SSC_VERSION
register, and is reflected in bits[0:15] of soc-id.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I8e0c5b2bc21e393e6d638858cc2ea9f4638f04b9

show more ...

fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by:

fix(versal_net): fix irq for IPI0

Currently isr is not called when IPI0 interrupt occurs.
fix irq number and enable GIC interrupt properly to invoke
registered isr on IPI0 interrupt.

Signed-off-by: Trung Tran <trung.tran@amd.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id0408b3a560b25234886a9fa01c4ed248d1d1532

show more ...

Merge "fix(cpus): workaround for Neoverse V1 errata 2743233" into integration

Merge "fix(rss): fix msg deserialization bugs in comms" into integration

Merge "fix(pmu): switch FVP PMUv3 SPIs to PPI" into integration

Merge "fix(tegra): append major revision to the chip_id value" into integration

Merge "fix(ti): do not take system power reference in bl31_platform_setup()" into integration

Merge "style: fix functions definitions" into integration

Merge changes I9430f5fa,I23680085 into integration

* changes:
feat(build): add support for new binutils versions
build(makefile): add helper to detect linker options

style: fix functions definitions

This is to fix old style functions definitions.

Change-Id: I094b1497dcf948d4d8de4d57d93878aa092ea053
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>

Merge "style: remove useless trailing semicolon and line continuations" into integration