Merge "fix(cpufeat): resolve build errors due to compiler optimization" into integration

fix(cpufeat): resolve build errors due to compiler optimization

Currently most of the architectural feature build flags are set
to 2(FEATURE_STATE_CHECK) for fvp platform only.

However other platfo

fix(cpufeat): resolve build errors due to compiler optimization

Currently most of the architectural feature build flags are set
to 2(FEATURE_STATE_CHECK) for fvp platform only.

However other platforms still configure them by default to 0, which
would lead to build failures in cases when compiler configured
to build TF-A with zero optimization (CFLAGS='-O0').

This patch addresses such build issues and thereby resolves the failures
seen under CI-l3 test_configurations.

Change-Id: I45b82b821951bba6b9df08177f7d286e624a4239
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(mmc): remove redundant reset_to_idle call

mmc_enumerate() is the only caller of mmc_send_op_cond().
mmc_enumerate() calls mmc_reset_to_idle() just before calling
mmc_send_op_cond(). No need to d

fix(mmc): remove redundant reset_to_idle call

mmc_enumerate() is the only caller of mmc_send_op_cond().
mmc_enumerate() calls mmc_reset_to_idle() just before calling
mmc_send_op_cond(). No need to do that again in mmc_send_op_cond().

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Change-Id: Ib8c8ed1a559e3fecb315245f91bb3dc1f547d820

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fix(mbedtls): fix mbedtls coverity issues

commit (a8eadc51a refactor(mbedtls): avoid including
MBEDTLS_CONFIG_FILE) avoids using config file directly and relies on
config file usage from mbedtls ver

fix(mbedtls): fix mbedtls coverity issues

commit (a8eadc51a refactor(mbedtls): avoid including
MBEDTLS_CONFIG_FILE) avoids using config file directly and relies on
config file usage from mbedtls version.h

But we could build trusted boot without mbedtls dir so guard version.h
include in cot_def.h with availability of config file.

Also we refactored in same commit to break dependencies between
auth_mod.h and cot_def.h, So add cot_def.h include in nxp tbbr
cot file.

Change-Id: I4779e90c18f04c73d2121c88df6420b4b1109c8b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(imx8mq): enable dram dvfs support on imx8mq

Enable DRAM DVFS support on i.MX8MQ.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b

feat(imx8m): use non-fast wakeup stop mode for system suspend

Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.

Signed-off-by: Jacky Bai <ping.bai@

feat(imx8m): use non-fast wakeup stop mode for system suspend

Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I37828d4e66ee2ebd48e7adca054b93c520cb2c82

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feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c058

feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c0582ae5f483ffaa887f95e27bd47875f7

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feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jack

feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibe954bc7c4a7b453ace13f8e4b6a335e6d4856c3

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feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_G

feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_GPR register (which now remains always set),
so it can only wake up one core at the time.Also, this entire
workaround has now been moved here in TF-A, allowing the kernel
side to be minimal.

Another advantage this workaround brings is the removal of the
50us delay (which was necessary before in gic_raise_softirq in
kernel) by allowing the core that is waking up to mask his own
IRQ0 in the suspend finish callback.

One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from
asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit
on for each core to exactly the reverse, that is, leaving the
IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1
1st bit for each independent core, we need to use the imx_gpc_core_wake
to wake up the cores.

Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off)
from kernel(gic_raise_softirq), since the new cpuidle workaround
does not need it in order to clean the IOMUX_GPC 12bit. For now,
the udelay seems to be still needed in order to delay the affinity
info OFF for the dying core. This is something that needs further
investigation.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9f17ff6fc3452b8225a50b232964712aafeab78a

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feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be co

feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25

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feat(imx8mq): add version for B2

iMX8MQ B2 chip uses same OCOTP magic value with B1. So
read the ROM version to distinguish it with B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <

feat(imx8mq): add version for B2

iMX8MQ B2 chip uses same OCOTP magic value with B1. So
read the ROM version to distinguish it with B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3e6865922deeb66816a0dddb49d986405e802b6f

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fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.co

fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd

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Merge "fix(rme): update sample platform attestation token" into integration

fix(pauth): make pauth_helpers linking generic

Pauth is a generic Arm feature that can be enabled on any platform that
implements it. It only needs a platform specific key generation hook. As
such,

fix(pauth): make pauth_helpers linking generic

Pauth is a generic Arm feature that can be enabled on any platform that
implements it. It only needs a platform specific key generation hook. As
such, the generic Pauth enablement can be included in the generic build.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf32f79addab3515214594bb8d7168151b450f59

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Merge changes from topic "feat_state_part2" into integration

* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(t

Merge changes from topic "feat_state_part2" into integration

* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
fix(cpufeat): context-switch: move FGT availability check to callers
feat(cpufeat): extend check_feature() to deal with min/max
refactor(cpufeat): wrap CPU ID register field isolation

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Merge changes Ia19c6678,I44baaa47 into integration

* changes:
refactor(auth): clean up certificate length checks
refactor(auth): remove code duplication

fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, t

fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:

1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time),
if not, go to step (2).

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0

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fix(imx8m): fix coverity out of bound access issue

Fix the out of bound access to the rank setting array.

Fix Coverity issue:

CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value

fix(imx8m): fix coverity out of bound access issue

Fix the out of bound access to the rank setting array.

Fix Coverity issue:

CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value (UNUSED_VALUE)

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I5d9ef90f1479e5d46d1b6c8693a27e3abd614766

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fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's

fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explicitly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I113069494074194e116fdb1229052d2956bf90ea

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feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3200mts & 4000mts.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4

feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3200mts & 4000mts.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4b0609f9e7c0f35d75a26ec9ccebec77b3dbe68f

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fix(imx8m): fix the current fsp init

The dfimisc reg value should be shift right 8 bit to
get the current fsp.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.

fix(imx8m): fix the current fsp init

The dfimisc reg value should be shift right 8 bit to
get the current fsp.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I4c8c166bc3ad4cc1376961cbf47631c68b5900cc

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fix(imx8m): fix the rank to rank space issue

update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed

fix(imx8m): fix the rank to rank space issue

update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I0fab18cdc378fda760daa0f89c4dd84eb46f7e11

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refactor(auth): clean up certificate length checks

The previous code was correct but unnecessarily verbose.

Change-Id: Ia19c667811a7c3b6957a0274d36076b0b16e36b7
Signed-off-by: Demi Marie Obenour <d

refactor(auth): clean up certificate length checks

The previous code was correct but unnecessarily verbose.

Change-Id: Ia19c667811a7c3b6957a0274d36076b0b16e36b7
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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refactor(auth): remove code duplication

The unique IDs are handled identically, so just use a for loop to get
both of them.

Change-Id: I44baaa4747ca7f314d364a79dfcbce97315f5a92
Signed-off-by: Demi

refactor(auth): remove code duplication

The unique IDs are handled identically, so just use a for loop to get
both of them.

Change-Id: I44baaa4747ca7f314d364a79dfcbce97315f5a92
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED

At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detecti

refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED

At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_TRF_FOR_NS=2), by splitting
is_feat_trf_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRF related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_trf_supported() function to guard its execution.

The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRF is an ARMv8.4 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.

Change-Id: Ia97b01adbe24970a4d837afd463dc5506b7295a3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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