1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/el3_runtime/pubsub_events.h> 24 #include <lib/extensions/amu.h> 25 #include <lib/extensions/brbe.h> 26 #include <lib/extensions/mpam.h> 27 #include <lib/extensions/sme.h> 28 #include <lib/extensions/spe.h> 29 #include <lib/extensions/sve.h> 30 #include <lib/extensions/sys_reg_trace.h> 31 #include <lib/extensions/trbe.h> 32 #include <lib/extensions/trf.h> 33 #include <lib/utils.h> 34 35 #if ENABLE_FEAT_TWED 36 /* Make sure delay value fits within the range(0-15) */ 37 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 38 #endif /* ENABLE_FEAT_TWED */ 39 40 static void manage_extensions_secure(cpu_context_t *ctx); 41 42 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 43 { 44 u_register_t sctlr_elx, actlr_elx; 45 46 /* 47 * Initialise SCTLR_EL1 to the reset value corresponding to the target 48 * execution state setting all fields rather than relying on the hw. 49 * Some fields have architecturally UNKNOWN reset values and these are 50 * set to zero. 51 * 52 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 53 * 54 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 55 * required by PSCI specification) 56 */ 57 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 58 if (GET_RW(ep->spsr) == MODE_RW_64) { 59 sctlr_elx |= SCTLR_EL1_RES1; 60 } else { 61 /* 62 * If the target execution state is AArch32 then the following 63 * fields need to be set. 64 * 65 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 66 * instructions are not trapped to EL1. 67 * 68 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 69 * instructions are not trapped to EL1. 70 * 71 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 72 * CP15DMB, CP15DSB, and CP15ISB instructions. 73 */ 74 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 75 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 76 } 77 78 #if ERRATA_A75_764081 79 /* 80 * If workaround of errata 764081 for Cortex-A75 is used then set 81 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 82 */ 83 sctlr_elx |= SCTLR_IESB_BIT; 84 #endif 85 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 86 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); 87 88 /* 89 * Base the context ACTLR_EL1 on the current value, as it is 90 * implementation defined. The context restore process will write 91 * the value from the context to the actual register and can cause 92 * problems for processor cores that don't expect certain bits to 93 * be zero. 94 */ 95 actlr_elx = read_actlr_el1(); 96 write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx)); 97 } 98 99 /****************************************************************************** 100 * This function performs initializations that are specific to SECURE state 101 * and updates the cpu context specified by 'ctx'. 102 *****************************************************************************/ 103 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 104 { 105 u_register_t scr_el3; 106 el3_state_t *state; 107 108 state = get_el3state_ctx(ctx); 109 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 110 111 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 112 /* 113 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 114 * indicated by the interrupt routing model for BL31. 115 */ 116 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 117 #endif 118 119 #if !CTX_INCLUDE_MTE_REGS || ENABLE_ASSERTIONS 120 /* Get Memory Tagging Extension support level */ 121 unsigned int mte = get_armv8_5_mte_support(); 122 #endif 123 /* 124 * Allow access to Allocation Tags when CTX_INCLUDE_MTE_REGS 125 * is set, or when MTE is only implemented at EL0. 126 */ 127 #if CTX_INCLUDE_MTE_REGS 128 assert((mte == MTE_IMPLEMENTED_ELX) || (mte == MTE_IMPLEMENTED_ASY)); 129 scr_el3 |= SCR_ATA_BIT; 130 #else 131 if (mte == MTE_IMPLEMENTED_EL0) { 132 scr_el3 |= SCR_ATA_BIT; 133 } 134 #endif /* CTX_INCLUDE_MTE_REGS */ 135 136 /* Enable S-EL2 if the next EL is EL2 and S-EL2 is present */ 137 if ((GET_EL(ep->spsr) == MODE_EL2) && is_feat_sel2_supported()) { 138 if (GET_RW(ep->spsr) != MODE_RW_64) { 139 ERROR("S-EL2 can not be used in AArch32\n."); 140 panic(); 141 } 142 143 scr_el3 |= SCR_EEL2_BIT; 144 } 145 146 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 147 148 /* 149 * Initialize EL1 context registers unless SPMC is running 150 * at S-EL2. 151 */ 152 #if !SPMD_SPM_AT_SEL2 153 setup_el1_context(ctx, ep); 154 #endif 155 156 manage_extensions_secure(ctx); 157 } 158 159 #if ENABLE_RME 160 /****************************************************************************** 161 * This function performs initializations that are specific to REALM state 162 * and updates the cpu context specified by 'ctx'. 163 *****************************************************************************/ 164 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 165 { 166 u_register_t scr_el3; 167 el3_state_t *state; 168 169 state = get_el3state_ctx(ctx); 170 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 171 172 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 173 174 if (is_feat_csv2_2_supported()) { 175 /* Enable access to the SCXTNUM_ELx registers. */ 176 scr_el3 |= SCR_EnSCXT_BIT; 177 } 178 179 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 180 } 181 #endif /* ENABLE_RME */ 182 183 /****************************************************************************** 184 * This function performs initializations that are specific to NON-SECURE state 185 * and updates the cpu context specified by 'ctx'. 186 *****************************************************************************/ 187 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 188 { 189 u_register_t scr_el3; 190 el3_state_t *state; 191 192 state = get_el3state_ctx(ctx); 193 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 194 195 /* SCR_NS: Set the NS bit */ 196 scr_el3 |= SCR_NS_BIT; 197 198 #if !CTX_INCLUDE_PAUTH_REGS 199 /* 200 * If the pointer authentication registers aren't saved during world 201 * switches the value of the registers can be leaked from the Secure to 202 * the Non-secure world. To prevent this, rather than enabling pointer 203 * authentication everywhere, we only enable it in the Non-secure world. 204 * 205 * If the Secure world wants to use pointer authentication, 206 * CTX_INCLUDE_PAUTH_REGS must be set to 1. 207 */ 208 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 209 #endif /* !CTX_INCLUDE_PAUTH_REGS */ 210 211 /* Allow access to Allocation Tags when MTE is implemented. */ 212 scr_el3 |= SCR_ATA_BIT; 213 214 #if HANDLE_EA_EL3_FIRST_NS 215 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 216 scr_el3 |= SCR_EA_BIT; 217 #endif 218 219 #if RAS_TRAP_NS_ERR_REC_ACCESS 220 /* 221 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 222 * and RAS ERX registers from EL1 and EL2(from any security state) 223 * are trapped to EL3. 224 * Set here to trap only for NS EL1/EL2 225 * 226 */ 227 scr_el3 |= SCR_TERR_BIT; 228 #endif 229 230 if (is_feat_csv2_2_supported()) { 231 /* Enable access to the SCXTNUM_ELx registers. */ 232 scr_el3 |= SCR_EnSCXT_BIT; 233 } 234 235 #ifdef IMAGE_BL31 236 /* 237 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 238 * indicated by the interrupt routing model for BL31. 239 */ 240 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 241 #endif 242 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 243 244 /* Initialize EL1 context registers */ 245 setup_el1_context(ctx, ep); 246 247 /* Initialize EL2 context registers */ 248 #if CTX_INCLUDE_EL2_REGS 249 250 /* 251 * Initialize SCTLR_EL2 context register using Endianness value 252 * taken from the entrypoint attribute. 253 */ 254 u_register_t sctlr_el2 = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 255 sctlr_el2 |= SCTLR_EL2_RES1; 256 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_SCTLR_EL2, 257 sctlr_el2); 258 259 /* 260 * Program the ICC_SRE_EL2 to make sure the correct bits are set 261 * when restoring NS context. 262 */ 263 u_register_t icc_sre_el2 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 264 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 265 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_ICC_SRE_EL2, 266 icc_sre_el2); 267 268 /* 269 * Initialize MDCR_EL2.HPMN to its hardware reset value so we don't 270 * throw anyone off who expects this to be sensible. 271 * TODO: A similar thing happens in cm_prepare_el3_exit. They should be 272 * unified with the proper PMU implementation 273 */ 274 u_register_t mdcr_el2 = ((read_pmcr_el0() >> PMCR_EL0_N_SHIFT) & 275 PMCR_EL0_N_MASK); 276 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_MDCR_EL2, mdcr_el2); 277 278 if (is_feat_hcx_supported()) { 279 /* 280 * Initialize register HCRX_EL2 with its init value. 281 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 282 * chance that this can lead to unexpected behavior in lower 283 * ELs that have not been updated since the introduction of 284 * this feature if not properly initialized, especially when 285 * it comes to those bits that enable/disable traps. 286 */ 287 write_ctx_reg(get_el2_sysregs_ctx(ctx), CTX_HCRX_EL2, 288 HCRX_EL2_INIT_VAL); 289 } 290 #endif /* CTX_INCLUDE_EL2_REGS */ 291 } 292 293 /******************************************************************************* 294 * The following function performs initialization of the cpu_context 'ctx' 295 * for first use that is common to all security states, and sets the 296 * initial entrypoint state as specified by the entry_point_info structure. 297 * 298 * The EE and ST attributes are used to configure the endianness and secure 299 * timer availability for the new execution context. 300 ******************************************************************************/ 301 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 302 { 303 u_register_t scr_el3; 304 el3_state_t *state; 305 gp_regs_t *gp_regs; 306 307 /* Clear any residual register values from the context */ 308 zeromem(ctx, sizeof(*ctx)); 309 310 /* 311 * SCR_EL3 was initialised during reset sequence in macro 312 * el3_arch_init_common. This code modifies the SCR_EL3 fields that 313 * affect the next EL. 314 * 315 * The following fields are initially set to zero and then updated to 316 * the required value depending on the state of the SPSR_EL3 and the 317 * Security state and entrypoint attributes of the next EL. 318 */ 319 scr_el3 = read_scr(); 320 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_EA_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | 321 SCR_ST_BIT | SCR_HCE_BIT | SCR_NSE_BIT); 322 323 /* 324 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 325 * Exception level as specified by SPSR. 326 */ 327 if (GET_RW(ep->spsr) == MODE_RW_64) { 328 scr_el3 |= SCR_RW_BIT; 329 } 330 331 /* 332 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 333 * Secure timer registers to EL3, from AArch64 state only, if specified 334 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 335 * bit always behaves as 1 (i.e. secure physical timer register access 336 * is not trapped) 337 */ 338 if (EP_GET_ST(ep->h.attr) != 0U) { 339 scr_el3 |= SCR_ST_BIT; 340 } 341 342 /* 343 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 344 * SCR_EL3.HXEn. 345 */ 346 if (is_feat_hcx_supported()) { 347 scr_el3 |= SCR_HXEn_BIT; 348 } 349 350 /* 351 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 352 * registers are trapped to EL3. 353 */ 354 #if ENABLE_FEAT_RNG_TRAP 355 scr_el3 |= SCR_TRNDR_BIT; 356 #endif 357 358 #if FAULT_INJECTION_SUPPORT 359 /* Enable fault injection from lower ELs */ 360 scr_el3 |= SCR_FIEN_BIT; 361 #endif 362 363 /* 364 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 365 */ 366 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 367 scr_el3 |= SCR_TCR2EN_BIT; 368 } 369 370 /* 371 * CPTR_EL3 was initialized out of reset, copy that value to the 372 * context register. 373 */ 374 write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); 375 376 /* 377 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 378 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 379 * next mode is Hyp. 380 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 381 * same conditions as HVC instructions and when the processor supports 382 * ARMv8.6-FGT. 383 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 384 * CNTPOFF_EL2 register under the same conditions as HVC instructions 385 * and when the processor supports ECV. 386 */ 387 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 388 || ((GET_RW(ep->spsr) != MODE_RW_64) 389 && (GET_M32(ep->spsr) == MODE32_hyp))) { 390 scr_el3 |= SCR_HCE_BIT; 391 392 if (is_feat_fgt_supported()) { 393 scr_el3 |= SCR_FGTEN_BIT; 394 } 395 396 if (is_feat_ecv_supported()) { 397 scr_el3 |= SCR_ECVEN_BIT; 398 } 399 } 400 401 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 402 if (is_feat_twed_supported()) { 403 /* Set delay in SCR_EL3 */ 404 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 405 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 406 << SCR_TWEDEL_SHIFT); 407 408 /* Enable WFE delay */ 409 scr_el3 |= SCR_TWEDEn_BIT; 410 } 411 412 /* 413 * Populate EL3 state so that we've the right context 414 * before doing ERET 415 */ 416 state = get_el3state_ctx(ctx); 417 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 418 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 419 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 420 421 /* 422 * Store the X0-X7 value from the entrypoint into the context 423 * Use memcpy as we are in control of the layout of the structures 424 */ 425 gp_regs = get_gpregs_ctx(ctx); 426 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 427 } 428 429 /******************************************************************************* 430 * Context management library initialization routine. This library is used by 431 * runtime services to share pointers to 'cpu_context' structures for secure 432 * non-secure and realm states. Management of the structures and their associated 433 * memory is not done by the context management library e.g. the PSCI service 434 * manages the cpu context used for entry from and exit to the non-secure state. 435 * The Secure payload dispatcher service manages the context(s) corresponding to 436 * the secure state. It also uses this library to get access to the non-secure 437 * state cpu context pointers. 438 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 439 * which will be used for programming an entry into a lower EL. The same context 440 * will be used to save state upon exception entry from that EL. 441 ******************************************************************************/ 442 void __init cm_init(void) 443 { 444 /* 445 * The context management library has only global data to intialize, but 446 * that will be done when the BSS is zeroed out. 447 */ 448 } 449 450 /******************************************************************************* 451 * This is the high-level function used to initialize the cpu_context 'ctx' for 452 * first use. It performs initializations that are common to all security states 453 * and initializations specific to the security state specified in 'ep' 454 ******************************************************************************/ 455 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 456 { 457 unsigned int security_state; 458 459 assert(ctx != NULL); 460 461 /* 462 * Perform initializations that are common 463 * to all security states 464 */ 465 setup_context_common(ctx, ep); 466 467 security_state = GET_SECURITY_STATE(ep->h.attr); 468 469 /* Perform security state specific initializations */ 470 switch (security_state) { 471 case SECURE: 472 setup_secure_context(ctx, ep); 473 break; 474 #if ENABLE_RME 475 case REALM: 476 setup_realm_context(ctx, ep); 477 break; 478 #endif 479 case NON_SECURE: 480 setup_ns_context(ctx, ep); 481 break; 482 default: 483 ERROR("Invalid security state\n"); 484 panic(); 485 break; 486 } 487 } 488 489 /******************************************************************************* 490 * Enable architecture extensions on first entry to Non-secure world. 491 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise 492 * it is zero. 493 ******************************************************************************/ 494 static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) 495 { 496 #if IMAGE_BL31 497 if (is_feat_spe_supported()) { 498 spe_enable(el2_unused); 499 } 500 501 if (is_feat_amu_supported()) { 502 amu_enable(el2_unused, ctx); 503 } 504 505 /* Enable SME, SVE, and FPU/SIMD for non-secure world. */ 506 if (is_feat_sme_supported()) { 507 sme_enable(ctx); 508 } else if (is_feat_sve_supported()) { 509 /* Enable SVE and FPU/SIMD for non-secure world. */ 510 sve_enable(ctx); 511 } 512 513 if (is_feat_mpam_supported()) { 514 mpam_enable(el2_unused); 515 } 516 517 if (is_feat_trbe_supported()) { 518 trbe_enable(); 519 } 520 521 if (is_feat_brbe_supported()) { 522 brbe_enable(); 523 } 524 525 if (is_feat_sys_reg_trace_supported()) { 526 sys_reg_trace_enable(ctx); 527 } 528 529 if (is_feat_trf_supported()) { 530 trf_enable(); 531 } 532 #endif 533 } 534 535 /******************************************************************************* 536 * Enable architecture extensions on first entry to Secure world. 537 ******************************************************************************/ 538 static void manage_extensions_secure(cpu_context_t *ctx) 539 { 540 #if IMAGE_BL31 541 542 if (is_feat_sme_supported()) { 543 if (ENABLE_SME_FOR_SWD) { 544 /* 545 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 546 * must ensure SME, SVE, and FPU/SIMD context properly managed. 547 */ 548 sme_enable(ctx); 549 } else { 550 /* 551 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 552 * world can safely use the associated registers. 553 */ 554 sme_disable(ctx); 555 } 556 } else if (is_feat_sve_supported()) { 557 if (ENABLE_SVE_FOR_SWD) { 558 /* 559 * Enable SVE and FPU in secure context, secure manager must 560 * ensure that the SVE and FPU register contexts are properly 561 * managed. 562 */ 563 sve_enable(ctx); 564 } else { 565 /* 566 * Disable SVE and FPU in secure context so non-secure world 567 * can safely use them. 568 */ 569 sve_disable(ctx); 570 } 571 } 572 573 #endif /* IMAGE_BL31 */ 574 } 575 576 /******************************************************************************* 577 * The following function initializes the cpu_context for a CPU specified by 578 * its `cpu_idx` for first use, and sets the initial entrypoint state as 579 * specified by the entry_point_info structure. 580 ******************************************************************************/ 581 void cm_init_context_by_index(unsigned int cpu_idx, 582 const entry_point_info_t *ep) 583 { 584 cpu_context_t *ctx; 585 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 586 cm_setup_context(ctx, ep); 587 } 588 589 /******************************************************************************* 590 * The following function initializes the cpu_context for the current CPU 591 * for first use, and sets the initial entrypoint state as specified by the 592 * entry_point_info structure. 593 ******************************************************************************/ 594 void cm_init_my_context(const entry_point_info_t *ep) 595 { 596 cpu_context_t *ctx; 597 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 598 cm_setup_context(ctx, ep); 599 } 600 601 /******************************************************************************* 602 * Prepare the CPU system registers for first entry into realm, secure, or 603 * normal world. 604 * 605 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 606 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 607 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 608 * For all entries, the EL1 registers are initialized from the cpu_context 609 ******************************************************************************/ 610 void cm_prepare_el3_exit(uint32_t security_state) 611 { 612 u_register_t sctlr_elx, scr_el3, mdcr_el2; 613 cpu_context_t *ctx = cm_get_context(security_state); 614 bool el2_unused = false; 615 uint64_t hcr_el2 = 0U; 616 617 assert(ctx != NULL); 618 619 if (security_state == NON_SECURE) { 620 uint64_t el2_implemented = el_implemented(2); 621 622 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 623 CTX_SCR_EL3); 624 625 if (((scr_el3 & SCR_HCE_BIT) != 0U) 626 || (el2_implemented != EL_IMPL_NONE)) { 627 /* 628 * If context is not being used for EL2, initialize 629 * HCRX_EL2 with its init value here. 630 */ 631 if (is_feat_hcx_supported()) { 632 write_hcrx_el2(HCRX_EL2_INIT_VAL); 633 } 634 } 635 636 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 637 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ 638 sctlr_elx = read_ctx_reg(get_el1_sysregs_ctx(ctx), 639 CTX_SCTLR_EL1); 640 sctlr_elx &= SCTLR_EE_BIT; 641 sctlr_elx |= SCTLR_EL2_RES1; 642 #if ERRATA_A75_764081 643 /* 644 * If workaround of errata 764081 for Cortex-A75 is used 645 * then set SCTLR_EL2.IESB to enable Implicit Error 646 * Synchronization Barrier. 647 */ 648 sctlr_elx |= SCTLR_IESB_BIT; 649 #endif 650 write_sctlr_el2(sctlr_elx); 651 } else if (el2_implemented != EL_IMPL_NONE) { 652 el2_unused = true; 653 654 /* 655 * EL2 present but unused, need to disable safely. 656 * SCTLR_EL2 can be ignored in this case. 657 * 658 * Set EL2 register width appropriately: Set HCR_EL2 659 * field to match SCR_EL3.RW. 660 */ 661 if ((scr_el3 & SCR_RW_BIT) != 0U) 662 hcr_el2 |= HCR_RW_BIT; 663 664 /* 665 * For Armv8.3 pointer authentication feature, disable 666 * traps to EL2 when accessing key registers or using 667 * pointer authentication instructions from lower ELs. 668 */ 669 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 670 671 write_hcr_el2(hcr_el2); 672 673 /* 674 * Initialise CPTR_EL2 setting all fields rather than 675 * relying on the hw. All fields have architecturally 676 * UNKNOWN reset values. 677 * 678 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1 679 * accesses to the CPACR_EL1 or CPACR from both 680 * Execution states do not trap to EL2. 681 * 682 * CPTR_EL2.TTA: Set to zero so that Non-secure System 683 * register accesses to the trace registers from both 684 * Execution states do not trap to EL2. 685 * If PE trace unit System registers are not implemented 686 * then this bit is reserved, and must be set to zero. 687 * 688 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses 689 * to SIMD and floating-point functionality from both 690 * Execution states do not trap to EL2. 691 */ 692 write_cptr_el2(CPTR_EL2_RESET_VAL & 693 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT 694 | CPTR_EL2_TFP_BIT)); 695 696 /* 697 * Initialise CNTHCTL_EL2. All fields are 698 * architecturally UNKNOWN on reset and are set to zero 699 * except for field(s) listed below. 700 * 701 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to 702 * Hyp mode of Non-secure EL0 and EL1 accesses to the 703 * physical timer registers. 704 * 705 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to 706 * Hyp mode of Non-secure EL0 and EL1 accesses to the 707 * physical counter registers. 708 */ 709 write_cnthctl_el2(CNTHCTL_RESET_VAL | 710 EL1PCEN_BIT | EL1PCTEN_BIT); 711 712 /* 713 * Initialise CNTVOFF_EL2 to zero as it resets to an 714 * architecturally UNKNOWN value. 715 */ 716 write_cntvoff_el2(0); 717 718 /* 719 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and 720 * MPIDR_EL1 respectively. 721 */ 722 write_vpidr_el2(read_midr_el1()); 723 write_vmpidr_el2(read_mpidr_el1()); 724 725 /* 726 * Initialise VTTBR_EL2. All fields are architecturally 727 * UNKNOWN on reset. 728 * 729 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 730 * 2 address translation is disabled, cache maintenance 731 * operations depend on the VMID. 732 * 733 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address 734 * translation is disabled. 735 */ 736 write_vttbr_el2(VTTBR_RESET_VAL & 737 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) 738 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 739 740 /* 741 * Initialise MDCR_EL2, setting all fields rather than 742 * relying on hw. Some fields are architecturally 743 * UNKNOWN on reset. 744 * 745 * MDCR_EL2.HLP: Set to one so that event counter 746 * overflow, that is recorded in PMOVSCLR_EL0[0-30], 747 * occurs on the increment that changes 748 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is 749 * implemented. This bit is RES0 in versions of the 750 * architecture earlier than ARMv8.5, setting it to 1 751 * doesn't have any effect on them. 752 * 753 * MDCR_EL2.TTRF: Set to zero so that access to Trace 754 * Filter Control register TRFCR_EL1 at EL1 is not 755 * trapped to EL2. This bit is RES0 in versions of 756 * the architecture earlier than ARMv8.4. 757 * 758 * MDCR_EL2.HPMD: Set to one so that event counting is 759 * prohibited at EL2. This bit is RES0 in versions of 760 * the architecture earlier than ARMv8.1, setting it 761 * to 1 doesn't have any effect on them. 762 * 763 * MDCR_EL2.TPMS: Set to zero so that accesses to 764 * Statistical Profiling control registers from EL1 765 * do not trap to EL2. This bit is RES0 when SPE is 766 * not implemented. 767 * 768 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and 769 * EL1 System register accesses to the Debug ROM 770 * registers are not trapped to EL2. 771 * 772 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 773 * System register accesses to the powerdown debug 774 * registers are not trapped to EL2. 775 * 776 * MDCR_EL2.TDA: Set to zero so that System register 777 * accesses to the debug registers do not trap to EL2. 778 * 779 * MDCR_EL2.TDE: Set to zero so that debug exceptions 780 * are not routed to EL2. 781 * 782 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance 783 * Monitors. 784 * 785 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and 786 * EL1 accesses to all Performance Monitors registers 787 * are not trapped to EL2. 788 * 789 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0 790 * and EL1 accesses to the PMCR_EL0 or PMCR are not 791 * trapped to EL2. 792 * 793 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the 794 * architecturally-defined reset value. 795 * 796 * MDCR_EL2.E2TB: Set to zero so that the trace Buffer 797 * owning exception level is NS-EL1 and, tracing is 798 * prohibited at NS-EL2. These bits are RES0 when 799 * FEAT_TRBE is not implemented. 800 */ 801 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP | 802 MDCR_EL2_HPMD) | 803 ((read_pmcr_el0() & PMCR_EL0_N_BITS) 804 >> PMCR_EL0_N_SHIFT)) & 805 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS | 806 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | 807 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT | 808 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT | 809 MDCR_EL2_TPMCR_BIT | 810 MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)); 811 812 write_mdcr_el2(mdcr_el2); 813 814 /* 815 * Initialise HSTR_EL2. All fields are architecturally 816 * UNKNOWN on reset. 817 * 818 * HSTR_EL2.T<n>: Set all these fields to zero so that 819 * Non-secure EL0 or EL1 accesses to System registers 820 * do not trap to EL2. 821 */ 822 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 823 /* 824 * Initialise CNTHP_CTL_EL2. All fields are 825 * architecturally UNKNOWN on reset. 826 * 827 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 828 * physical timer and prevent timer interrupts. 829 */ 830 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & 831 ~(CNTHP_CTL_ENABLE_BIT)); 832 } 833 manage_extensions_nonsecure(el2_unused, ctx); 834 } 835 836 cm_el1_sysregs_context_restore(security_state); 837 cm_set_next_eret_context(security_state); 838 } 839 840 #if CTX_INCLUDE_EL2_REGS 841 842 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 843 { 844 write_ctx_reg(ctx, CTX_HDFGRTR_EL2, read_hdfgrtr_el2()); 845 if (is_feat_amu_supported()) { 846 write_ctx_reg(ctx, CTX_HAFGRTR_EL2, read_hafgrtr_el2()); 847 } 848 write_ctx_reg(ctx, CTX_HDFGWTR_EL2, read_hdfgwtr_el2()); 849 write_ctx_reg(ctx, CTX_HFGITR_EL2, read_hfgitr_el2()); 850 write_ctx_reg(ctx, CTX_HFGRTR_EL2, read_hfgrtr_el2()); 851 write_ctx_reg(ctx, CTX_HFGWTR_EL2, read_hfgwtr_el2()); 852 } 853 854 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 855 { 856 write_hdfgrtr_el2(read_ctx_reg(ctx, CTX_HDFGRTR_EL2)); 857 if (is_feat_amu_supported()) { 858 write_hafgrtr_el2(read_ctx_reg(ctx, CTX_HAFGRTR_EL2)); 859 } 860 write_hdfgwtr_el2(read_ctx_reg(ctx, CTX_HDFGWTR_EL2)); 861 write_hfgitr_el2(read_ctx_reg(ctx, CTX_HFGITR_EL2)); 862 write_hfgrtr_el2(read_ctx_reg(ctx, CTX_HFGRTR_EL2)); 863 write_hfgwtr_el2(read_ctx_reg(ctx, CTX_HFGWTR_EL2)); 864 } 865 866 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 867 { 868 u_register_t mpam_idr = read_mpamidr_el1(); 869 870 write_ctx_reg(ctx, CTX_MPAM2_EL2, read_mpam2_el2()); 871 872 /* 873 * The context registers that we intend to save would be part of the 874 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 875 */ 876 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 877 return; 878 } 879 880 /* 881 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 882 * MPAMIDR_HAS_HCR_BIT == 1. 883 */ 884 write_ctx_reg(ctx, CTX_MPAMHCR_EL2, read_mpamhcr_el2()); 885 write_ctx_reg(ctx, CTX_MPAMVPM0_EL2, read_mpamvpm0_el2()); 886 write_ctx_reg(ctx, CTX_MPAMVPMV_EL2, read_mpamvpmv_el2()); 887 888 /* 889 * The number of MPAMVPM registers is implementation defined, their 890 * number is stored in the MPAMIDR_EL1 register. 891 */ 892 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 893 case 7: 894 write_ctx_reg(ctx, CTX_MPAMVPM7_EL2, read_mpamvpm7_el2()); 895 __fallthrough; 896 case 6: 897 write_ctx_reg(ctx, CTX_MPAMVPM6_EL2, read_mpamvpm6_el2()); 898 __fallthrough; 899 case 5: 900 write_ctx_reg(ctx, CTX_MPAMVPM5_EL2, read_mpamvpm5_el2()); 901 __fallthrough; 902 case 4: 903 write_ctx_reg(ctx, CTX_MPAMVPM4_EL2, read_mpamvpm4_el2()); 904 __fallthrough; 905 case 3: 906 write_ctx_reg(ctx, CTX_MPAMVPM3_EL2, read_mpamvpm3_el2()); 907 __fallthrough; 908 case 2: 909 write_ctx_reg(ctx, CTX_MPAMVPM2_EL2, read_mpamvpm2_el2()); 910 __fallthrough; 911 case 1: 912 write_ctx_reg(ctx, CTX_MPAMVPM1_EL2, read_mpamvpm1_el2()); 913 break; 914 } 915 } 916 917 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 918 { 919 u_register_t mpam_idr = read_mpamidr_el1(); 920 921 write_mpam2_el2(read_ctx_reg(ctx, CTX_MPAM2_EL2)); 922 923 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 924 return; 925 } 926 927 write_mpamhcr_el2(read_ctx_reg(ctx, CTX_MPAMHCR_EL2)); 928 write_mpamvpm0_el2(read_ctx_reg(ctx, CTX_MPAMVPM0_EL2)); 929 write_mpamvpmv_el2(read_ctx_reg(ctx, CTX_MPAMVPMV_EL2)); 930 931 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 932 case 7: 933 write_mpamvpm7_el2(read_ctx_reg(ctx, CTX_MPAMVPM7_EL2)); 934 __fallthrough; 935 case 6: 936 write_mpamvpm6_el2(read_ctx_reg(ctx, CTX_MPAMVPM6_EL2)); 937 __fallthrough; 938 case 5: 939 write_mpamvpm5_el2(read_ctx_reg(ctx, CTX_MPAMVPM5_EL2)); 940 __fallthrough; 941 case 4: 942 write_mpamvpm4_el2(read_ctx_reg(ctx, CTX_MPAMVPM4_EL2)); 943 __fallthrough; 944 case 3: 945 write_mpamvpm3_el2(read_ctx_reg(ctx, CTX_MPAMVPM3_EL2)); 946 __fallthrough; 947 case 2: 948 write_mpamvpm2_el2(read_ctx_reg(ctx, CTX_MPAMVPM2_EL2)); 949 __fallthrough; 950 case 1: 951 write_mpamvpm1_el2(read_ctx_reg(ctx, CTX_MPAMVPM1_EL2)); 952 break; 953 } 954 } 955 956 /******************************************************************************* 957 * Save EL2 sysreg context 958 ******************************************************************************/ 959 void cm_el2_sysregs_context_save(uint32_t security_state) 960 { 961 u_register_t scr_el3 = read_scr(); 962 963 /* 964 * Always save the non-secure and realm EL2 context, only save the 965 * S-EL2 context if S-EL2 is enabled. 966 */ 967 if ((security_state != SECURE) || 968 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 969 cpu_context_t *ctx; 970 el2_sysregs_t *el2_sysregs_ctx; 971 972 ctx = cm_get_context(security_state); 973 assert(ctx != NULL); 974 975 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 976 977 el2_sysregs_context_save_common(el2_sysregs_ctx); 978 #if CTX_INCLUDE_MTE_REGS 979 el2_sysregs_context_save_mte(el2_sysregs_ctx); 980 #endif 981 if (is_feat_mpam_supported()) { 982 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 983 } 984 985 if (is_feat_fgt_supported()) { 986 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 987 } 988 989 if (is_feat_ecv_v2_supported()) { 990 write_ctx_reg(el2_sysregs_ctx, CTX_CNTPOFF_EL2, 991 read_cntpoff_el2()); 992 } 993 994 if (is_feat_vhe_supported()) { 995 write_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2, 996 read_contextidr_el2()); 997 write_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2, 998 read_ttbr1_el2()); 999 } 1000 #if RAS_EXTENSION 1001 el2_sysregs_context_save_ras(el2_sysregs_ctx); 1002 #endif 1003 1004 if (is_feat_nv2_supported()) { 1005 write_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2, 1006 read_vncr_el2()); 1007 } 1008 1009 if (is_feat_trf_supported()) { 1010 write_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2, read_trfcr_el2()); 1011 } 1012 1013 if (is_feat_csv2_2_supported()) { 1014 write_ctx_reg(el2_sysregs_ctx, CTX_SCXTNUM_EL2, 1015 read_scxtnum_el2()); 1016 } 1017 1018 if (is_feat_hcx_supported()) { 1019 write_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2, read_hcrx_el2()); 1020 } 1021 if (is_feat_tcr2_supported()) { 1022 write_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2, read_tcr2_el2()); 1023 } 1024 } 1025 } 1026 1027 /******************************************************************************* 1028 * Restore EL2 sysreg context 1029 ******************************************************************************/ 1030 void cm_el2_sysregs_context_restore(uint32_t security_state) 1031 { 1032 u_register_t scr_el3 = read_scr(); 1033 1034 /* 1035 * Always restore the non-secure and realm EL2 context, only restore the 1036 * S-EL2 context if S-EL2 is enabled. 1037 */ 1038 if ((security_state != SECURE) || 1039 ((security_state == SECURE) && ((scr_el3 & SCR_EEL2_BIT) != 0U))) { 1040 cpu_context_t *ctx; 1041 el2_sysregs_t *el2_sysregs_ctx; 1042 1043 ctx = cm_get_context(security_state); 1044 assert(ctx != NULL); 1045 1046 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1047 1048 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1049 #if CTX_INCLUDE_MTE_REGS 1050 el2_sysregs_context_restore_mte(el2_sysregs_ctx); 1051 #endif 1052 if (is_feat_mpam_supported()) { 1053 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1054 } 1055 1056 if (is_feat_fgt_supported()) { 1057 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1058 } 1059 1060 if (is_feat_ecv_v2_supported()) { 1061 write_cntpoff_el2(read_ctx_reg(el2_sysregs_ctx, 1062 CTX_CNTPOFF_EL2)); 1063 } 1064 1065 if (is_feat_vhe_supported()) { 1066 write_contextidr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_CONTEXTIDR_EL2)); 1067 write_ttbr1_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TTBR1_EL2)); 1068 } 1069 #if RAS_EXTENSION 1070 el2_sysregs_context_restore_ras(el2_sysregs_ctx); 1071 #endif 1072 1073 if (is_feat_nv2_supported()) { 1074 write_vncr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_VNCR_EL2)); 1075 } 1076 if (is_feat_trf_supported()) { 1077 write_trfcr_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TRFCR_EL2)); 1078 } 1079 1080 if (is_feat_csv2_2_supported()) { 1081 write_scxtnum_el2(read_ctx_reg(el2_sysregs_ctx, 1082 CTX_SCXTNUM_EL2)); 1083 } 1084 1085 if (is_feat_hcx_supported()) { 1086 write_hcrx_el2(read_ctx_reg(el2_sysregs_ctx, CTX_HCRX_EL2)); 1087 } 1088 if (is_feat_tcr2_supported()) { 1089 write_tcr2_el2(read_ctx_reg(el2_sysregs_ctx, CTX_TCR2_EL2)); 1090 } 1091 } 1092 } 1093 #endif /* CTX_INCLUDE_EL2_REGS */ 1094 1095 /******************************************************************************* 1096 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1097 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1098 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1099 * cm_prepare_el3_exit function. 1100 ******************************************************************************/ 1101 void cm_prepare_el3_exit_ns(void) 1102 { 1103 #if CTX_INCLUDE_EL2_REGS 1104 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1105 assert(ctx != NULL); 1106 1107 /* Assert that EL2 is used. */ 1108 #if ENABLE_ASSERTIONS 1109 el3_state_t *state = get_el3state_ctx(ctx); 1110 u_register_t scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1111 #endif 1112 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1113 (el_implemented(2U) != EL_IMPL_NONE)); 1114 1115 /* 1116 * Currently some extensions are configured using 1117 * direct register updates. Therefore, do this here 1118 * instead of when setting up context. 1119 */ 1120 manage_extensions_nonsecure(0, ctx); 1121 1122 /* 1123 * Set the NS bit to be able to access the ICC_SRE_EL2 1124 * register when restoring context. 1125 */ 1126 write_scr_el3(read_scr_el3() | SCR_NS_BIT); 1127 1128 /* 1129 * Ensure the NS bit change is committed before the EL2/EL1 1130 * state restoration. 1131 */ 1132 isb(); 1133 1134 /* Restore EL2 and EL1 sysreg contexts */ 1135 cm_el2_sysregs_context_restore(NON_SECURE); 1136 cm_el1_sysregs_context_restore(NON_SECURE); 1137 cm_set_next_eret_context(NON_SECURE); 1138 #else 1139 cm_prepare_el3_exit(NON_SECURE); 1140 #endif /* CTX_INCLUDE_EL2_REGS */ 1141 } 1142 1143 /******************************************************************************* 1144 * The next four functions are used by runtime services to save and restore 1145 * EL1 context on the 'cpu_context' structure for the specified security 1146 * state. 1147 ******************************************************************************/ 1148 void cm_el1_sysregs_context_save(uint32_t security_state) 1149 { 1150 cpu_context_t *ctx; 1151 1152 ctx = cm_get_context(security_state); 1153 assert(ctx != NULL); 1154 1155 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1156 1157 #if IMAGE_BL31 1158 if (security_state == SECURE) 1159 PUBLISH_EVENT(cm_exited_secure_world); 1160 else 1161 PUBLISH_EVENT(cm_exited_normal_world); 1162 #endif 1163 } 1164 1165 void cm_el1_sysregs_context_restore(uint32_t security_state) 1166 { 1167 cpu_context_t *ctx; 1168 1169 ctx = cm_get_context(security_state); 1170 assert(ctx != NULL); 1171 1172 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1173 1174 #if IMAGE_BL31 1175 if (security_state == SECURE) 1176 PUBLISH_EVENT(cm_entering_secure_world); 1177 else 1178 PUBLISH_EVENT(cm_entering_normal_world); 1179 #endif 1180 } 1181 1182 /******************************************************************************* 1183 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1184 * given security state with the given entrypoint 1185 ******************************************************************************/ 1186 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1187 { 1188 cpu_context_t *ctx; 1189 el3_state_t *state; 1190 1191 ctx = cm_get_context(security_state); 1192 assert(ctx != NULL); 1193 1194 /* Populate EL3 state so that ERET jumps to the correct entry */ 1195 state = get_el3state_ctx(ctx); 1196 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1197 } 1198 1199 /******************************************************************************* 1200 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1201 * pertaining to the given security state 1202 ******************************************************************************/ 1203 void cm_set_elr_spsr_el3(uint32_t security_state, 1204 uintptr_t entrypoint, uint32_t spsr) 1205 { 1206 cpu_context_t *ctx; 1207 el3_state_t *state; 1208 1209 ctx = cm_get_context(security_state); 1210 assert(ctx != NULL); 1211 1212 /* Populate EL3 state so that ERET jumps to the correct entry */ 1213 state = get_el3state_ctx(ctx); 1214 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1215 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1216 } 1217 1218 /******************************************************************************* 1219 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1220 * pertaining to the given security state using the value and bit position 1221 * specified in the parameters. It preserves all other bits. 1222 ******************************************************************************/ 1223 void cm_write_scr_el3_bit(uint32_t security_state, 1224 uint32_t bit_pos, 1225 uint32_t value) 1226 { 1227 cpu_context_t *ctx; 1228 el3_state_t *state; 1229 u_register_t scr_el3; 1230 1231 ctx = cm_get_context(security_state); 1232 assert(ctx != NULL); 1233 1234 /* Ensure that the bit position is a valid one */ 1235 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1236 1237 /* Ensure that the 'value' is only a bit wide */ 1238 assert(value <= 1U); 1239 1240 /* 1241 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1242 * and set it to its new value. 1243 */ 1244 state = get_el3state_ctx(ctx); 1245 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1246 scr_el3 &= ~(1UL << bit_pos); 1247 scr_el3 |= (u_register_t)value << bit_pos; 1248 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1249 } 1250 1251 /******************************************************************************* 1252 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1253 * given security state. 1254 ******************************************************************************/ 1255 u_register_t cm_get_scr_el3(uint32_t security_state) 1256 { 1257 cpu_context_t *ctx; 1258 el3_state_t *state; 1259 1260 ctx = cm_get_context(security_state); 1261 assert(ctx != NULL); 1262 1263 /* Populate EL3 state so that ERET jumps to the correct entry */ 1264 state = get_el3state_ctx(ctx); 1265 return read_ctx_reg(state, CTX_SCR_EL3); 1266 } 1267 1268 /******************************************************************************* 1269 * This function is used to program the context that's used for exception 1270 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 1271 * the required security state 1272 ******************************************************************************/ 1273 void cm_set_next_eret_context(uint32_t security_state) 1274 { 1275 cpu_context_t *ctx; 1276 1277 ctx = cm_get_context(security_state); 1278 assert(ctx != NULL); 1279 1280 cm_set_next_context(ctx); 1281 } 1282