fix(xilinx): handle CRC failure in IPI callback

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.

fix(xilinx): handle CRC failure in IPI callback

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read_callb() logs error message but don't return
error code to upper layers.

Added CRC failure specific error code which will be returned by
pm_ipi_buff_read_callb() if CRC validation fails.

Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I2eaca073e2bf325a8c86b1820bdd7cca487b783e

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fix(xilinx): handle CRC failure in IPI

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read() logs error message but don't return error
code to upper layers.

Added CRC fail

fix(xilinx): handle CRC failure in IPI

Currently, if CRC validation fails during IPI communication,
pm_ipi_buff_read() logs error message but don't return error
code to upper layers.

Added CRC failure specific error code which will be returned by
pm_ipi_buff_read() if CRC validation fails.

Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: I33be330f276973471f4ce4115d1e1609ed8fb754

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feat(spmd): fail safe if SPM fails to initialize

The spmd_setup function is made fail safe in that a failure in the
SPMC manifest parsing, SPMD or SPMC initialization returns a success
code to the s

feat(spmd): fail safe if SPM fails to initialize

The spmd_setup function is made fail safe in that a failure in the
SPMC manifest parsing, SPMD or SPMC initialization returns a success
code to the standard services initialization routine (std_svc_setup).
This permits continuing the boot process and initialize services
beyond the SPMD to succeed for the system to operate in the normal
world. It operates in a degraded mode for the secure world.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ida0ac91c17925279a79f112d190f9ad038f518e7

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fix(cpus): workaround for Cortex-A78C erratum 2779484

Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.

The workaround is to set the CPUACTLR

fix(cpus): workaround for Cortex-A78C erratum 2779484

Cortex-A78C erratum 2779484 is a Cat B erratum that applies to
revisions r0p1 and r0p2 and is still open.

The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this
bit might have a small impact on power and negligible impact on
performance.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2004089/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed

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fix(cpus): workaround for Cortex-A78 erratum 2742426

Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR5_EL

fix(cpus): workaround for Cortex-A78 erratum 2742426

Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.

The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1

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feat(fvp): copy the Event Log to TZC secured DRAM area

Copied the Event Log from internal SRAM to the TZC secured DRAM
reserved area. Also passed this Trusted DRAM address to OPTEE via
NT FW configu

feat(fvp): copy the Event Log to TZC secured DRAM area

Copied the Event Log from internal SRAM to the TZC secured DRAM
reserved area. Also passed this Trusted DRAM address to OPTEE via
NT FW configuration, and to SPMC via TOS FW configuration,
which is eventually used to extend PCR via fTPM application running
on top of OPTEE/SPMC.

Furthermore, this patch makes it easier to access Event Log in RME
enabled systems where Secure World firmware does not have access to
internal(Root) SRAM.

Change-Id: I005e9da1e6075511f412bdf4d8b541fa543df9ab
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(arm): carveout DRAM1 area for Event Log

Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent

feat(arm): carveout DRAM1 area for Event Log

Reserved 4KB area for Event Log in DRAM1. This area is used by BL2
to copy Event Log from internal SRAM to this carved out DRAM region
in the subsequent patch.

Change-Id: I7b405775c66d249e31edf7688d95770e6c05c175
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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test(tc): test for AP/RSS NV counter interface

Change in PLATFORM_TEST build flag from boolean -> string, with the
current string options being tfm-testsuite and rss-nv-counters.

To get the old beh

test(tc): test for AP/RSS NV counter interface

Change in PLATFORM_TEST build flag from boolean -> string, with the
current string options being tfm-testsuite and rss-nv-counters.

To get the old behavior, i.e. where we used to use PLATFORM_TEST=1,
we now need to pass PLATFORM_TEST=tfm-testsuite.

Adding new test of the AP/RSS interface for non-volatile counters.
The test reads, increments, and reads again each 3 types of NV
counters for: CCA, secure, and non-secure firmware. Enabled by
PLATFORM_TEST=rss-nv-counters.

Change-Id: I2044cc9b2f37984697e0754c9c824eab51a11e7f
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Signed-off-by: Raef Coles <raef.coles@arm.com>

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docs: add guidelines for thirdparty includes

Currently there is no guidelines in docs for including thirdparty
includes, trying to address that with a proposed method to use third
party includes.

C

docs: add guidelines for thirdparty includes

Currently there is no guidelines in docs for including thirdparty
includes, trying to address that with a proposed method to use third
party includes.

Change-Id: Ieec7a5c88a60b66ca72228741ba1894545130a06
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(tc): change the FIP offset to 8 KiB boundary" into integration

fix(tc): change the FIP offset to 8 KiB boundary

* This change overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT

* This aligns the FIP base in GPT image to the RSS ATU page size
boundary (8 KiB).

fix(tc): change the FIP offset to 8 KiB boundary

* This change overrides the default PLAT_ARM_FIP_OFFSET_IN_GPT

* This aligns the FIP base in GPT image to the RSS ATU page size
boundary (8 KiB). RSS XIP feature requires the FIP to be aligned to
the page size boundary. TC platform will require the XIP feature.

* The aligned FIP_A is starting at sector 48. Hence the offset will be
48*512 = 0x6000.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Change-Id: I8135ecd4168231847c80151c33ef8353a1586b9a

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fix(ti): do not take system power reference in bl31_platform_setup()

Taking a reference at this early stage can cause boot failure if the DM
firmware is not fully initialized. Remove this early call

fix(ti): do not take system power reference in bl31_platform_setup()

Taking a reference at this early stage can cause boot failure if the DM
firmware is not fully initialized. Remove this early call until the
fix in DM firmware is widely available.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic9c47ccf1e9a1b9faeb1c7d2665d54cf55ef5396

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fix(pmu): switch FVP PMUv3 SPIs to PPI

FVP PMUv3 SPIs legacy interrupts are only listed for
cluster #0 and are missing for cluster #1.
This patch changes FVP SPIs to PMUv3 PPI as in
arm_fpga.dtsi, m

fix(pmu): switch FVP PMUv3 SPIs to PPI

FVP PMUv3 SPIs legacy interrupts are only listed for
cluster #0 and are missing for cluster #1.
This patch changes FVP SPIs to PMUv3 PPI as in
arm_fpga.dtsi, morello.dtsi and n1sdp.dtsi.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ic624cec09ba932666c746ae1a6a4b78b6decde96

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docs(zynqmp): add ddr address usage

Update documentation for TF-A DDR address range usage when the FSBL is
run on RPU instead of APU.

Change-Id: I223d67c35ac9ce3384820531a7453d3b32a1eb58
Signed-off

docs(zynqmp): add ddr address usage

Update documentation for TF-A DDR address range usage when the FSBL is
run on RPU instead of APU.

Change-Id: I223d67c35ac9ce3384820531a7453d3b32a1eb58
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "docs: discourage usage of weak functions" into integration

docs: discourage usage of weak functions

As a coding guideline, we now discourage introducing new weak
functions in platform-agnostic code going forward and provide the
rationale for this.

This was

docs: discourage usage of weak functions

As a coding guideline, we now discourage introducing new weak
functions in platform-agnostic code going forward and provide the
rationale for this.

This was already enforced most of the time in code reviews but this
patch makes it explicit in the project's documentation.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I88f4a55788899fb4146c4d26afb3a7418376b30c

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fix(rss): fix msg deserialization bugs in comms

-fix1: size of struct instead of pointer during reply_size check
-fix2: update the out_vec length with the actual length from reply
message (e.

fix(rss): fix msg deserialization bugs in comms

-fix1: size of struct instead of pointer during reply_size check
-fix2: update the out_vec length with the actual length from reply
message (e.g. in case of an output buffer, the returned output
data length remained the size of the buffer and was not updated
with the size of the actual data in it)

Change-Id: Ibed5520ca1fb05df358de4bdf85ace219183866c
Signed-off-by: David Vincze <david.vincze@arm.com>

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Merge "docs(spm): add other-s-interrupts-action field to sp manifest" into integration

feat(stm32mp15-fdts): add support for prtt1x board family

Add one device tree to support a family of boards (PRTT1C, PRTT1S,
PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for
indust

feat(stm32mp15-fdts): add support for prtt1x board family

Add one device tree to support a family of boards (PRTT1C, PRTT1S,
PRTT1A) based on STM32MP151AAD3, used as sensors and actuators for
industrial, 10BaseT1L based networks.

This change was tested with barebox 2022.12.0 bootloader and kernel
v6.2.0-rc1.

Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Change-Id: Ibab9933eadd7aa379ae0a7c7ccbfc2fbb9a44ca8

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Merge "fix(zynqmp): conditional reservation of memory in DTB" into integration

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This create

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.

To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "fix(mbedtls): fix mbedtls coverity issues" into integration

Merge "refactor(auth): use a single function for parsing extensions" into integration

refactor(auth): use a single function for parsing extensions

Previously, extensions were parsed twice: once with error checking for
validation, and a second time without error checking to extract th

refactor(auth): use a single function for parsing extensions

Previously, extensions were parsed twice: once with error checking for
validation, and a second time without error checking to extract the
extension data. This is error prone and caused TFV-10 (CVE-2022-47630).

A simpler approach is to have get_ext() be responsible for all extension
parsing, and to treat a NULL OID as an indicator that get_ext() is only
being called for validation. cert_parse() checks that get_ext() returns
IMG_PARSER_OK and fails otherwise.

Change-Id: I65a2ff053a188351ba54799827a2b7bd833bb037
Signed-off-by: Demi Marie Obenour <demiobenour@gmail.com>

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Merge "fix(docs): add plantuml as a dependency" into integration