Merge "feat(imx8): add support for debug uart on lpuart1" into integration

Merge "build(hooks): allow hooks to skip Commitizen" into integration

feat: add support for poetry

New python dependencies are introduced by the memory mapping script.
Rather than add another `requirements.txt` utilise poetry. This is a
proper dependency management fr

feat: add support for poetry

New python dependencies are introduced by the memory mapping script.
Rather than add another `requirements.txt` utilise poetry. This is a
proper dependency management framework for Python. The two main upsides
of using poetry instead of the traditional requirements.txt are
maintainability and reproducibility.

Poetry provides a proper lock file for pinning dependencies, similar to
npm for JavaScript. This allows for separate environments (i.e. docs,
tools) to be created efficiently, and in a reproducible manner, wherever
the project is deployed. Having dependencies pinned in this manner is a
boon as a security focused project. An additional upside is that we will
receive security updates for dependencies via GitHub's Dependabot.

Change-Id: I5a3c2003769b878a464c8feac0f789e5ecf8d56c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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docs(threat-model): add a notes related to the Measured Boot

TF-A currently does not have any TPM2 driver for extending
measurements into a discrete TPM chip. In TPM-based attestation
scheme, measur

docs(threat-model): add a notes related to the Measured Boot

TF-A currently does not have any TPM2 driver for extending
measurements into a discrete TPM chip. In TPM-based attestation
scheme, measurements are just stored into a TCG-compatible event
log buffer in secure memory.

In light of the fact that Event Log measurements are taken by BL1 and
BL2, we need to trust these components to store genuine measurements,
and the Generic Threat Model always mitigates against attacks on these
components, therefore, there is no explicit document for the Measured
Boot threat model at this time is needed.

Change-Id: I41b037b2f5956d327b53cd834345e5aefdcfb5ef
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(morello): remove duplication of platform information struct

morello_plat_info is defined identically in multiple files, definition
is moved to a header file to avoid duplication.

Signed-of

refactor(morello): remove duplication of platform information struct

morello_plat_info is defined identically in multiple files, definition
is moved to a header file to avoid duplication.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I607354902c55f5c31f0732de9db60604b82aef97

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Merge "feat(fvp): add Event Log maximum size property in DT" into integration

build(hooks): allow hooks to skip Commitizen

Adds a conditional check in the `prepare-commit-msg` commit hook that
reads the `tf-a.disableCommitizen` Git configuration option, and
does not execute C

build(hooks): allow hooks to skip Commitizen

Adds a conditional check in the `prepare-commit-msg` commit hook that
reads the `tf-a.disableCommitizen` Git configuration option, and
does not execute Commitizen if it is found.

To skip Commitizen, run:

git config tf-a.disableCommitizen true

Change-Id: Ic8967f6f42bf3555df09b57096044fb99438d4d4
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size a

feat(fvp): add Event Log maximum size property in DT

Updated the code to get and set the 'tpm_event_log_max_size' property
in the event_log.dtsi.

In this change, the maximum Event Log buffer size allocated by BL1 is
passed to BL2, rather than both relying on the maximum Event Log buffer
size macro.

Change-Id: I7aa6256390872171e362b6f166f3f7335aa6e425
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "feat(docs): allow verbose build" into integration

feat(tcr2): add FEAT_TCR2 to the changelog

This was omitted from the patch adding the feature.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: Ie7f2b63434a70320178be74fc3f165618aca8392

feat(gcs): support guarded control stack

Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the c

feat(gcs): support guarded control stack

Arm v9.4 introduces support for Guarded Control Stack, providing
mitigations against some forms of RPO attacks and an efficient mechanism
for obtaining the current call stack without requiring a full stack
unwind. Enable access to this feature for EL2 and below, context
switching the newly added EL2 registers as appropriate.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Signed-off-by: Mark Brown <broonie@kernel.org>
Change-Id: I691aa7c22e3547bb3abe98d96993baf18c5f0e7b

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build(trp): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly

build(trp): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: Ife89a8bb9e592b55c761d9a3dfefc2aeeb07802f
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(tsp): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly

build(tsp): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: Id702a2a572f2b43c77d53634ddc64b0220d2560b
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(sp-min): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicit

build(sp-min): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: I33d5044e4d34a9d1187d0935ffc03d1f1177e340
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(bl31): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly

build(bl31): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: Iadcd38a66a7a9f4b2af3adbc0487a15091486b17
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(bl2u): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly

build(bl2u): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: I2745327ed106295e0e0d3a54b3096514a1403c3c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(bl2): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly

build(bl2): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: Id70be2a5399c4c75fcf2a736cab0991d20a6b863
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(bl1): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly

build(bl1): sort sections by alignment by default

This change forces LD to sort all input sections by alignment when
allocating them within an output section. This is done in some places
explicitly in the linker scripts today, but this makes sure we don't
miss any easy targets.

Change-Id: I69d6acea822036a6365a7ea10fa732b5e0387f52
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(uuid): add missing `#include` directives

These include directives were missing from both `uuid.h` files.

Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304
Signed-off-by: Chris Kay <chris.kay

fix(uuid): add missing `#include` directives

These include directives were missing from both `uuid.h` files.

Change-Id: I875dfda3e0985728277b72f0e7597dde5cf9d304
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes I43a9d83c,Ibfaa47fb into integration

* changes:
fix(intel): fix Agilex and N5X clock manager to main PLL C0
feat(intel): implement timer init divider via CPU frequency for N5X

feat(imx8): add support for debug uart on lpuart1

Needed for TQMa8Xx on MBa8Xx. With this changes it is
possible to build:

$ make PLAT=imx8qx IMX_DEBUG_UART=1 DEBUG_CONSOLE=1 bl31

Signed-off-by: M

feat(imx8): add support for debug uart on lpuart1

Needed for TQMa8Xx on MBa8Xx. With this changes it is
possible to build:

$ make PLAT=imx8qx IMX_DEBUG_UART=1 DEBUG_CONSOLE=1 bl31

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Change-Id: If380845b254f30fe919ebb33c86130597c4b8ad3

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fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS

Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it

fix(zynqmp): remove unused PLAT_NUM_POWER_DOMAINS

Remove unused PLAT_NUM_POWER_DOMAINS macro. Macro is referenced by
docs/design/psci-pd-tree.rst but it is not used in any calculation
that's why it is better to remove it.

Change-Id: I33f26cda6a4404061af5598ea4c751f64127e50a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(versal): switch to xlat_v2

Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.

Change-Id: I3f27591caf944dc758cc45ee870

feat(versal): switch to xlat_v2

Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.

Change-Id: I3f27591caf944dc758cc45ee870b9b5b3ff0a18d
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(xilinx): remove asserts around arg0/arg1

The commit a6f340fe58b9 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platfo

fix(xilinx): remove asserts around arg0/arg1

The commit a6f340fe58b9 ("Introduce the new BL handover interface")
extended handoff to 4 registers instead of 2. Arguments arg0-3 are
not used by platform code but in future they can be used for it.
But it doesn't make sense to checking their unused value.

Change-Id: I151e4b1574465409424453c054d937487086b79a
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(versal): replace FPD_MAINCCI* macros" into integration