Merge "fix(versal): modify IPI4 and IPI5 trigger bit definitions" into integration

fix(versal): modify IPI4 and IPI5 trigger bit definitions

The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI com

fix(versal): modify IPI4 and IPI5 trigger bit definitions

The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI communication failures between processing units in
Versal SoCs. So, modified the trigger bits to align the software
definitions with the hardware register specification as documented
in the register database.

Change-Id: I1e32961124daf8e5635906fb615e98a650130f27
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>

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Merge "chore(vscode): ignore noisy directories" into integration

Merge "chore(changelog): add Visual Studio Code scope" into integration

refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS

WRAPPER_FLAGS is this awkward exception to linker related flags that is
defined in the build_macros file which is only meant to provide macros.
It

refactor(romlib): absorb WRAPPER_FLAGS into LDFLAGS

WRAPPER_FLAGS is this awkward exception to linker related flags that is
defined in the build_macros file which is only meant to provide macros.
It also relies on being lazily evaluated as at the time of its expansion
BUILD_PLAT is not defined yet. It's also another variable in the myriad
of others.

So absorb it into ldflags-common in cflags.mk. This brings it in line
with all the rest and gets rid of its weird quirkiness.

Change-Id: Id711e38774a22fd0f20a26c827a505e40de18e50
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(build): simplify the -target options

It turns out that there are a lot of ways to specify the target
triplets, some of which are identical in meaning. This allows us to use
a single unambiguous

fix(build): simplify the -target options

It turns out that there are a lot of ways to specify the target
triplets, some of which are identical in meaning. This allows us to use
a single unambiguous triplet regardless of build flags.

This was spotted in
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/36980/comment/ced50479_a1e937c0/

Change-Id: I531a2ee17e621c93373f9ededc0e654c79480e31
Co-developed-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): allow full LTO builds with clang

GCC doesn't like LTOing __builtins. This has been broken for time
immemorial (see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63215) and
there is no fi

feat(build): allow full LTO builds with clang

GCC doesn't like LTOing __builtins. This has been broken for time
immemorial (see https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63215) and
there is no fix coming. Prior to GCC 14 a build of the libc with LTO
will simply not work. From GCC14 a workaround is possible passing
-ffat-lto-objects. The underlying issue is that the linker "forgets"
about builtin symbols it added during LTO. The non-LTO copies make these
forgotten functions available during final resolution. However, this
still does not LTO the libc, it just allows for it to build with -flto.

Since GCC is our main compiler, and we do not differentiate the libc
from any other lib we build, we have simply not built libs with LTO so
far. However, there is no need to kneecap clang for GCC's failings, so
LTO all libs on clang when enabled.

When GCC14 becomes the oldest reasonable compiler we support, this can
be done for GCC too, although with the workaround above. This still
won't LTO the libc, but it will at least LTO other libs.

Change-Id: Ic5b4851480131f4e8aefd678cc05d4dd02ee01ef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): make sorting of sections generic

All BLs define essentially the same sequence for sorting of sections.
Make that generic so it applies more easily.

Change-Id: I81f5f6635232bd43d999

refactor(build): make sorting of sections generic

All BLs define essentially the same sequence for sorting of sections.
Make that generic so it applies more easily.

Change-Id: I81f5f6635232bd43d999c8054e290a6437c26c71
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies

feat(build): use clang as a linker

To support LTO, the gcc binary is used as a compiler, assembler, and
linker. Do the same for clang and enable LTO builds with it as a side
effect.

This simplifies code quite a bit as the gcc/clang different is much
smaller. Support for ld/lld (if overriden with LD) is maintained.

This is a good time to convert tabs to spaces to conform to make's
expectations on syntax.

Change-Id: I6c529c1393f7e9e8046ed537f871fc3ad91d599a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(build): correctly detect that an option is missing with ld_option

We support building directly with ld and indirectly with gcc. The
`ld_option` macro is oblivious to this and does a check for bo

fix(build): correctly detect that an option is missing with ld_option

We support building directly with ld and indirectly with gcc. The
`ld_option` macro is oblivious to this and does a check for both styles
of invocation. However, the gcc one is incorrect - gcc returns `0` even
when it has printed an error saying that it doesn't recognise the
option. Add a discovery function for each linker we expect and
dynamically dispatch to the correct one.

While we're at it, also add a little bit of code to return the -Wl
prefix for gcc and not for ld.

All of the above is also true for clang and lld, although they don't
suffer from the problem that gcc does.

Change-Id: I4f7bdf40c01f4c5df9c177f5048f5e349bc2b9c9
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pa

feat(build): pass cflags to the linker when LTO is enabled

Usually, both compiling and linking happen by calling the top level
gcc/clang binary. Also, both compilers quite specifically tell us to
pass the same flags to the compilation and linking stages when we enable
LTO. This is crucial for things like the undefined behaviour sanitiser.
Anecdotally, in working on this, there have been a fair few errors that
the compiler has only been able to catch due to warning flags being
passed to the linker and building with LTO.

This patch puts the contents of TF_CFLAGS into TF_LDFLAGS when LTO is
enabled. This is easier said than done, however, as we support building
with clang and linking with gcc (or vice versa), so CFLAGS that are
discovered for one will not work for the other. This patch works around
this by splitting all flags into a per-compiler variable. Then CFLAGS
and LDFLAGS get the contents of the correct one.

Some notable side effects: CPPFLAGS and TF_CFLAGS_$(ARCH) become empty
and are removed, although expanding them is kept as platforms set them.
Some flags become duplicate and are removed form TF_LDFLAGS (eg -O1).

The errata (--fix) flags are kept as-is but moved to cpu-ops.mk for
consistency. This is because they currently don't work with LTO and will
be addressed in a later patch.

Finally, ERROR_DEPRECATED's flags are also identical on all compilers so
don't maintain a difference.

Change-Id: I3630729ee5f474c09d4722cd0ede6845e1725d95
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "build(changelog): add new scope for Altera platform" into integration

Merge changes I44f90daa,I0fed6ef4,I018869d3,I9089b3ad,Ibf5b3a80 into integration

* changes:
refactor(fvp): always build RAS files
fix(fvp): give fvp_ras.c better dependencies
fix(cpufeat): add

Merge changes I44f90daa,I0fed6ef4,I018869d3,I9089b3ad,Ibf5b3a80 into integration

* changes:
refactor(fvp): always build RAS files
fix(fvp): give fvp_ras.c better dependencies
fix(cpufeat): add ras files to the build from a common location
fix(cm): do not restore spsr and elr twice on external aborts
fix(cm): do not save SCR_EL3 on external aborts

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fix(scmi): change error code output for wrong ids

This changes the error code output in the power and clock domain for
a non-existing device and clock id from SCMI_INVALID_PARAMETER to
SCMI_NOT_FOUN

fix(scmi): change error code output for wrong ids

This changes the error code output in the power and clock domain for
a non-existing device and clock id from SCMI_INVALID_PARAMETER to
SCMI_NOT_FOUND in accordance to the SCMI specification

Change-Id: Ica2a549635a8a52393bed38a5e35bd63a873a3d9
Signed-off-by: Scaria Kochidanadu <s-kochidanadu@ti.com>

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Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG

Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG for psci

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Merge changes I6770567a,I4567d75b,Id65d5ba4 into integration

* changes:
refactor: fix workaround order for Cortex-A720
fix(cpus): workaround for Cortex-A720 erratum 2729604
fix(cpus): workarou

Merge changes I6770567a,I4567d75b,Id65d5ba4 into integration

* changes:
refactor: fix workaround order for Cortex-A720
fix(cpus): workaround for Cortex-A720 erratum 2729604
fix(cpus): workaround for Cortex-A720 erratum 3711910

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build(changelog): add new scope for Altera platform

Add new scope for Altera platform.

Change-Id: I8a9ab38e8e5c5b7b36f957309266fedff310f3c2
Signed-off-by: Sieu Mun Tang <sieumun93@gmail.com>

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those system registers are trapped by the SCR_EL3.AIEn bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_AIE build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: Iba2011719013a89f9cb3a4317bde18254f45cd25
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was

fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was passed to the firmware which is incorrect. Pass NON_SECURE
flag from the platform specific file to the firmware in order to
align with the PSCI specification.

Change-Id: Iabe2cb45467cf63fe36626d323513ff05548eb3b
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359

fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(rcar3): clear TCR_EL1 at the BL2 entry point

According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to a

fix(rcar3): clear TCR_EL1 at the BL2 entry point

According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to an architecturally UNKNOWN value.

On some SoCs, after reset, this TCR_EL1 may not be 0, which in itself
is perfectly valid behavior. However, existing software may depend on
TCR_EL1 being 0, and the UNKNOWN value may confuse such software.

Reset TCR_EL1 to well defined value 0 at BL2 entrypoint to achieve
maximum compatibility.

[1] https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message
Change-Id: If3a1d40291b9b9768a8fc55e750bd742f3cc4ddc
---
Note: This is related to MR 25532 , but with reworked commit message
and broken out from the large work-in-progress series.

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refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

$(OBJS): %.o: %.s
...

These behave similarly, but have some subtle differences. The former
defines a rule "for any target matching %.o where there is not a more
specific rule", whereas the latter defines a rule "for these targets,
which match %.o".

Where possible it is better to use a static pattern rule as it reduces
the rule space that Make needs to search.

Change-Id: Ifba4f44bcecf4e74980c31347e192cdf1e42003e
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(docs): fix some broken links

Fix few broken links from docs.

Link check was done with following steps -

[..]
tf-a/docs$ make clean -j8; poetry run make html -j8
tf-a/docs$ poetry run sphinx-bu

fix(docs): fix some broken links

Fix few broken links from docs.

Link check was done with following steps -

[..]
tf-a/docs$ make clean -j8; poetry run make html -j8
tf-a/docs$ poetry run sphinx-build -j8 -q -b linkcheck . build/
[..]

Add link check conf values to config.py
- avoid reporting false broken links when `#`(anchors) are present
in the link.
- avoid checking for broken links in "change-log.md", this is summary
of commit msg's we are not going to fix broken links in cmt-msg's

Change-Id: I384094c8dcf3e93875c9052afa79ad826b9901d9
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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refactor: fix workaround order for Cortex-A720

One of the Cortex-A720 errata was below the CVE workaround, this
moves it up to the correct place.

Change-Id: I6770567a9580973ceedb5911f0a495391ef9e83

refactor: fix workaround order for Cortex-A720

One of the Cortex-A720 errata was below the CVE workaround, this
moves it up to the correct place.

Change-Id: I6770567a9580973ceedb5911f0a495391ef9e839
Signed-off-by: John Powell <john.powell@arm.com>

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