Merge changes from topic "lw/errata_refactor" into integration

* changes:
refactor(cpus): convert Neoverse-N1 to use helpers
refactor(cpus): convert Neoverse-N1 to framework
refactor(cpus): re

Merge changes from topic "lw/errata_refactor" into integration

* changes:
refactor(cpus): convert Neoverse-N1 to use helpers
refactor(cpus): convert Neoverse-N1 to framework
refactor(cpus): reorder Neoverse-N1 .S file
refactor(cpus): convert Neoverse-E1 to framework

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Merge "feat(morello): add support for I2S audio" into integration

Merge "Revert "docs: disable PDF output for documentation generation"" into integration

feat(morello): add support for I2S audio

Add support for Morello I2S audio subsystem. This includes adding the
audio formatter and I2S transmitter nodes and gluing them together with
the hdmi codec

feat(morello): add support for I2S audio

Add support for Morello I2S audio subsystem. This includes adding the
audio formatter and I2S transmitter nodes and gluing them together with
the hdmi codec using a simple sound card machine node.

Change-Id: I3de4b06ef965c8e0555d074118b944fe6b4b78bb
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Faiz Abbas <faiz.abbas@arm.com>

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Revert "docs: disable PDF output for documentation generation"

This reverts commit 279e28ed3526bfcfb8d8bc736e4f5aafd3d73ba3.

Reason for revert: Re-enable the pdf generation since the necessary fix

Revert "docs: disable PDF output for documentation generation"

This reverts commit 279e28ed3526bfcfb8d8bc736e4f5aafd3d73ba3.

Reason for revert: Re-enable the pdf generation since the necessary fix to generate pdf has already been merged.

Change-Id: Ia68e8caea94b5d89fcf182251a13473b32b4bfad

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refactor(cpus): convert the Cortex-x2 to use cpu helpers

Change-Id: Ic1016eb8598dbba08cdfc3bdaa24f90411d83a7c
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(cpus): convert the Cortex-x2 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu

refactor(cpus): convert the Cortex-x2 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata.

* Testing via script was not complete, as it directed to verify the
check and the workaround functions of few erratas manually.

* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Manual comparison of disassembly of both both files(bl31.elf)
ensured,the ported changes were identical and hence verified.

* Build for release with all errata flags enabled and run default tftf
tests.

CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp \
ARCH=aarch64 \
DEBUG=0 \
HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 \
CTX_INCLUDE_AARCH32_REGS=0 \
ERRATA_X2_2002765=1 \
ERRATA_X2_2017096=1 \
ERRATA_X2_2058056=1 \
ERRATA_X2_2081180=1 \
ERRATA_X2_2083908=1 \
ERRATA_X2_2147715=1 \
ERRATA_X2_2216384=1 \
ERRATA_X2_2282622=1 \
ERRATA_X2_2371105=1 \
ERRATA_X2_2768515=1 \
WORKAROUND_CVE_2022_23960=1 \
ERRATA_DSU_2313941=1 \
BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
fip all -j12

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure that if Errata are applicable then the workaround
functions are entered precisely.

Change-Id: Icd2268cdf27f41240c92e3df23b5ad22f3ce3124
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): reorder Cortex-x2 errata by ascending order

Change-Id: Ic1b2c73f468db6bb434b5b23f345bfc37d2a7833
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(cpus): convert the Cortex-A65AE to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <

refactor(cpus): convert the Cortex-A65AE to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
* This core has only errata related to DSU, which is defined under
another file dsu_helpers.s but gets applied to A65AE as well.
Hence symbolic names have been added to get them registered under
errata framework.

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Testing was conducted by:
* Building for release with all errata flags enabled and running
script in change 19136 to compare output of objdump for each errata.

* Testing via script was not complete, as it directed to verify the
check and the workaround functions of few erratas manually.

* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Manual comparison of disassembly of both both files(bl31.elf)
ensured, the ported changes were identical and hence verified.

* Build for release with all errata flags enabled and run default
tftf tests.

CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp \
ARCH=aarch64 \
DEBUG=0 \
HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 \
CTX_INCLUDE_AARCH32_REGS=0 \
ERRATA_DSU_936184=1 \
BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
fip all -j12

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure that if Errata are applicable then the workaround
functions are entered precisely. In this case, errata is not
applied as DSU does not has the ACP interface and hence the
check_errata_dsu_936184 returns 0.

* In summary, porting work for this CPU, does not adds any new changes
as we are just creating macros via .equ, henceforth code remains
identical.

Change-Id: Iab37295319b5ccd69428185b2d22af0ca9c07a5e
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): convert the Cortex-A510 to use cpu helpers

Change-Id: I6d26092525c2d5255a741515071ee7ed873aa52d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(cpus): convert the Cortex-A510 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <c

refactor(cpus): convert the Cortex-A510 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

Note: cortex_a510.S is applicable and being used only by arm_fpga platform.

However, to test the ported changes, below steps were carried out on the
fvp and the obtained results has been verified.

Testing was conducted by:
* Building for release with all errata flags enabled and running script
in change 19136 to compare output of objdump for each errata.

* Testing via script was not complete, as it directed to verify the
check and the workaround functions of few erratas manually.

* Manual comparison of disassembly of converted functions with non-
converted functions

aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

* Manual comparison of disassembly of both both files(bl31.elf)
ensured, the ported changes were identical and hence verified.

* Build for release with all errata flags enabled and run default
tftf tests.

CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp \
ARCH=aarch64 \
DEBUG=0 \
HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 \
CTX_INCLUDE_AARCH32_REGS=0 \
ERRATA_A510_1922240=1 \
ERRATA_A510_2288014=1 \
ERRATA_A510_2042739=1 \
ERRATA_A510_2041909=1 \
ERRATA_A510_2250311=1 \
ERRATA_A510_2218950=1 \
ERRATA_A510_2172148=1 \
ERRATA_A510_2347730=1 \
ERRATA_A510_2371937=1 \
ERRATA_A510_2666669=1 \
ERRATA_A510_2684597=1 \
ERRATA_DSU_2313941=1 \
BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
fip all -j12

* Build for debug with all errata enabled and step through ArmDS
at reset to ensure that if Errata are applicable then the
workaround functions are entered precisely.

Change-Id: Icf7aa25c0b3b30f5e2ad6db83953f7f4f0b201d9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): reorder Cortex-A510 errata by ascending order

Change-Id: Id6b4ae42d413f2c501c8200305cdb8068219912b
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

chore(fvp): add Aarch32 Cortex-A53 to the build

Change-Id: I493893d38d2db80e2c4d2efcf832c712a9abe5a8
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(cpus): add Cortex-A53 errata framework information

Change-Id: I3518847728fa17baa423cfef66694895a39ee888
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

feat(cpus): add errata framework helpers

Adding an helper macro for bit field insert(bic) instruction
to group all the operations related to it.

Change-Id: Idfd06c7f38faf52090f62b458d2d96c2682f63fe

feat(cpus): add errata framework helpers

Adding an helper macro for bit field insert(bic) instruction
to group all the operations related to it.

Change-Id: Idfd06c7f38faf52090f62b458d2d96c2682f63fe
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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chore(brcm): include cpu_helpers.S for bl2 build

With errata conversion in place for Cortex_A72 cpu,
build fails with undefined reference to functions defined
in cpu_helpers.S file.
Including the sa

chore(brcm): include cpu_helpers.S for bl2 build

With errata conversion in place for Cortex_A72 cpu,
build fails with undefined reference to functions defined
in cpu_helpers.S file.
Including the same to handle build issues related to
Stingray platform.

Change-Id: I2bab3e5ca0811d83cd9ee43ac33d557afe6575a8
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): convert Neoverse-N1 to use helpers

Conversion to use CPU helpers for Neoverse-N1 testing done with
framework adaptation patch.

Change-Id: I2103f6e64daf0ee4c7b756083e5bf485f15c0e21
S

refactor(cpus): convert Neoverse-N1 to use helpers

Conversion to use CPU helpers for Neoverse-N1 testing done with
framework adaptation patch.

Change-Id: I2103f6e64daf0ee4c7b756083e5bf485f15c0e21
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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refactor(cpus): convert Neoverse-N1 to framework

For N1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_erra

refactor(cpus): convert Neoverse-N1 to framework

For N1, this involves replacing:
- The reset_func with the standard cpu_reset_func_{start,end}
to apply errata automatically
- The <cpu>_errata_report with the errata_report_shim to
report errata automatically
And for each erratum:
- The prologue with the workaround_<type>_start to do the checks and
framework registration automatically at reset or runtime
- The epilogue with the workaround_<type>_end
- The checker function with the check_erratum_<type> to check whether
the erratum applies on the revision of the CPU.

Testing was conducted by:
- Manual comparison of disassembly of converted functions with non-
converted functions:

aarch64-none-elf-objdump -D
<trusted-firmware-a with conversion>/build/fvp/release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D
<trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf

- Build for debug with all errata enabled and step through ArmDS
to ensure all functions are entered and the path remains the same
as before conversion to the new framework.

Change-Id: I2ea612d4c197dd73835fadda81f59732c19534f8
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(nuvoton): added support for npcm845x chip

Initial version

Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: If433d325a90b519ae5f02411865bffd368ff2824

feat(measured-boot): introduce platform function to measure and publish Public Key

Added a platform function to measure and publish Public Key information.
Subsequent patches define this function fo

feat(measured-boot): introduce platform function to measure and publish Public Key

Added a platform function to measure and publish Public Key information.
Subsequent patches define this function for the FVP and TC platforms to
measure Public Key and publishes it to RSS if MEASURED_BOOT is
enabled.

Change-Id: I1f61f44c7a83bb4cbafbd1af97b5adeb8398e8e8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "chore(docs): update march utility details" into integration

Merge "feat(imx8m): detect console base address during runtime" into integration

Merge "fix(el3-spmc): fix incorrect CASSERT" into integration

Merge "fix(cpus): workaround for Neoverse V2 erratum 2801372" into integration

feat(imx8m): detect console base address during runtime

Provide a helper to detect the enabled UART device during runtime. This
lower the integration effort and make it more straight forward for
'si

feat(imx8m): detect console base address during runtime

Provide a helper to detect the enabled UART device during runtime. This
lower the integration effort and make it more straight forward for
'simple' use-cases with a single UART enabled. If multiple UARTs are
enabled the first enabled is returned.

The auto-detection is enabled by setting IMX_BOOT_UART_BASE=0 to keep
the backward compatibility. For more advanced use-cases (multiple UARTs
are enabled) the user still has to provide the correct base address.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I300a167e1a10f9aa991c8d1c3efe2c6b23f56c47

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