1 /* 2 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_common.h> 23 #include <stm32mp_dt.h> 24 #include <stm32mp1_dbgmcu.h> 25 #include <stm32mp1_private.h> 26 #include <stm32mp1_shared_resources.h> 27 #endif 28 29 #include "stm32mp1_fip_def.h" 30 31 /******************************************************************************* 32 * CHIP ID 33 ******************************************************************************/ 34 #if STM32MP13 35 #define STM32MP1_CHIP_ID U(0x501) 36 37 #define STM32MP135C_PART_NB U(0x05010000) 38 #define STM32MP135A_PART_NB U(0x05010001) 39 #define STM32MP133C_PART_NB U(0x050100C0) 40 #define STM32MP133A_PART_NB U(0x050100C1) 41 #define STM32MP131C_PART_NB U(0x050106C8) 42 #define STM32MP131A_PART_NB U(0x050106C9) 43 #define STM32MP135F_PART_NB U(0x05010800) 44 #define STM32MP135D_PART_NB U(0x05010801) 45 #define STM32MP133F_PART_NB U(0x050108C0) 46 #define STM32MP133D_PART_NB U(0x050108C1) 47 #define STM32MP131F_PART_NB U(0x05010EC8) 48 #define STM32MP131D_PART_NB U(0x05010EC9) 49 #endif 50 #if STM32MP15 51 #define STM32MP1_CHIP_ID U(0x500) 52 53 #define STM32MP157C_PART_NB U(0x05000000) 54 #define STM32MP157A_PART_NB U(0x05000001) 55 #define STM32MP153C_PART_NB U(0x05000024) 56 #define STM32MP153A_PART_NB U(0x05000025) 57 #define STM32MP151C_PART_NB U(0x0500002E) 58 #define STM32MP151A_PART_NB U(0x0500002F) 59 #define STM32MP157F_PART_NB U(0x05000080) 60 #define STM32MP157D_PART_NB U(0x05000081) 61 #define STM32MP153F_PART_NB U(0x050000A4) 62 #define STM32MP153D_PART_NB U(0x050000A5) 63 #define STM32MP151F_PART_NB U(0x050000AE) 64 #define STM32MP151D_PART_NB U(0x050000AF) 65 #endif 66 67 #define STM32MP1_REV_B U(0x2000) 68 #if STM32MP13 69 #define STM32MP1_REV_Y U(0x1003) 70 #define STM32MP1_REV_Z U(0x1001) 71 #endif 72 #if STM32MP15 73 #define STM32MP1_REV_Z U(0x2001) 74 #endif 75 76 /******************************************************************************* 77 * PACKAGE ID 78 ******************************************************************************/ 79 #if STM32MP15 80 #define PKG_AA_LFBGA448 U(4) 81 #define PKG_AB_LFBGA354 U(3) 82 #define PKG_AC_TFBGA361 U(2) 83 #define PKG_AD_TFBGA257 U(1) 84 #endif 85 86 /******************************************************************************* 87 * STM32MP1 memory map related constants 88 ******************************************************************************/ 89 #define STM32MP_ROM_BASE U(0x00000000) 90 #define STM32MP_ROM_SIZE U(0x00020000) 91 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000) 92 93 #if STM32MP13 94 #define STM32MP_SYSRAM_BASE U(0x2FFE0000) 95 #define STM32MP_SYSRAM_SIZE U(0x00020000) 96 #define SRAM1_BASE U(0x30000000) 97 #define SRAM1_SIZE U(0x00004000) 98 #define SRAM2_BASE U(0x30004000) 99 #define SRAM2_SIZE U(0x00002000) 100 #define SRAM3_BASE U(0x30006000) 101 #define SRAM3_SIZE U(0x00002000) 102 #define SRAMS_BASE SRAM1_BASE 103 #define SRAMS_SIZE_2MB_ALIGNED U(0x00200000) 104 #endif /* STM32MP13 */ 105 #if STM32MP15 106 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 107 #define STM32MP_SYSRAM_SIZE U(0x00040000) 108 #endif /* STM32MP15 */ 109 110 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE 111 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \ 112 STM32MP_SYSRAM_SIZE - \ 113 STM32MP_NS_SYSRAM_SIZE) 114 115 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE 116 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE 117 118 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 119 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \ 120 STM32MP_NS_SYSRAM_SIZE) 121 122 /* DDR configuration */ 123 #define STM32MP_DDR_BASE U(0xC0000000) 124 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 125 126 /* DDR power initializations */ 127 #ifndef __ASSEMBLER__ 128 enum ddr_type { 129 STM32MP_DDR3, 130 STM32MP_LPDDR2, 131 STM32MP_LPDDR3 132 }; 133 #endif 134 135 /* Section used inside TF binaries */ 136 #if STM32MP13 137 /* 512 Octets reserved for header */ 138 #define STM32MP_HEADER_RESERVED_SIZE U(0x200) 139 140 #define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE 141 142 #define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE 143 #endif 144 #if STM32MP15 145 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 146 /* 256 Octets reserved for header */ 147 #define STM32MP_HEADER_SIZE U(0x00000100) 148 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 149 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 150 151 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \ 152 STM32MP_PARAM_LOAD_SIZE + \ 153 STM32MP_HEADER_SIZE) 154 155 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 156 (STM32MP_PARAM_LOAD_SIZE + \ 157 STM32MP_HEADER_SIZE)) 158 #endif 159 160 /* BL2 and BL32/sp_min require finer granularity tables */ 161 #if defined(IMAGE_BL2) 162 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */ 163 #endif 164 165 #if defined(IMAGE_BL32) 166 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 167 #endif 168 169 /* 170 * MAX_MMAP_REGIONS is usually: 171 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 172 */ 173 #if defined(IMAGE_BL2) 174 #if STM32MP_USB_PROGRAMMER 175 #define MAX_MMAP_REGIONS 8 176 #else 177 #define MAX_MMAP_REGIONS 7 178 #endif 179 #endif 180 181 #if STM32MP13 182 #define STM32MP_BL33_BASE STM32MP_DDR_BASE 183 #endif 184 #if STM32MP15 185 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 186 #endif 187 #define STM32MP_BL33_MAX_SIZE U(0x400000) 188 189 /* Define maximum page size for NAND devices */ 190 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000) 191 192 /* Define location for the MTD scratch buffer */ 193 #if STM32MP13 194 #define STM32MP_MTD_BUFFER (SRAM1_BASE + \ 195 SRAM1_SIZE - \ 196 PLATFORM_MTD_MAX_PAGE_SIZE) 197 #endif 198 /******************************************************************************* 199 * STM32MP1 device/io map related constants (used for MMU) 200 ******************************************************************************/ 201 #define STM32MP1_DEVICE1_BASE U(0x40000000) 202 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 203 204 #define STM32MP1_DEVICE2_BASE U(0x80000000) 205 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 206 207 /******************************************************************************* 208 * STM32MP1 RCC 209 ******************************************************************************/ 210 #define RCC_BASE U(0x50000000) 211 212 /******************************************************************************* 213 * STM32MP1 PWR 214 ******************************************************************************/ 215 #define PWR_BASE U(0x50001000) 216 217 /******************************************************************************* 218 * STM32MP1 GPIO 219 ******************************************************************************/ 220 #define GPIOA_BASE U(0x50002000) 221 #define GPIOB_BASE U(0x50003000) 222 #define GPIOC_BASE U(0x50004000) 223 #define GPIOD_BASE U(0x50005000) 224 #define GPIOE_BASE U(0x50006000) 225 #define GPIOF_BASE U(0x50007000) 226 #define GPIOG_BASE U(0x50008000) 227 #define GPIOH_BASE U(0x50009000) 228 #define GPIOI_BASE U(0x5000A000) 229 #if STM32MP15 230 #define GPIOJ_BASE U(0x5000B000) 231 #define GPIOK_BASE U(0x5000C000) 232 #define GPIOZ_BASE U(0x54004000) 233 #endif 234 #define GPIO_BANK_OFFSET U(0x1000) 235 236 /* Bank IDs used in GPIO driver API */ 237 #define GPIO_BANK_A U(0) 238 #define GPIO_BANK_B U(1) 239 #define GPIO_BANK_C U(2) 240 #define GPIO_BANK_D U(3) 241 #define GPIO_BANK_E U(4) 242 #define GPIO_BANK_F U(5) 243 #define GPIO_BANK_G U(6) 244 #define GPIO_BANK_H U(7) 245 #define GPIO_BANK_I U(8) 246 #if STM32MP15 247 #define GPIO_BANK_J U(9) 248 #define GPIO_BANK_K U(10) 249 #define GPIO_BANK_Z U(25) 250 251 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 252 #endif 253 254 /******************************************************************************* 255 * STM32MP1 UART 256 ******************************************************************************/ 257 #if STM32MP13 258 #define USART1_BASE U(0x4C000000) 259 #define USART2_BASE U(0x4C001000) 260 #endif 261 #if STM32MP15 262 #define USART1_BASE U(0x5C000000) 263 #define USART2_BASE U(0x4000E000) 264 #endif 265 #define USART3_BASE U(0x4000F000) 266 #define UART4_BASE U(0x40010000) 267 #define UART5_BASE U(0x40011000) 268 #define USART6_BASE U(0x44003000) 269 #define UART7_BASE U(0x40018000) 270 #define UART8_BASE U(0x40019000) 271 272 /* For UART crash console */ 273 #define STM32MP_DEBUG_USART_BASE UART4_BASE 274 #if STM32MP13 275 /* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */ 276 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 277 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE 278 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR 279 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN 280 #define DEBUG_UART_TX_GPIO_PORT 6 281 #define DEBUG_UART_TX_GPIO_ALTERNATE 8 282 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR 283 #define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI 284 #endif /* STM32MP13 */ 285 #if STM32MP15 286 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 287 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 288 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 289 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 290 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 291 #define DEBUG_UART_TX_GPIO_PORT 11 292 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 293 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 294 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 295 #endif /* STM32MP15 */ 296 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 297 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 298 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR 299 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST 300 301 /******************************************************************************* 302 * STM32MP1 ETZPC 303 ******************************************************************************/ 304 #define STM32MP1_ETZPC_BASE U(0x5C007000) 305 306 /* ETZPC TZMA IDs */ 307 #define STM32MP1_ETZPC_TZMA_ROM U(0) 308 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1) 309 310 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0) 311 312 /* ETZPC DECPROT IDs */ 313 #define STM32MP1_ETZPC_STGENC_ID 0 314 #define STM32MP1_ETZPC_BKPSRAM_ID 1 315 #define STM32MP1_ETZPC_IWDG1_ID 2 316 #define STM32MP1_ETZPC_USART1_ID 3 317 #define STM32MP1_ETZPC_SPI6_ID 4 318 #define STM32MP1_ETZPC_I2C4_ID 5 319 #define STM32MP1_ETZPC_RNG1_ID 7 320 #define STM32MP1_ETZPC_HASH1_ID 8 321 #define STM32MP1_ETZPC_CRYP1_ID 9 322 #define STM32MP1_ETZPC_DDRCTRL_ID 10 323 #define STM32MP1_ETZPC_DDRPHYC_ID 11 324 #define STM32MP1_ETZPC_I2C6_ID 12 325 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13 326 327 #define STM32MP1_ETZPC_TIM2_ID 16 328 #define STM32MP1_ETZPC_TIM3_ID 17 329 #define STM32MP1_ETZPC_TIM4_ID 18 330 #define STM32MP1_ETZPC_TIM5_ID 19 331 #define STM32MP1_ETZPC_TIM6_ID 20 332 #define STM32MP1_ETZPC_TIM7_ID 21 333 #define STM32MP1_ETZPC_TIM12_ID 22 334 #define STM32MP1_ETZPC_TIM13_ID 23 335 #define STM32MP1_ETZPC_TIM14_ID 24 336 #define STM32MP1_ETZPC_LPTIM1_ID 25 337 #define STM32MP1_ETZPC_WWDG1_ID 26 338 #define STM32MP1_ETZPC_SPI2_ID 27 339 #define STM32MP1_ETZPC_SPI3_ID 28 340 #define STM32MP1_ETZPC_SPDIFRX_ID 29 341 #define STM32MP1_ETZPC_USART2_ID 30 342 #define STM32MP1_ETZPC_USART3_ID 31 343 #define STM32MP1_ETZPC_UART4_ID 32 344 #define STM32MP1_ETZPC_UART5_ID 33 345 #define STM32MP1_ETZPC_I2C1_ID 34 346 #define STM32MP1_ETZPC_I2C2_ID 35 347 #define STM32MP1_ETZPC_I2C3_ID 36 348 #define STM32MP1_ETZPC_I2C5_ID 37 349 #define STM32MP1_ETZPC_CEC_ID 38 350 #define STM32MP1_ETZPC_DAC_ID 39 351 #define STM32MP1_ETZPC_UART7_ID 40 352 #define STM32MP1_ETZPC_UART8_ID 41 353 #define STM32MP1_ETZPC_MDIOS_ID 44 354 #define STM32MP1_ETZPC_TIM1_ID 48 355 #define STM32MP1_ETZPC_TIM8_ID 49 356 #define STM32MP1_ETZPC_USART6_ID 51 357 #define STM32MP1_ETZPC_SPI1_ID 52 358 #define STM32MP1_ETZPC_SPI4_ID 53 359 #define STM32MP1_ETZPC_TIM15_ID 54 360 #define STM32MP1_ETZPC_TIM16_ID 55 361 #define STM32MP1_ETZPC_TIM17_ID 56 362 #define STM32MP1_ETZPC_SPI5_ID 57 363 #define STM32MP1_ETZPC_SAI1_ID 58 364 #define STM32MP1_ETZPC_SAI2_ID 59 365 #define STM32MP1_ETZPC_SAI3_ID 60 366 #define STM32MP1_ETZPC_DFSDM_ID 61 367 #define STM32MP1_ETZPC_TT_FDCAN_ID 62 368 #define STM32MP1_ETZPC_LPTIM2_ID 64 369 #define STM32MP1_ETZPC_LPTIM3_ID 65 370 #define STM32MP1_ETZPC_LPTIM4_ID 66 371 #define STM32MP1_ETZPC_LPTIM5_ID 67 372 #define STM32MP1_ETZPC_SAI4_ID 68 373 #define STM32MP1_ETZPC_VREFBUF_ID 69 374 #define STM32MP1_ETZPC_DCMI_ID 70 375 #define STM32MP1_ETZPC_CRC2_ID 71 376 #define STM32MP1_ETZPC_ADC_ID 72 377 #define STM32MP1_ETZPC_HASH2_ID 73 378 #define STM32MP1_ETZPC_RNG2_ID 74 379 #define STM32MP1_ETZPC_CRYP2_ID 75 380 #define STM32MP1_ETZPC_SRAM1_ID 80 381 #define STM32MP1_ETZPC_SRAM2_ID 81 382 #define STM32MP1_ETZPC_SRAM3_ID 82 383 #define STM32MP1_ETZPC_SRAM4_ID 83 384 #define STM32MP1_ETZPC_RETRAM_ID 84 385 #define STM32MP1_ETZPC_OTG_ID 85 386 #define STM32MP1_ETZPC_SDMMC3_ID 86 387 #define STM32MP1_ETZPC_DLYBSD3_ID 87 388 #define STM32MP1_ETZPC_DMA1_ID 88 389 #define STM32MP1_ETZPC_DMA2_ID 89 390 #define STM32MP1_ETZPC_DMAMUX_ID 90 391 #define STM32MP1_ETZPC_FMC_ID 91 392 #define STM32MP1_ETZPC_QSPI_ID 92 393 #define STM32MP1_ETZPC_DLYBQ_ID 93 394 #define STM32MP1_ETZPC_ETH_ID 94 395 #define STM32MP1_ETZPC_RSV_ID 95 396 397 #define STM32MP_ETZPC_MAX_ID 96 398 399 /******************************************************************************* 400 * STM32MP1 TZC (TZ400) 401 ******************************************************************************/ 402 #define STM32MP1_TZC_BASE U(0x5C006000) 403 404 #if STM32MP13 405 #define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0) 406 #endif 407 #if STM32MP15 408 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \ 409 TZC_400_REGION_ATTR_FILTER_BIT(1)) 410 #endif 411 412 /******************************************************************************* 413 * STM32MP1 SDMMC 414 ******************************************************************************/ 415 #define STM32MP_SDMMC1_BASE U(0x58005000) 416 #define STM32MP_SDMMC2_BASE U(0x58007000) 417 #define STM32MP_SDMMC3_BASE U(0x48004000) 418 419 /******************************************************************************* 420 * STM32MP1 BSEC / OTP 421 ******************************************************************************/ 422 #define STM32MP1_OTP_MAX_ID 0x5FU 423 #define STM32MP1_UPPER_OTP_START 0x20U 424 425 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 426 427 /* OTP labels */ 428 #define CFG0_OTP "cfg0_otp" 429 #define PART_NUMBER_OTP "part_number_otp" 430 #if STM32MP15 431 #define PACKAGE_OTP "package_otp" 432 #endif 433 #define HW2_OTP "hw2_otp" 434 #if STM32MP13 435 #define NAND_OTP "cfg9_otp" 436 #define NAND2_OTP "cfg10_otp" 437 #endif 438 #if STM32MP15 439 #define NAND_OTP "nand_otp" 440 #endif 441 #define MONOTONIC_OTP "monotonic_otp" 442 #define UID_OTP "uid_otp" 443 #define PKH_OTP "pkh_otp" 444 #define ENCKEY_OTP "enckey_otp" 445 #define BOARD_ID_OTP "board_id" 446 447 /* OTP mask */ 448 /* CFG0 */ 449 #if STM32MP13 450 #define CFG0_OTP_MODE_MASK GENMASK_32(9, 0) 451 #define CFG0_OTP_MODE_SHIFT 0 452 #define CFG0_OPEN_DEVICE 0x17U 453 #define CFG0_CLOSED_DEVICE 0x3FU 454 #define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU 455 #define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU 456 #endif 457 #if STM32MP15 458 #define CFG0_CLOSED_DEVICE BIT(6) 459 #endif 460 461 /* PART NUMBER */ 462 #if STM32MP13 463 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0) 464 #endif 465 #if STM32MP15 466 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 467 #endif 468 #define PART_NUMBER_OTP_PART_SHIFT 0 469 470 /* PACKAGE */ 471 #if STM32MP15 472 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 473 #define PACKAGE_OTP_PKG_SHIFT 27 474 #endif 475 476 /* IWDG OTP */ 477 #define HW2_OTP_IWDG_HW_POS U(3) 478 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 479 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 480 481 /* HW2 OTP */ 482 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 483 484 /* NAND OTP */ 485 /* NAND parameter storage flag */ 486 #define NAND_PARAM_STORED_IN_OTP BIT(31) 487 488 /* NAND page size in bytes */ 489 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 490 #define NAND_PAGE_SIZE_SHIFT 29 491 #define NAND_PAGE_SIZE_2K U(0) 492 #define NAND_PAGE_SIZE_4K U(1) 493 #define NAND_PAGE_SIZE_8K U(2) 494 495 /* NAND block size in pages */ 496 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 497 #define NAND_BLOCK_SIZE_SHIFT 27 498 #define NAND_BLOCK_SIZE_64_PAGES U(0) 499 #define NAND_BLOCK_SIZE_128_PAGES U(1) 500 #define NAND_BLOCK_SIZE_256_PAGES U(2) 501 502 /* NAND number of block (in unit of 256 blocks) */ 503 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 504 #define NAND_BLOCK_NB_SHIFT 19 505 #define NAND_BLOCK_NB_UNIT U(256) 506 507 /* NAND bus width in bits */ 508 #define NAND_WIDTH_MASK BIT(18) 509 #define NAND_WIDTH_SHIFT 18 510 511 /* NAND number of ECC bits per 512 bytes */ 512 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 513 #define NAND_ECC_BIT_NB_SHIFT 15 514 #define NAND_ECC_BIT_NB_UNSET U(0) 515 #define NAND_ECC_BIT_NB_1_BITS U(1) 516 #define NAND_ECC_BIT_NB_4_BITS U(2) 517 #define NAND_ECC_BIT_NB_8_BITS U(3) 518 #define NAND_ECC_ON_DIE U(4) 519 520 /* NAND number of planes */ 521 #define NAND_PLANE_BIT_NB_MASK BIT(14) 522 523 /* NAND2 OTP */ 524 #define NAND2_PAGE_SIZE_SHIFT 16 525 526 /* NAND2 config distribution */ 527 #define NAND2_CONFIG_DISTRIB BIT(0) 528 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 529 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 530 531 /* MONOTONIC OTP */ 532 #define MAX_MONOTONIC_VALUE 32 533 534 /* UID OTP */ 535 #define UID_WORD_NB U(3) 536 537 /* FWU configuration (max supported value is 15) */ 538 #define FWU_MAX_TRIAL_REBOOT U(3) 539 540 /******************************************************************************* 541 * STM32MP1 TAMP 542 ******************************************************************************/ 543 #define TAMP_BASE U(0x5C00A000) 544 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 545 #define TAMP_BKP_REG_CLK RTCAPB 546 #define TAMP_COUNTR U(0x40) 547 548 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 549 static inline uintptr_t tamp_bkpr(uint32_t idx) 550 { 551 return TAMP_BKP_REGISTER_BASE + (idx << 2); 552 } 553 #endif 554 555 /******************************************************************************* 556 * STM32MP1 USB 557 ******************************************************************************/ 558 #define USB_OTG_BASE U(0x49000000) 559 560 /******************************************************************************* 561 * STM32MP1 DDRCTRL 562 ******************************************************************************/ 563 #define DDRCTRL_BASE U(0x5A003000) 564 565 /******************************************************************************* 566 * STM32MP1 DDRPHYC 567 ******************************************************************************/ 568 #define DDRPHYC_BASE U(0x5A004000) 569 570 /******************************************************************************* 571 * STM32MP1 IWDG 572 ******************************************************************************/ 573 #define IWDG_MAX_INSTANCE U(2) 574 #define IWDG1_INST U(0) 575 #define IWDG2_INST U(1) 576 577 #define IWDG1_BASE U(0x5C003000) 578 #define IWDG2_BASE U(0x5A002000) 579 580 /******************************************************************************* 581 * Miscellaneous STM32MP1 peripherals base address 582 ******************************************************************************/ 583 #define BSEC_BASE U(0x5C005000) 584 #if STM32MP13 585 #define CRYP_BASE U(0x54002000) 586 #endif 587 #if STM32MP15 588 #define CRYP1_BASE U(0x54001000) 589 #endif 590 #define DBGMCU_BASE U(0x50081000) 591 #if STM32MP13 592 #define HASH_BASE U(0x54003000) 593 #endif 594 #if STM32MP15 595 #define HASH1_BASE U(0x54002000) 596 #endif 597 #if STM32MP13 598 #define I2C3_BASE U(0x4C004000) 599 #define I2C4_BASE U(0x4C005000) 600 #define I2C5_BASE U(0x4C006000) 601 #endif 602 #if STM32MP15 603 #define I2C4_BASE U(0x5C002000) 604 #define I2C6_BASE U(0x5c009000) 605 #endif 606 #if STM32MP13 607 #define RNG_BASE U(0x54004000) 608 #endif 609 #if STM32MP15 610 #define RNG1_BASE U(0x54003000) 611 #endif 612 #define RTC_BASE U(0x5c004000) 613 #if STM32MP13 614 #define SPI4_BASE U(0x4C002000) 615 #define SPI5_BASE U(0x4C003000) 616 #endif 617 #if STM32MP15 618 #define SPI6_BASE U(0x5c001000) 619 #endif 620 #define STGEN_BASE U(0x5c008000) 621 #define SYSCFG_BASE U(0x50020000) 622 623 /******************************************************************************* 624 * STM32MP13 SAES 625 ******************************************************************************/ 626 #define SAES_BASE U(0x54005000) 627 628 /******************************************************************************* 629 * STM32MP13 PKA 630 ******************************************************************************/ 631 #define PKA_BASE U(0x54006000) 632 633 /******************************************************************************* 634 * REGULATORS 635 ******************************************************************************/ 636 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 637 #define PLAT_NB_RDEVS U(19) 638 /* 2 FIXED */ 639 #define PLAT_NB_FIXED_REGS U(2) 640 641 /******************************************************************************* 642 * Device Tree defines 643 ******************************************************************************/ 644 #if STM32MP13 645 #define DT_BSEC_COMPAT "st,stm32mp13-bsec" 646 #define DT_DDR_COMPAT "st,stm32mp13-ddr" 647 #endif 648 #if STM32MP15 649 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 650 #define DT_DDR_COMPAT "st,stm32mp1-ddr" 651 #endif 652 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 653 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" 654 #if STM32MP13 655 #define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc" 656 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure" 657 #endif 658 #if STM32MP15 659 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 660 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure" 661 #endif 662 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 663 #define DT_UART_COMPAT "st,stm32h7-uart" 664 665 #endif /* STM32MP1_DEF_H */ 666