1 /* 2 * Copyright (c) 2023, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #include <dt-bindings/clock/stm32mp25-clks.h> 16 #include <dt-bindings/clock/stm32mp25-clksrc.h> 17 #include <dt-bindings/reset/stm32mp25-resets.h> 18 19 #ifndef __ASSEMBLER__ 20 #include <boot_api.h> 21 #include <stm32mp_common.h> 22 #include <stm32mp_dt.h> 23 #include <stm32mp_shared_resources.h> 24 #endif 25 26 /******************************************************************************* 27 * STM32MP2 memory map related constants 28 ******************************************************************************/ 29 #define STM32MP_SYSRAM_BASE U(0x0E000000) 30 #define STM32MP_SYSRAM_SIZE U(0x00040000) 31 32 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE 33 #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE 34 35 /* DDR configuration */ 36 #define STM32MP_DDR_BASE U(0x80000000) 37 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 38 39 /* DDR power initializations */ 40 #ifndef __ASSEMBLER__ 41 enum ddr_type { 42 STM32MP_DDR3, 43 STM32MP_DDR4, 44 STM32MP_LPDDR4 45 }; 46 #endif 47 48 #define STM32MP_BL2_SIZE U(0x0002A000) /* 168 KB for BL2 */ 49 50 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 51 STM32MP_SEC_SYSRAM_SIZE - \ 52 STM32MP_BL2_SIZE) 53 54 /* BL2 and BL32/sp_min require 4 tables */ 55 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 56 57 /* 58 * MAX_MMAP_REGIONS is usually: 59 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 60 */ 61 #define MAX_MMAP_REGIONS 6 62 63 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 64 #define STM32MP_BL33_MAX_SIZE U(0x400000) 65 66 /******************************************************************************* 67 * STM32MP2 RCC 68 ******************************************************************************/ 69 #define RCC_BASE U(0x44200000) 70 71 /******************************************************************************* 72 * STM32MP2 PWR 73 ******************************************************************************/ 74 #define PWR_BASE U(0x44210000) 75 76 /******************************************************************************* 77 * STM32MP2 GPIO 78 ******************************************************************************/ 79 #define GPIOA_BASE U(0x44240000) 80 #define GPIOB_BASE U(0x44250000) 81 #define GPIOC_BASE U(0x44260000) 82 #define GPIOD_BASE U(0x44270000) 83 #define GPIOE_BASE U(0x44280000) 84 #define GPIOF_BASE U(0x44290000) 85 #define GPIOG_BASE U(0x442A0000) 86 #define GPIOH_BASE U(0x442B0000) 87 #define GPIOI_BASE U(0x442C0000) 88 #define GPIOJ_BASE U(0x442D0000) 89 #define GPIOK_BASE U(0x442E0000) 90 #define GPIOZ_BASE U(0x46200000) 91 #define GPIO_BANK_OFFSET U(0x10000) 92 93 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 94 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 95 96 /******************************************************************************* 97 * STM32MP2 UART 98 ******************************************************************************/ 99 #define USART1_BASE U(0x40330000) 100 #define USART2_BASE U(0x400E0000) 101 #define USART3_BASE U(0x400F0000) 102 #define UART4_BASE U(0x40100000) 103 #define UART5_BASE U(0x40110000) 104 #define USART6_BASE U(0x40220000) 105 #define UART7_BASE U(0x40370000) 106 #define UART8_BASE U(0x40380000) 107 #define UART9_BASE U(0x402C0000) 108 #define STM32MP_NB_OF_UART U(9) 109 110 /* For UART crash console */ 111 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 112 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 113 #define STM32MP_DEBUG_USART_BASE USART2_BASE 114 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 115 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 116 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 117 #define DEBUG_UART_TX_GPIO_PORT 4 118 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 119 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 120 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 121 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 122 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 123 #define DEBUG_UART_RST_REG RCC_USART2CFGR 124 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 125 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 126 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 127 128 /******************************************************************************* 129 * STM32MP2 SDMMC 130 ******************************************************************************/ 131 #define STM32MP_SDMMC1_BASE U(0x48220000) 132 #define STM32MP_SDMMC2_BASE U(0x48230000) 133 #define STM32MP_SDMMC3_BASE U(0x48240000) 134 135 /******************************************************************************* 136 * STM32MP2 TAMP 137 ******************************************************************************/ 138 #define PLAT_MAX_TAMP_INT U(5) 139 #define PLAT_MAX_TAMP_EXT U(3) 140 #define TAMP_BASE U(0x46010000) 141 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 142 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 143 #define TAMP_BKP_REG_CLK CK_BUS_RTC 144 #define TAMP_BKP_SEC_NUMBER U(10) 145 #define TAMP_COUNTR U(0x40) 146 147 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 148 static inline uintptr_t tamp_bkpr(uint32_t idx) 149 { 150 return TAMP_BKP_REGISTER_BASE + (idx << 2); 151 } 152 #endif 153 154 /******************************************************************************* 155 * STM32MP2 DDRCTRL 156 ******************************************************************************/ 157 #define DDRCTRL_BASE U(0x48040000) 158 159 /******************************************************************************* 160 * STM32MP2 DDRDBG 161 ******************************************************************************/ 162 #define DDRDBG_BASE U(0x48050000) 163 164 /******************************************************************************* 165 * STM32MP2 DDRPHYC 166 ******************************************************************************/ 167 #define DDRPHYC_BASE U(0x48C00000) 168 169 /******************************************************************************* 170 * Miscellaneous STM32MP1 peripherals base address 171 ******************************************************************************/ 172 #define BSEC_BASE U(0x44000000) 173 #define DBGMCU_BASE U(0x4A010000) 174 #define HASH_BASE U(0x42010000) 175 #define RTC_BASE U(0x46000000) 176 #define STGEN_BASE U(0x48080000) 177 #define SYSCFG_BASE U(0x44230000) 178 179 /******************************************************************************* 180 * REGULATORS 181 ******************************************************************************/ 182 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 183 #define PLAT_NB_RDEVS U(19) 184 /* 2 FIXED */ 185 #define PLAT_NB_FIXED_REGUS U(2) 186 /* No GPIO regu */ 187 #define PLAT_NB_GPIO_REGUS U(0) 188 189 /******************************************************************************* 190 * Device Tree defines 191 ******************************************************************************/ 192 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 193 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 194 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 195 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 196 #define DT_UART_COMPAT "st,stm32h7-uart" 197 198 #endif /* STM32MP2_DEF_H */ 199